93182 Commits

Author SHA1 Message Date
Ulrich Weigand
824b7d8dfd [PowerPC] Support generic conditional branches in asm parser
This adds instruction patterns to cover the generic forms of
the conditional branch instructions.  This allows the assembler
to support the generic mnemonics.

The compiler will still generate the various specific forms
of the instruction that were already supported.

llvm-svn: 184722
2013-06-24 11:55:21 +00:00
Ulrich Weigand
b6a30d159e [PowerPC] Support absolute branches
There is currently only limited support for the "absolute" variants
of branch instructions.  This patch adds support for the absolute
variants of all branches that are currently otherwise supported.

This requires adding new fixup types so that the correct variant
of relocation type can be selected by the object writer.

While the compiler will continue to usually choose the relative
branch variants, this will allow the asm parser to fully support
the absolute branches, with either immediate (numerical) or
symbolic target addresses.

No change in code generation intended.

llvm-svn: 184721
2013-06-24 11:03:33 +00:00
Ulrich Weigand
5b9d591ad1 [PowerPC] Support bd(n)zl and bd(n)zlrl
This adds support for the bd(n)zl and bd(n)zlrl instructions.
The patterns are currently used for the asm parser only.

llvm-svn: 184720
2013-06-24 11:02:38 +00:00
Ulrich Weigand
d20e91edad [PowerPC] Support b(cond)l in the asm parser
This patch adds support for the conditional variants of bl.
The pattern is currently used by the asm parser only.

llvm-svn: 184719
2013-06-24 11:02:19 +00:00
Ulrich Weigand
1847bb811e [PowerPC] Support blrl and variants in the asm parser
This patch adds support for blrl and its conditional variants.
The patterns are (currently) used for the asm parser only.

llvm-svn: 184718
2013-06-24 11:01:55 +00:00
Vladimir Medic
233dd51b13 This patch introduces RegisterOperand class into Mips FPU instruction definitions and adds dedicated parser methods to MipsAsmParser. It is the first in a series of patches that should fix the problems with parsing Mips FPU instructions and optimize the code in MipsAsmParser.
llvm-svn: 184716
2013-06-24 10:05:34 +00:00
Michael Gottesman
f989929cf0 [APFloat] Removed trailing whitespace from unittests.
llvm-svn: 184715
2013-06-24 09:58:09 +00:00
Michael Gottesman
e45b108339 [APFloat] Added a large unittest for APFloat.add that checks that special values are computed correctly.
llvm-svn: 184714
2013-06-24 09:58:07 +00:00
Michael Gottesman
40e8a187f6 [APFloat] Added support for parsing float strings which contain {inf,-inf,NaN,-NaN}.
llvm-svn: 184713
2013-06-24 09:58:05 +00:00
Michael Gottesman
c4facdf390 [APFloat] Added make{Zero,Inf} methods and implemented get{Zero,Inf} on top of them.
llvm-svn: 184712
2013-06-24 09:58:02 +00:00
Michael Gottesman
f0e8cd1a7f [APFloat] Removed a assert from significandParts() which says that one can only access the significand of FiniteNonZero/NaN floats.
The method significandParts() is a helper method meant to ease access to
APFloat's significand by allowing the user to not need to be aware of whether or
not the APFloat is using memory allocated in the instance itself or in an
external array.

This assert says that one can only access the significand of FiniteNonZero/NaN
floats. This makes it cumbersome and more importantly dangerous when one wishes
to zero out the significand of a zero/infinity value since one will have to deal
with the aforementioned quandary related to how the memory in APFloat is
allocated.

llvm-svn: 184711
2013-06-24 09:57:59 +00:00
Michael Gottesman
9b877e18a3 [APFloat] Rename macro convolve => PackCategoriesIntoKey so that it is clear what APFloat is actually using said macro for.
In the context of APFloat, seeing a macro called convolve suggests that APFloat
is using said value in some sort of convolution somewhere in the source code.
This is misleading.

I also added a documentation comment to the macro.

llvm-svn: 184710
2013-06-24 09:57:57 +00:00
Andrew Trick
c08bd450a3 Add -mcpu to some unit tests that only fail on certain hosts.
llvm-svn: 184709
2013-06-24 09:51:30 +00:00
Amaury de la Vieuville
8449c0d5ed ARM: check predicate bits for thumb instructions
When encoded to thumb, VFP instruction and VMOV/VDUP between scalar and
core registers, must have their predicate bit to 0b1110.

llvm-svn: 184707
2013-06-24 09:15:01 +00:00
Amaury de la Vieuville
8175bda3db ARM: rGPR is meant to be unpredictable, not undefined
llvm-svn: 184706
2013-06-24 09:14:54 +00:00
Andrew Trick
5a1e0af838 Temporarily enable MI-Sched on X86.
Sorry for the unit test churn. I'll try to make the change permanently
next time.

llvm-svn: 184705
2013-06-24 09:13:20 +00:00
Amaury de la Vieuville
f2f00b4e28 ARM: fix thumb1 nop decoding
In thumb1, NOP is a pseudo-instruction equivalent to mov r8, r8.
However the disassembler should not use this alias.

llvm-svn: 184703
2013-06-24 09:11:53 +00:00
Amaury de la Vieuville
2f0ac8d961 ARM: fix IT decoding
mask == 0 -> UNPRED

llvm-svn: 184702
2013-06-24 09:11:45 +00:00
Amaury de la Vieuville
4b6c076da3 ARM: enable decoding of pc-relative PLD/PLI
llvm-svn: 184701
2013-06-24 09:11:38 +00:00
Chandler Carruth
08e1b8742b Add a flag to defer vectorization into a phase after the inliner and its
CGSCC pass manager. This should insulate the inlining decisions from the
vectorization decisions, however it may have both compile time and code
size problems so it is just an experimental option right now.

Adding this based on a discussion with Arnold and it seems at least
worth having this flag for us to both run some experiments to see if
this strategy is workable. It may solve some of the regressions seen
with the loop vectorizer.

llvm-svn: 184698
2013-06-24 07:21:47 +00:00
Chandler Carruth
99c46b980f Filter out dragonegg when checked out into a projects subdirectory.
There is some hope of eventually supporting a unified build with it, but
until then this lets me (and others) check it out in this location
without things breaking.

llvm-svn: 184697
2013-06-24 07:21:35 +00:00
David Blaikie
6225137470 DebugInfo: enumerator values returned as int64 as they are stored
llvm-svn: 184694
2013-06-24 07:11:08 +00:00
David Blaikie
3656123dfc DebugInfo: add some testing from an overly broad end-to-end test in Clang
llvm-svn: 184692
2013-06-24 06:47:22 +00:00
Arnold Schwaighofer
58ca945f38 Revert "LoopVectorize: Use the dependence test utility class"
This reverts commit cbfa1ca993363ca5c4dbf6c913abc957c584cbac.

We are seeing a stage2 and stage3 miscompare on some dragonegg bots.

llvm-svn: 184690
2013-06-24 06:10:41 +00:00
Michael Gottesman
d851ea068c [APFloat] Removed out of date comment from isNormal().
I already finished the isIEEENormal => isNormal transition. So isNormal is now
IEEE-754R compliant.

llvm-svn: 184687
2013-06-24 04:19:37 +00:00
Michael Gottesman
9dc98338b8 [APFloat] Rename llvm::exponent_t => llvm::APFloat::ExponentType.
exponent_t is only used internally in APFloat and no exponent_t values are
exposed via the APFloat API. In light of such conditions it does not make any
sense to gum up the llvm namespace with said type. Plus it makes it clearer that
exponent_t is associated with APFloat.

llvm-svn: 184686
2013-06-24 04:06:23 +00:00
Arnold Schwaighofer
b914a7e2ef LoopVectorize: Use the dependence test utility class
We now no longer need alias analysis - the cases that alias analysis would
handle are now handled as accesses with a large dependence distance.

We can now vectorize loops with simple constant dependence distances.

  for (i = 8; i < 256; ++i) {
    a[i] = a[i+4] * a[i+8];
  }

  for (i = 8; i < 256; ++i) {
    a[i] = a[i-4] * a[i-8];
  }

We would be able to vectorize about 200 more loops (in many cases the cost model
instructs us no to) in the test suite now. Results on x86-64 are a wash.

I have seen one degradation in ammp. Interestingly, the function in which we
now vectorize a loop is never executed so we probably see some instruction
cache effects. There is a 2% improvement in h264ref. There is one or the other
TSCV loop kernel that speeds up.

radar://13681598

llvm-svn: 184685
2013-06-24 03:55:48 +00:00
Arnold Schwaighofer
d517976758 LoopVectorize: Add utility class for checking dependency among accesses
This class checks dependences by subtracting two Scalar Evolution access
functions allowing us to catch very simple linear dependences.

The checker assumes source order in determining whether vectorization is safe.
We currently don't reorder accesses.
Positive true dependencies need to be a multiple of VF otherwise we impede
store-load forwarding.

llvm-svn: 184684
2013-06-24 03:55:45 +00:00
Arnold Schwaighofer
d57419696d LoopVectorize: Add utility class for building sets of dependent accesses
Sets of dependent accesses are built by unioning sets based on underlying
objects. This class will be used by the upcoming dependence checker.

llvm-svn: 184683
2013-06-24 03:55:44 +00:00
Nadav Rotem
210e86d7c4 SLP Vectorizer: Add support for vectorizing parts of the tree.
Untill now we detected the vectorizable tree and evaluated the cost of the
entire tree.  With this patch we can decide to trim-out branches of the tree
that are not profitable to vectorizer.

Also, increase the max depth from 6 to 12. In the worse possible case where all
of the code is made of diamond-shaped graph this can bring the cost to 2**10,
but diamonds are not very common.

llvm-svn: 184681
2013-06-24 02:52:43 +00:00
Andrew Trick
97a1d7c475 Fix tail merging to assign the (more) correct BasicBlock when splitting.
This makes it possible to write unit tests that are less susceptible
to minor code motion, particularly copy placement. block-placement.ll
covers this case with -pre-RA-sched=source which will soon be
default. One incorrectly named block is already fixed, but without
this fix, enabling new coalescing and scheduling would cause more
failures.

llvm-svn: 184680
2013-06-24 01:55:01 +00:00
Nadav Rotem
0323925d51 SLP Vectorizer: Fix a bug in the code that does CSE on the generated gather sequences.
Make sure that we don't replace and RAUW two sequences if one does not dominate the other.

llvm-svn: 184674
2013-06-23 21:57:27 +00:00
Nadav Rotem
78428401e9 SLP Vectorizer: Erase instructions outside the vectorizeTree method.
The RAII builder location guard is saving a reference to instructions, so we can't erase instructions during vectorization.

llvm-svn: 184671
2013-06-23 19:38:56 +00:00
David Blaikie
5acff7e691 DebugInfo: PR14404: Avoid truncating 64 bit values into 32 bits for ULEB128/SLEB128 generation
llvm-svn: 184669
2013-06-23 18:31:11 +00:00
Tim Northover
295f049d1f AArch64: fix overzealous NEXTing for Windows testing.
llvm-svn: 184667
2013-06-23 15:32:01 +00:00
Andrew Trick
47740deb26 Add MI-Sched support for x86 macro fusion.
This is an awful implementation of the target hook. But we don't have
abstractions yet for common machine ops, and I don't see any quick way
to make it table-driven.

llvm-svn: 184664
2013-06-23 09:00:28 +00:00
Nadav Rotem
eb65e67eea SLP Vectorizer: Implement a simple CSE optimization for the gather sequences.
llvm-svn: 184660
2013-06-23 06:15:46 +00:00
Nadav Rotem
80de0a28f1 SLP Vectorizer: Implement multi-block slp-vectorization.
Rewrote the SLP-vectorization as a whole-function vectorization pass. It is now able to vectorize chains across multiple basic blocks.
It still does not vectorize PHIs, but this should be easy to do now that we scan the entire function.
I removed the support for extracting values from trees.
We are now able to vectorize more programs, but there are some serious regressions in many workloads (such as flops-6 and mandel-2).

llvm-svn: 184647
2013-06-22 21:34:10 +00:00
Reed Kotler
de085b2afb Replace with a shorter test case produced by Doug Gillmore.
llvm-svn: 184645
2013-06-22 19:35:08 +00:00
David Blaikie
2b380232c3 DebugInfo: Support (using GNU extensions) for template template parameters and parameter packs
llvm-svn: 184643
2013-06-22 18:59:11 +00:00
Chad Rosier
295bd43adb The getRegForInlineAsmConstraint function should only accept MVT value types.
llvm-svn: 184642
2013-06-22 18:37:38 +00:00
Benjamin Kramer
40d7f354b5 Revert "FunctionAttrs: Merge attributes once instead of doing it for every argument."
It doesn't work as I intended it to.  This reverts commit r184638.

llvm-svn: 184641
2013-06-22 16:56:32 +00:00
Benjamin Kramer
76b7bd0e75 FunctionAttrs: Merge attributes once instead of doing it for every argument.
It has become an expensive operation. No functionality change.

llvm-svn: 184638
2013-06-22 15:51:19 +00:00
Benjamin Kramer
b5ab360020 RelocVisitor: Add another PPC64 relocation that occurs in dwarf output.
Should bring the ppc64 buildbot back to life.

llvm-svn: 184633
2013-06-22 13:03:15 +00:00
Rafael Espindola
b046eedb94 Create the file with the right permissions instead of setting it afterwards.
Removes the last use of PathV1.h in llvm-ar.

llvm-svn: 184630
2013-06-22 02:34:24 +00:00
Sean Silva
8217757379 [yaml2obj][ELF] Make symbol table top-level key.
Although in reality the symbol table in ELF resides in a section, the
standard requires that there be no more than one SHT_SYMTAB. To enforce
this constraint, it is cleaner to group all the symbols under a
top-level `Symbols` key on the object file.

llvm-svn: 184627
2013-06-22 01:38:00 +00:00
Sean Silva
7a0c3a6fc4 [yaml2obj][ELF] Narrow parameter.
The full ELFYAML::Section isn't needed.

llvm-svn: 184626
2013-06-22 01:37:55 +00:00
Sean Silva
7d61722259 [yaml2obj][ELF] Don't special case writing these.
Just add them to the vector of section headers like the rest of the
section headers.

llvm-svn: 184624
2013-06-22 01:06:12 +00:00
Sean Silva
11caebaa32 [yaml2obj][ELF] Make this "type switch" actually readable.
llvm-svn: 184623
2013-06-22 01:03:35 +00:00
Sean Silva
d93323f51d [yaml2obj][ELF] Align section contents in the output.
The improperly aligned section content in the output was causing
buildbot failures. This should fix them.

Incidentally, this results in a simpler and more robust API for
ContiguousBlobAccumulator.

llvm-svn: 184621
2013-06-22 00:47:43 +00:00