463338 Commits

Author SHA1 Message Date
Matthias Springer
584f401730 [mlir][linalg][transform] Register linalg dialect patterns
Differential Revision: https://reviews.llvm.org/D152124
2023-06-05 11:36:59 +02:00
Jay Foad
3030c03988 [AMDGPU] Make use of MachineInstr::all_defs and all_uses. NFCI. 2023-06-05 10:32:33 +01:00
David Green
2b4807ba04 [AArch64][SVE] Predicated mla/mls patterns
To go with D149267 and D149967, this adds predicated mla/mls patterns, selected
from select(mask, add(a, mul(b, c)), a) -> mla(a, mask, b, c). The existing
patterns are eventually removed by D149967.

Differential Revision: https://reviews.llvm.org/D149969
2023-06-05 10:08:57 +01:00
Chen Zheng
b447dc5a47 use // instad of ; in c file tests, NFC 2023-06-05 05:02:38 -04:00
Mehdi Amini
d476ece573 Adopt Properties in builtin dialect
This was missed when the other dialects adopted it.

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D151410
2023-06-05 01:27:20 -07:00
Qiu Chaofan
9e17e08324 [PowerPC] Combine fptoint-store under strict cases
Reviewed By: shchenz

Differential Revision: https://reviews.llvm.org/D141249
2023-06-05 16:24:02 +08:00
Chen Zheng
225cf64e03 fix failures caused by https://reviews.llvm.org/D148490
buildbot: https://lab.llvm.org/buildbot/#/builders/214/builds/7823
2023-06-05 04:00:26 -04:00
Adrian Kuegel
bc7f65cbd8 [mlir][Bazel] Adjust BUILD files for a9d003ef855ff7ed1bf4f8229ee9944b55936e6f 2023-06-05 09:57:01 +02:00
Nathan Ridge
8ec44987e5 [clangd] Do not end inactiveRegions range at position 0 of line
This carries over the fix previously made for semantic highlighting
https://reviews.llvm.org/D92148, to the new inactiveRegions
protocol as well.

In addition, the directives at the beginning and end of an
inactive region are now excluded from the region.

Fixes https://github.com/clangd/clangd/issues/1631
Fixes https://github.com/clangd/clangd/issues/773

Differential Revision: https://reviews.llvm.org/D151190
2023-06-05 03:51:15 -04:00
LLVM GN Syncbot
95bfbf26ab [gn build] Port bbcd998efdb5 2023-06-05 07:38:58 +00:00
pvanhout
bbcd998efd Revert "[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp"
This reverts commit 79caedf5f8992ac16313157470f529344972c2ee.
2023-06-05 09:38:22 +02:00
LLVM GN Syncbot
c7ac32b313 [gn build] Port 79caedf5f899 2023-06-05 07:28:16 +00:00
pvanhout
79caedf5f8 [NFC][RFC][TableGen] Split GlobalISelEmitter.cpp
This patch splits the GlobalISelEmitter.cpp file, which imports DAG ISel patterns for GISel, into separate "GISelMatchTable.h/cpp" files.

The main motive is readability & maintainability. GlobalISelEmitter.cpp was about 6400 lines of mixed code, some bits implementing the match table codegen, some others dedicated to importing DAG patterns.

Now it's down to  2700 + a 2150 header + 2000 impl.
It's a tiny bit more lines overall but that's to be expected - moving
inline definitions to out-of-line, adding comments in the .cpp, etc. all of that takes additional space, but I think the tradeoff is worth it.

I did as little unrelated code changes as possible, I would say the biggest change is the introduction of the `gi` namespace used to prevent name conflicts/ODR violations with type common names such as `Matcher`.
It was previously not an issue because all of the code was in an anonymous namespace.

This moves all of the "match table" code out of the file, so predicates,
rules, and actions are all separated now. I believe this helps separating concerns, now `GlobalISelEmitter.cpp` is more focused on importing DAG patterns into GI, instead of also containing the whole match table internals as well.

Note: the new files have a "GISel" prefix to make them distinct from the other "GI" files in the same folder, which are for the combiner.

Reviewed By: aemerson

Differential Revision: https://reviews.llvm.org/D151432
2023-06-05 09:27:48 +02:00
Mikhail Goncharov
34866154d6 [bazel] add missing dep for GPUTransforms 2023-06-05 09:20:20 +02:00
esmeyi
6f57d8df2d Revert "[XCOFF][DWARF] XCOFF64 should be able to select the dwarf format in intergrated-as mode."
This reverts commit 4054c68644dfebbb584bca698a25d18d1d312bae.

Due to AIX system linker requires DWARF64 for XCOFF64.
2023-06-05 02:50:47 -04:00
Matthias Springer
4abccd3913 [mlir][memref][transform] Register memref dialect patterns
Differential Revision: https://reviews.llvm.org/D151998
2023-06-05 08:43:39 +02:00
Qiu Chaofan
590c6a1727 [PowerPC] Require FPCVT for store fptoi combination 2023-06-05 14:26:32 +08:00
Serge Pavlov
eecaeb6f10 [FPEnv] Intrinsics for access to FP environment
The change implements intrinsics 'get_fpenv', 'set_fpenv' and 'reset_fpenv'.
They are used to read floating-point environment, set it or reset to
some default state. They do the same actions as C library functions
'fegetenv' and 'fesetenv'. By default these intrinsics are lowered to calls
to these functions.

The new intrinsics specify FP environment as a value of integer type, it
is convenient of most targets where the FP state is a content of some
register. Some targets however use long representations. On X86 the size
of FP environment is 256 bits, and even half of this size is not a legal
ibteger type. To facilitate legalization in such cases, two sets of DAG
nodes is used. Nodes GET_FPENV and SET_FPENV are used when FP
environment may be represented by a legal integer type. Nodes
GET_FPENV_MEM and SET_FPENV_MEM consider FP environment as a region in
memory, much like `fesetenv` and `fegetenv` do. They are used when
target has long representation for floationg-point state.

Differential Revision: https://reviews.llvm.org/D71742
2023-06-05 13:10:01 +07:00
Qiu Chaofan
69bc8ff766 Reland "[PowerPC] Simplify fp-to-int store optimization"
The build failure should be fixed by de681d53. Follow-up refactor will
be done in future patches.

This reverts commit e7c5ced0b9f0551ea17e1d2b48be86f03a772c59.
2023-06-05 13:53:08 +08:00
Haohai Wen
b56c439d7d [NFC][COFF] clang-format WinCOFFObjectWriter and MCWinCOFFObjectWriter
Reviewed By: skan

Differential Revision: https://reviews.llvm.org/D152119
2023-06-05 13:42:01 +08:00
Vinayaka Bandishti
c45c96250b [Affine-fusion] Fix a bug in mod detection
Fix a bug in detecting unknown ids as mods of known ids that was
preventing certain fusions.

While at this, fix the function signature of `detectAsMod` function to
have output as the last argument.

Reviewed By: bondhugula

Differential Revision: https://reviews.llvm.org/D152055
2023-06-05 10:47:48 +05:30
Vinayaka Bandishti
01c755ff80 Make optimize llvm common to both gpu-to-hsaco/cubin
Before serializing, optimizations on llvm were only called on path to
hsaco, and not cubin. Define opt-level for `gpu-to-cubin` pass as well,
and move call to optimize llvm to a common place.

Reviewed By: bondhugula

Differential Revision: https://reviews.llvm.org/D151554
2023-06-05 10:32:51 +05:30
Alex Voicu
29663e2b8c [clang][CodeGen] Account for VTT address space
Correctly account for the fact that certain targets do not use the generic address space for the implicit VTT argument. This entails adjusting `ItaniumCXXABI::buildStructorSignature`, `ItaniumCXXABI::addImplicitStructorParams` and `ItaniumCXXABI::getImplicitConstructorArgs` to use the target's global variable address space. The associated test is temporarily marked `XFAIL` as additional fixes are needed.

Reviewed By: rjmccall

Differential Revision: https://reviews.llvm.org/D150746
2023-06-05 03:06:25 +01:00
Haohai Wen
01cc38843d [NFC][COFF] Use COFFSection.MCSection when writeSection
Each COFFSection bind MCSection when created. No need to iterate
throught MCAssembler when writeSection.

Reviewed By: skan

Differential Revision: https://reviews.llvm.org/D151793
2023-06-05 09:45:56 +08:00
Chen Zheng
4b27ad735c [AIX] use system assembler for assembly files
Change to system assembler to compile assembly files even
-fintegrated-as is specified. We don't have a good Clang as
for now for assembly files on AIX.

Reviewed By: qiucf

Differential Revision: https://reviews.llvm.org/D148490
2023-06-04 21:37:48 -04:00
Jacques Pienaar
1f8a33c19c [mlir][bytecodegen] Add list helper methods.
Previously the SignedVarInt was incorrectly defined. Follow up work
needed for improving Array printing/parsing, but correcting the
definitions for now.
2023-06-04 15:52:37 -07:00
Alexey Lapshin
d4100f07da Fix test bot breakage from 36f351098cd50809658493d9b2e22a795874bab0
This addresses the issue found by: https://lab.llvm.org/buildbot/#/builders/192/builds/2309
2023-06-05 00:04:53 +02:00
Jacques Pienaar
a9d003ef85 [mlir][bytecodegen] Add ReservedOrDead marker.
Enables reserving or marking dead in enum list, resulting in skipping in dispatches.
2023-06-04 14:59:50 -07:00
Jacques Pienaar
ba0aa2ec1c [mlir][bytecodegen] Remove comments (NFC).
Fix missed review comment from https://reviews.llvm.org/D144820
2023-06-04 14:19:40 -07:00
Aiden Grossman
8f7496b0b1 [Docs][llvm-mc] Fix location of statement
The comment moved is referring to the --output-asm-syntax flag rather
than the --print-imm-hex flag, but seems to have mistakenly been put
under the definition of that flag due to some misplaced line numbers on
phabricator.
2023-06-04 20:40:37 +00:00
Benjamin Kramer
9d531c2dcf [bazel] Port 36f351098cd5 2023-06-04 21:39:52 +02:00
Florian Hahn
e19297471a
[LV] Check if value was already not uniform for previous VF.
If the value was already known to not be uniform for the previous
(smaller VF), it cannot be uniform for the larger VF.

This slightly reduces compile-time, once uniformity checks are becoming
a bit more expensive due to using SCEV rewriting (D148841).

Reviewed By: Ayal

Differential Revision: https://reviews.llvm.org/D151658
2023-06-04 20:31:01 +01:00
Alexey Lapshin
0b8fbd49b5 make sanitizer happy for 36f351098cd50809658493d9b2e22a795874bab0. 2023-06-04 20:49:14 +02:00
LLVM GN Syncbot
373b54b9b1 [gn build] Port 36f351098cd5 2023-06-04 18:33:22 +00:00
Alexey Lapshin
36f351098c [DWARFLinkerParallel][Reland] Add interface files, create a skeleton implementation.
This patch creates skeleton implementation for the DWARFLinkerParallel.
It also integrates DWARFLinkerParallel into dsymutil and llvm-dwarfutil,
so that empty DWARFLinker::link() can be called. To do this new command
line option is added "--linker apple/llvm". Additionally it changes
existing DWARFLinker interfaces/implementations to be compatible:
use Error for error reporting for the DWARFStreamer, make DWARFFile to
owner of referenced resources, other small refactorings.

Differential Revision: https://reviews.llvm.org/D147952
2023-06-04 20:18:06 +02:00
LLVM GN Syncbot
72261627f6 [gn build] Port 7e1ee1e10dc0 2023-06-04 17:27:50 +00:00
Danila Kutenin
7e1ee1e10d [libcxx] Add strict weak ordering checks to sorting algorithms
This is the implementation of the first proposal of strict weak ordering checks described in https://discourse.llvm.org/t/rfc-strict-weak-ordering-checks-in-the-debug-libc/70217

This targets the most vulnerable algorithms like std::sort

Reviewed By: philnik, #libc

Differential Revision: https://reviews.llvm.org/D150264
2023-06-04 19:27:31 +02:00
Manna, Soumi
b0525f6698 [NFC][CLANG] [NFC][CLANG] Fix nullptr dereference issue in ConvertQualTypeToKind()
This patch uses castAs instead of getAs which will assert if the type doesn't match in ConvertQualTypeToKind(clang::ASTContext const &, clang::QualType).

Reviewed By: erichkeane

Differential Revision: https://reviews.llvm.org/D151928
2023-06-04 09:35:44 -07:00
Manna, Soumi
c755031073 [NFC][CLANG] Fix Static Code Analyzer Concerns
This patch uses castAs instead of getAs which will assert if the type doesn't match to resolve dereference issue with nullptr FPT when calling getThisType() in clang::CodeGen::CGDebugInfo::CreateType(clang::MemberPointerType const *, llvm::DIFile *).

Reviewed By: erichkeane

Differential Revision: https://reviews.llvm.org/D151947
2023-06-04 09:09:59 -07:00
Simon Pilgrim
0702d4e04d [GlobalIsel][X86] Move G_ICMP legalization before legacy handling and merge 32-bit/64-bit handling
I've kept the legalForCartesianProduct call, but this requires us to maintain 32-bit/64-bit integer lists - we might want to just use legalIf and perform the type pair set matching manually.
2023-06-04 17:01:57 +01:00
Ben Shi
53a7c254e4 [AVR][NFC][test] Suppement a test of the pseudo instruction RORBRd
Reviewed By: aykevl, Patryk27

Differential Revision: https://reviews.llvm.org/D152087
2023-06-04 23:19:21 +08:00
Sergei Barannikov
c9b9b08a24 [MC] Remove unused mc_difflist_iterator constructor (NFC)
The constructor hasn't been used since its introduction.
2023-06-04 18:18:36 +03:00
Simon Pilgrim
6effec1a50 [GlobalIsel][X86] Move G_PTRTOINT/G_INTTOPTR legalization before legacy handling and merge 32-bit/64-bit handling
I've kept the legalForCartesianProduct call, but this requires us to maintain 32-bit/64-bit integer lists - we might want to just use legalIf and perform the type pair set matching manually.
2023-06-04 15:21:42 +01:00
LLVM GN Syncbot
3a458256ee [gn build] Port 66e5678fece3 2023-06-04 11:36:45 +00:00
Sergei Barannikov
e8bd2a5784 [clang][CodeGen] Break up TargetInfo.cpp [6/8]
Make `qualifyWindowsLibrary` and `addStackProbeTargetAttributes`
protected members of `TargetCodeGenInfo`.
These are helper functions used by `getDependentLibraryOption` and
`setTargetAttributes` methods when targeting Windows. The change will
allow these functions to be reused after splitting `TargetInfo.cpp`.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D150178
2023-06-04 14:35:32 +03:00
Simon Pilgrim
73f55f7928 [GlobalIsel][X86] Remove some unused setLegalizerInfo* methods. NFC.
We're moving away from using per-ISA legalization controls and using LegalIf etc. to handle specific ISAs instead.
2023-06-04 12:34:14 +01:00
Alexey Lapshin
66e5678fec Revert "[DWARFLinkerParallel] Add interface files, create a skeleton implementation."
This reverts commit e0ba9b2ace7ffc20bf8fe2eb533d638f27619b10.
2023-06-04 13:28:54 +02:00
LLVM GN Syncbot
2150231652 [gn build] Port e0ba9b2ace7f 2023-06-04 11:09:26 +00:00
Alexey Lapshin
e0ba9b2ace [DWARFLinkerParallel] Add interface files, create a skeleton implementation.
This patch creates skeleton implementation for the DWARFLinkerParallel.
It also integrates DWARFLinkerParallel into dsymutil and llvm-dwarfutil,
so that empty DWARFLinker::link() can be called. To do this new command
line option is added "--linker apple/llvm". Additionally it changes
existing DWARFLinker interfaces/implementations to be compatible:
use Error for error reporting for the DWARFStreamer, make DWARFFile to
owner of referenced resources, other small refactorings.

Differential Revision: https://reviews.llvm.org/D147952
2023-06-04 13:03:57 +02:00
Sergei Barannikov
7a258706e3 [CodeGen] Fix incorrect usage of MCPhysReg for diff list elements
The lists contain differences between register numbers, not the register
numbers themselves. Since a difference can also be negative, this also
changes its type to signed.

Changing the type to signed exposed a "bug". For AMDGPU, which has many
registers, the first element of a sequence could be as big as ~45k.
The value does not fit into int16_t, but fits into uint16_t. The bug
didn't show up because of unsigned wrapping and truncation of the Val
field in the advance() method.

To fix the issue, I changed the way regunit difflists are encoded. The
4-bit 'scale' field of MCRegisterDesc::RegUnit was replaced by 12-bit
number of the first regunit, and the first element of each of the lists
was removed. The higher 20 bits of RegUnit field contain the initial
offset into DiffLists array.
AMDGPU has 1'409 regunits (2^12 = 4'096), and the biggest offset is
80'041 (2^20 = 1'048'576). That is, there is enough room.

Changing the encoding method also resulted in a smaller array size, the
numbers are below (I omitted targets with less than 100 elements).

```
AMDGPU   | 80052 | 78741 |  -1,6%
RISCV    |  6498 |  6297 |  -3,1%
ARM      |  4181 |  3966 |  -5,1%
AArch64  |  2770 |  2592 |  -6,4%
PPC      |  1578 |  1441 |  -8,7%
Hexagon  |   994 |   740 | -25,6%
R600     |   508 |   398 | -21,7%
VE       |   471 |   459 |  -2,5%
Sparc    |   381 |   363 |  -4,7%
X86      |   326 |   208 | -36,2%
Mips     |   253 |   200 | -20,9%
SystemZ  |   186 |   162 | -12,9%
```

Reviewed By: foad, arsenm

Differential Revision: https://reviews.llvm.org/D151036
2023-06-04 14:01:04 +03:00