424232 Commits

Author SHA1 Message Date
Stanislav Mekhanoshin
791ec1c68e [AMDGPU] Add intrinsics llvm.amdgcn.{raw|struct}.buffer.load.lds
Differential Revision: https://reviews.llvm.org/D124884
2022-05-17 10:32:13 -07:00
Min-Yih Hsu
0b168a49bf [mlir][LLVMIR] Use a new way to verify GEPOp indices
Previously, GEPOp relies on `findKnownStructIndices` to check if a GEP
index should be static. The truth is, `findKnownStructIndices` can only
tell you a GEP index _might_ be indexing into a struct (which should use
a static GEP index). But GEPOp::build and GEPOp::verify are falsely
taking this information as a certain answer, which creates many false
alarms like the one depicted in
`test/Target/LLVMIR/Import/dynamic-gep-index.ll`.

The solution presented here adopts a new verification scheme: When we're
recursively checking the child element types of a struct type, instead
of checking every child types, we only check the one dictated by the
(static) GEP index value. We also combine "refinement" logics --
refine/promote struct index mlir::Value into constants -- into the very
verification process since they have lots of logics in common. The
resulting code is more concise and less brittle.

We also hide GEPOp::findKnownStructIndices since most of the
aforementioned logics are already encapsulated within GEPOp::build and
GEPOp::verify, we found little reason for findKnownStructIndices (or the
new findStructIndices) to be public.

Differential Revision: https://reviews.llvm.org/D124935
2022-05-17 10:28:44 -07:00
Ruobing Han
e1cf702a02 fix typo error in DivergenceAnalysis.h
Fix a typo error in the comment in DivergenceAnalysis.h

Reviewed By: asbirlea

Differential Revision: https://reviews.llvm.org/D125808
2022-05-17 17:20:17 +00:00
David Green
4c6a070a2c [AArch64] Teach perfect shuffles tables about D-lane movs
Similar to D123386, this adds D-Movs to the AArch64 perfect shuffle
tables, slightly lowering the costs a little more. This is a rough
improvement in general, especially if you ignore mov v0.16b, v2.16b type
moves that are often artefacts of the calling convention.

The D register movs are encoded as (0x4 | LaneIdx), and to generate a D
register move we are required to bitcast into a higher type, but it is
otherwise very similar to the S-lane mov's already supported.

Differential Revision: https://reviews.llvm.org/D125477
2022-05-17 18:16:45 +01:00
Michael Kruse
bd93df937a [Polly] Mark classes as final by default. NFC.
This make is obivious that a class was not intended to be derived from.

NPM analysis pass can unfortunately not marked as final because they are
derived from a llvm::Checker<T> template internally by the NPM.

Also normalize the use of classes/structs
 * NPM passes are structs
 * Legacy passes are classes
 * structs that have methods and are not a visitor pattern are classes
 * structs have public inheritance by default, remove "public" keyword
 * Use typedef'ed type instead of inline forward declaration
2022-05-17 12:05:39 -05:00
Florian Hahn
d92cec4c96
[LV] Regenerate check lines for some tests.
Make sure the auto-generated check lines are up-to-date for some files,
to reduce the test diff in upcoming changes
2022-05-17 17:45:01 +01:00
Pengxuan Zheng
366e57de23 [clang-cl] Add /Zc:wchar_t- option
Map /Zc:wchar_t- to the cc1 flag -fno-wchar which is already supported.

Reviewed By: thakis

Differential Revision: https://reviews.llvm.org/D125513
2022-05-17 09:40:30 -07:00
Jay Foad
f84741d8bf [AMDGPU] Add a MIR test for D125567 2022-05-17 17:12:33 +01:00
Walter Erquinigo
d8f4f1027a [llvm][json] Fix UINT64 json parsing
https://reviews.llvm.org/D109347 added support for UINT64 json numeric
types. However, it seems that it didn't properly test uint64_t numbers
larger than the int64_t because the number parsing logic doesn't
have any special handling for these large numbers.

This diffs adds a handler for large numbers, and besides that, fixes the
parsing of signed types by checking for errno ERANGE, which is the
recommended way to check if parsing fails because of out of bounds
errors. Before this diff, strtoll was always returning a number within
the bounds of an int64_t and the bounds check it was doing was completely
superfluous.

As an interesting fact about the old implementation, when calling strtoll
with "18446744073709551615", the largest uint64_t, End was S.end(), even
though it didn't use all digits. Which means that this check can only be
used to identify if the numeric string is malformed or not.

This patch also adds additional tests for extreme cases.

Differential Revision: https://reviews.llvm.org/D125322
2022-05-17 09:11:45 -07:00
Walter Erquinigo
be738c9d1c [lldb-vscode] Fix data race in lldb-vscode when running with ThreadSanitizer
This patch fixes https://github.com/llvm/llvm-project/issues/54768. A ProgressEventReporter creates a dedicated thread that keeps checking whether there are new events that need to be sent to IDE as long as m_thread_should_exit is true. When the VSCode instance is destructed, it will set m_thread_should_exit to false, which caused a data race because at the same time its ProgressEventReporter is reading this value to determine whether it should quit. This fix simply uses mutex to ensure they cannot read and write this value at the same time.

Committed on behalf of PRESIDENT810

Reviewed By: clayborg, wallace

Differential Revision: https://reviews.llvm.org/D125073
2022-05-17 09:11:45 -07:00
Keith Smiley
627928c58b
Revert "[llvm-objcopy][test] Add cmp after copy"
This reverts commit 0d863b5b90a2f11e58b0b54d7183cb1577fd3a0b.

Broke a test https://reviews.llvm.org/D125478#3519509
2022-05-17 09:07:21 -07:00
Arthur Eubanks
470910c4ad [OpaquePtr][BitcodeReader] Explicitly turn off opaque pointers if we see a typed pointer
Followup to D125735 on the bitcode reader side.

Reviewed By: #opaque-pointers, nikic

Differential Revision: https://reviews.llvm.org/D125736
2022-05-17 08:43:02 -07:00
Arthur Eubanks
d2be4f9549 [OpaquePtr][LLParser] Explicitly turn off opaque pointers if we see a star
If we turn on --opaque-pointers, tests with '*' would use opaque pointers.

Can't really test this without flipping the default value for --opaque-pointers.

Reviewed By: #opaque-pointers, nikic

Differential Revision: https://reviews.llvm.org/D125735
2022-05-17 08:40:18 -07:00
Jim Ingham
7afd257ff8 Fix the std::string formatter to report errors in the case where the
string points to unaccessible memory.

The formatter tries to get the data field of the std::string, and to
check whether that fails it just checks that the ValueObjectSP
returned is not empty. But we never return empty ValueObjectSP's to
indicate failure, since doing so would lose the Error object that
tells you why fetching the ValueObject failed.

This patch adds a check for ValueObject::GetError().Success().

I also added a test case for this failure, and reworked the test case
a bit (to use run_to_source_breakpoint). I also renamed a couple of
single letter locals which don't follow the lldb coding conventions.

Differential Revision: https://reviews.llvm.org/D108228
2022-05-17 08:22:30 -07:00
LLVM GN Syncbot
f032690a7c [gn build] Port 76ddbb1ca747 2022-05-17 15:17:39 +00:00
Sam McCall
76ddbb1ca7 Revert "[clangd] Indexing of standard library"
This reverts commit ecaa4d9662c9a6ac013ac40a8ad72a2c75e3fd3b.
2022-05-17 17:17:27 +02:00
Sanjay Patel
f31d39c42c [InstCombine] remove cast-of-signbit to shift transform
The transform was wrong in 3 ways:

1. It created an extra instruction when the source and dest types don't match.
2. It did not account for an extra use of the icmp, so could create 2 extra insts.
3. It favored bit hacks over icmp (icmp generally has better analysis).

This fixes #54692 (modeled by the PhaseOrdering tests).

This is a minimal step to fix the bug, but we should likely invert
this and the sibling transform for the "is negative" pattern too.

The backend should be able to invert this back to a shift if that
leads to better codegen.

This is a reduced try of 3794cc0e9964 - that was reverted because
it could cause infinite loops by conflicting with the related
transforms in this block that create shifts.
2022-05-17 11:10:28 -04:00
Fraser Cormack
f7709a059a [RISCV] Add a test showing incorrect RVV stack alignment
The RISC-V stack is assumed to be aligned to 16 bytes and can handle stack
realignment for larger objects, but the "RVV stack" is only ensured to be
aligned to 8 bytes. This means that objects specified at a larger alignment may
be misaligned, not only for 16-byte-aligned RVV objects that don't trigger
realignment, but also for 32-byte-and-larger-aligned objects which do.

The new test checks a variety of alignment configurations, showing the
misaligned cases.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D110933
2022-05-17 15:53:53 +01:00
Florian Hahn
5b00d13c00
[LV] Fetch vector loop region once and remember it (NFC).
This avoids an unnecessary lookup and makes the code slightly more
compact.
2022-05-17 15:57:23 +01:00
LLVM GN Syncbot
c8cb644185 [gn build] Port ecaa4d9662c9 2022-05-17 14:51:11 +00:00
Sam McCall
ecaa4d9662 [clangd] Indexing of standard library
This provides a nice "warm start" with all headers indexed, not just
those included so far.

The standard library is indexed after a preamble is parsed, using that
file's configuration. The result is pushed into the dynamic index.
If we later see a higher language version, we reindex it.

It's configurable as Index.StandardLibrary, off by default for now.

Based on D105177 by @kuhnel

Fixes https://github.com/clangd/clangd/issues/618

Differential Revision: https://reviews.llvm.org/D115232
2022-05-17 16:50:41 +02:00
Fraser Cormack
8430b82741 [RISCV] Drop notion of "strict" vsetvli compatibility
With recent fixes to the dataflow in place, we now never pass
Strict=true to isCompatible, so remove the parameter completely.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D125748
2022-05-17 15:24:23 +01:00
Jake Egan
5caa7038a4 [NFC][AIX] Reenable mri1.test
This test is passing now because of D124017 and D123949.

Reviewed By: DiggerLin

Differential Revision: https://reviews.llvm.org/D125772
2022-05-17 10:27:20 -04:00
Nikita Popov
5df22e507b [IRBuilder] Move insertvalue/extractvalue to fold infrastructure
Move from the old CreateXYZ() to the new FoldXYZ() mechanism.

This change is likely NFC in practice, because I don't think that
the places using InstSimplifyFolder use insertvalue/extractvalue.
2022-05-17 16:04:55 +02:00
Erich Keane
2def74bef1 Fix release note typo from 6da3d66f 2022-05-17 06:35:06 -07:00
Cullen Rhodes
6ad6b00f6a [mlir] vim: add bf16 type 2022-05-17 13:28:31 +00:00
Cullen Rhodes
9bb0f4616a [mlir][licm] Fix debug output with newlines 2022-05-17 13:28:30 +00:00
Dmitri Gribenko
9c6a2f2966 Fix an unused variable warning in no-asserts build mode 2022-05-17 15:27:44 +02:00
Erich Keane
6da3d66f03 [concepts] Implement dcl.decl.general p4: No constraints on non-template funcs
The standard says:
The optional requires-clause ([temp.pre]) in an init-declarator or
member-declarator shall be present only if the declarator declares a
templated function ([dcl.fct]).

This implements that limitation, and updates the tests to the best of my
ability to capture the intent of the original checks.

Differential Revision: https://reviews.llvm.org/D125711
2022-05-17 06:21:51 -07:00
Haojian Wu
86bc6399a0 [pseudo] Add the missing ; terminal for module-declaration rule. 2022-05-17 15:14:46 +02:00
Alexey Bataev
b0f0313feb [SLP]Add an extra check for select minmax reduction to avoid crash.
Need to check if the reduction is still (not)cmp-select pattern min/max
reduction to avoid compiler crash during building list of reduction
operations. cmp-sel pattern provides 2 reduction operations, while
intrinsics - just one.
2022-05-17 06:05:52 -07:00
Konrad Kleine
329dc5587c [pgo] Fix doc typo: thingswith -> things with
The title says it all.

Reviewed By: thakis

Differential Revision: https://reviews.llvm.org/D125763
2022-05-17 12:58:23 +00:00
Kamau Bridgeman
99639e5a3e Enabling the detection of devtoolset-11 toolchain.
This patch allows systems to build the llvm-project with the devtoolset-11
toolchain.

Reviewed By: phosek

Differential Revision: https://reviews.llvm.org/D125499
2022-05-17 07:57:45 -05:00
Simon Pilgrim
d40b7f0d5a [DAG] Fold (shl (srl x, c), c) -> and(x, m) even if srl has other uses
If we're using shift pairs to mask, then relax the one use limit if the shift amounts are equal - we'll only be generating a single AND node.

AArch64 has a couple of regressions due to this, so I've enforced the existing one use limit inside a AArch64TargetLowering::shouldFoldConstantShiftPairToMask callback.

Part of the work to fix the regressions in D77804

Differential Revision: https://reviews.llvm.org/D125607
2022-05-17 13:40:11 +01:00
Louis Dionne
6de59ca417 [libc++] Introduce LIBCXX_LIBRARY_VERSION
This allows controlling the current_version linker property on Apple
platforms.

Differential Revision: https://reviews.llvm.org/D125686
2022-05-17 08:36:19 -04:00
Nathan Ridge
df2a4eae6b [clang] Expose CoawaitExpr's operand in the AST
Previously the Expr returned by getOperand() was actually the
subexpression common to the "ready", "suspend", and "resume"
expressions, which often isn't just the operand but e.g.
await_transform() called on the operand.

It's important for the AST to expose the operand as written
in the source for traversals and tools like clangd to work
correctly.

Fixes https://github.com/clangd/clangd/issues/939

Differential Revision: https://reviews.llvm.org/D115187
2022-05-17 08:13:37 -04:00
Jay Foad
77480556c4 [RegAllocGreedy] New hook regClassPriorityTrumpsGlobalness
Add a new TargetRegisterInfo hook to allow targets to tweak the
priority of live ranges, so that AllocationPriority of the register
class will be treated as more important than whether the range is local
to a basic block or global. This is determined per-MachineFunction.

Differential Revision: https://reviews.llvm.org/D125102
2022-05-17 12:35:21 +01:00
David Spickett
9e469ced42 [mlir][Tablegen-LSP] Don't link with llvm dylib
This updates 5de12bb703c5104b3fd64ee51c6900d6171d826a
to not link with the dylib since that does not include
the tablegen library.

Should fix flang dylib build failures:
https://lab.llvm.org/buildbot/#/builders/177/builds/5120
2022-05-17 11:03:01 +00:00
Florian Hahn
c1a9d14982
[VPlan] Move usesScalars/onlyFirstLaneUsed to VPUser.
Those helpers model properties of a user and they should also be
available to non-recipe users. This will be used in D123537 for a new
exit value user.

Reviewed By: Ayal

Differential Revision: https://reviews.llvm.org/D124936
2022-05-17 11:20:06 +01:00
David Green
8311fb7512 [AArch64] Extra tests useful for D-lane shuffles. NFC 2022-05-17 11:15:55 +01:00
Nikita Popov
b3bd732835 [JumpThreading] Regenerate test checks (NFC) 2022-05-17 12:13:02 +02:00
Alex Bradbury
8a23df89da [WebAssembly][NFC] Convert IsWasm64 instruction field to 'bit' from string
Extends the cleanup in D125713 to IsWasm64.

Differential Revision: https://reviews.llvm.org/D125714
2022-05-17 11:06:40 +01:00
Alex Bradbury
601ed0b605 [WebAssembly][NFC] Convert StackBased instruction field to 'bit' from string
This is (IMHO) cleaner and (objectively) more strongly typed than using strings.

A follow-on patch will do the same for IsWasm64.

Differential Revision: https://reviews.llvm.org/D125713
2022-05-17 11:02:30 +01:00
Simon Pilgrim
c64f5d44ad [X86] Attempt to fold EFLAGS into X86ISD::ADD/SUB ops
We already use combineAddOrSubToADCOrSBB to fold extended EFLAGS results into ISD::ADD/SUB ops as X86ISD::ADC/SBB carry ops.

This patch extends this to also try to fold EFLAGS results with X86ISD::ADD/SUB ops

Differential Revision: https://reviews.llvm.org/D125642
2022-05-17 10:59:24 +01:00
Sven van Haastregt
b250cca11d [OpenCL] Do not guard vload/store_half builtins
The vload*_half* and vstore*_half* builtins do not require the
cl_khr_fp16 extension: pointers to `half` can be declared without the
extension and the _half variants of vload and vstore should be
available without the extension.

This aligns the guards for these builtins for
`-fdeclare-opencl-builtins` with `opencl-c.h`.

Fixes https://github.com/llvm/llvm-project/issues/55275

Differential Revision: https://reviews.llvm.org/D125401
2022-05-17 10:57:23 +01:00
Nikita Popov
9ba452b08e [JumpThreading] Don't pass DT to isGuaranteedNotToBeUndefOrPoison()
JumpThreading intentionally does not force updating of the DT
during optimization, because this may be expensive when many CFG
updates and DT calculations are interleaved.

We shouldn't be fetching the DT just for the purpose of calling
isGuaranteedNotToBeUndefOrPoison(), especially as DT availability
doesn't even show benefit in tests.
2022-05-17 11:53:49 +02:00
Alexey Lapshin
4d9c083437 [DWARFLinker][NFC] Add None value to the DwarfLinkerAccelTableKind enum.
this review is extracted from D86539.

1. Rename AccelTableKind to DwarfLinkerAccelTableKind
   (to differentiate from AccelTableKind from CodeGen/AsmPrinter/DwarfDebug.h)

2. Add None value to the DwarfLinkerAccelTableKind.

3. added 'None' value for 'accelerator' option of dsymutil.

Differential Revision: https://reviews.llvm.org/D125474
2022-05-17 12:32:32 +03:00
Dmitry Vassiliev
7759680e2f [SROA] Avoid postponing rewriting load/store by ignoring lifetime intrinsics in partition's promotability checking
This patch fixes a bug that generates unnecessary packing/unpacking structure code because of incorrectly handling lifetime intrinsic.
For example, a partition of an alloca may contain many slices:
```
Partition [0, 4):
  Slice0: [0, 4) used by: load i32 addr;
  Slice1: [0, 4) used by: store i32 v, addr;
  Slice2: [0, 16) used by lifetime.start(16, addr);
```
When SROA determines if the partition can be promoted, lifetime.start is currently treated as a whole alloca load/store, so Slice0 and Slice1 cannot be promoted at this attempt,
but the packing/unpacking code for Slice0 and Slice1 has been generated.
After rewrite lifetime.start/end intrinsic, SROA tries again with Slice0 and Slice1 and finally promotes them, but redundant packing/unpacking code remaining in the IRs.
This patch changes promotability checking to ignore lifetime intrinsic (they will be rewritten to correct sizes later), so we can promote the real users (load/store) at the first attempt with optimal code.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D124967
2022-05-17 11:25:59 +02:00
Dmitry Vassiliev
9983b978f7 [SROA] Precommit test for D124967 2022-05-17 11:23:31 +02:00
Fraser Cormack
f00f894d5d [RISCV][NFC] Reword split SP adjustment comments 2022-05-17 10:03:21 +01:00