Commit Graph

419554 Commits

Author SHA1 Message Date
Simon Pilgrim
d32d65b903 [X86] Regenerate x86-interleaved-access.ll with AVX1OR2 common check-prefix to reduce duplication 2022-03-29 12:24:46 +01:00
Thomas Preud'homme
f1d8e46258 Clarify invariants of software pipelining hooks
PowerPC backend relies on each pair of prologue/epilogue of a software
pipelined loop to correspond to a single iteration a the loop through
its use of the BDZ instruction to skip inner prologues/epilogues and
loop kernel. However the interface does not make it clear that it is a
valid way to check that the trip count is big enough to execute inner
prologues/epilogues and kernel loop.

The API also does not specify in which order of prologues the
createTripCountGreaterCondition() hook is being called. Knowing that it
starts with the last/innermost prologues can help recording some
information when createTripCountGreaterCondition() is first executed and
reuse it in setPreheader() or adjustTripCount().

This commit documents both aspects.

Reviewed By: jmolloy

Differential Revision: https://reviews.llvm.org/D122642
2022-03-29 11:44:10 +01:00
Javier Setoain
7bc8ad5109 [mlir][vector][nfc] Rename index optimizations option
We are using "enable-index-optimizations" and "indexOptimizations" as
names for an optimization that consists of using i32 for indices within
a vector. For instance, when building a vector comparison for mask
generation. The name is confusing and suggests a scope beyond these
vector indices.  This change makes the function of the option explicit
in its name.

Differential Revision: https://reviews.llvm.org/D122415
2022-03-29 11:33:22 +01:00
serge-sans-paille
f5c666742f [doc] Rely on tblgen to dump supported options value when generating doc
It was already the case for CLI help, also support it for rst output. As a side
effect remove redundant (and sometime inconsistent!) value help from HelpText in
clang/Driver/Options.td.

Differential Revision: https://reviews.llvm.org/D122378
2022-03-29 12:25:33 +02:00
Jay Foad
2b754384ad [AMDGPU] Generate checks in atomic_optimizations_*.ll
This had already been done for some of these files but not all.
2022-03-29 11:05:23 +01:00
Sven van Haastregt
de30408b3b [OpenCL] opencl-c.h: remove a/b/c/i/p/n/v arg names
This simplifies completeness comparisons against OpenCLBuiltins.td and
also makes the header no longer "claim" any single-letter identifiers.

Continues the direction set out in D119560.
2022-03-29 10:16:27 +01:00
David Green
60f57b3658 [AArch64] Ensure fixed point fptoi_sat has correct saturation width
D113200 introduced an error where it was converting FP_TO_SI_SAT with
multiply to a fixed point floating point convert. The saturation
bitwidth needs to be equal to the floating point width, or else the
routine would truncate the result as opposed to saturating it.

Fixes 
2022-03-29 10:12:44 +01:00
Florian Hahn
3dbb5eb2cd
[ConstraintElimination] Move ConstraintInfo after ConstraintTy. (NFC)
Code movement to it slightly easier to use ConstraintTy & co in
ConstraintInfo directly, for follow-up patches.
2022-03-29 09:59:03 +01:00
Guillaume Chatelet
df838dbcfa [NFC][libc] Disable benchmarks when the LLVM benchmark target is not available
Fixes https://github.com/llvm/llvm-project/issues/53686

Differential Revision: https://reviews.llvm.org/D122481
2022-03-29 08:45:53 +00:00
Chenbing Zheng
6a01b676cf [DAGCombine] add tests for bswap-shift optimization
Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D121504
2022-03-29 16:34:52 +08:00
Uday Bondhugula
6e56d049db [MLIR][NFC] Remove dead FlatAffineConstraints constructor
NFC. Remove dead FlatAffineConstraints constructor.

Differential Revision: https://reviews.llvm.org/D122638
2022-03-29 13:44:56 +05:30
Zi Xuan Wu
0365c54ca3 [CSKY] Add CSKYTargetObjectFile to support exception handling
Initialize TargetLoweringObjectFileELF and EH header.
2022-03-29 16:05:30 +08:00
Zi Xuan Wu
27c18558e6 [CSKY] Add missing codegen pattern for 16-bit instruction
In generic cpu model, there are only low 16 registers and little 32-bit instruction. CK801 is the cpu
family with least basic features like generic model.

Add test run and check for generic cpu model in original test case to cover basic LLVM IR functionality.
2022-03-29 16:05:30 +08:00
Liqin Weng
8568d681ae [RISCV][NFC] Improve encoding/decoding tests for Zbb/Zbp/Zbt instructions
Reviewed By: benshi001

Differential Revision: https://reviews.llvm.org/D122282
2022-03-29 15:45:48 +08:00
Jean Perier
ec13942e71 [flang] prevent undefined behavior in character MAXLOC folding
When folding MAXLOC/MINLOC, the current element being compared was moved twice
in row in case it became the new extremum. With numeric and logical types, it
made no difference (std::move is a no-op for them), but for characters
where the string storage is actually moved, it caused the new extremum to
be set to the empty string, leading to wrong results.

Note: I could have left the first std::move relating to logical Findloc, but it
brings nothing and makes the code less auditable, so I also removed it.

Differential Revision: https://reviews.llvm.org/D122590
2022-03-29 09:34:09 +02:00
Lian Wang
2c503dcb4f [RISCV][NFC] Remove redundant check and rename functions in some IR tests
Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D122204
2022-03-29 07:29:58 +00:00
Markus Böck
984554f846 [clang][DR] Test and mark DR1479 as complete
DR: http://www.open-std.org/jtc1/sc22/wg21/docs/cwg_defects.html#1479

Clang has implemented this DR as far back as I could go on compiler explorer (3.0). This patch simply adds a test case and needed comments for the update script to mark it as complete.

Differential Revision: https://reviews.llvm.org/D122620
2022-03-29 09:28:32 +02:00
Argyrios Kyrtzidis
23519d3000 [Support/BLAKE3] Re-enable building with the simd-optimized implementations 2022-03-29 00:18:24 -07:00
Serguei Katkov
6444a65514 [LSR] Fixup canonicalization formula and its checker.
According to definition of canonical form, it is a canonical
if scale reg does not contain addrec for loop L then none of bases
should contain addrec for this loop.

The critical word here is "contains".

Current checker of canonical form checks not "containing" property
but "is". So it does not check whether it contains but whether it is.

Fix the checker and canonicalizing utility to follow definition.

Without this fix in the test attached the base formula looking as
reg((-1 * {0,+,8}<nuw><nsw><%bb2>)<nsw>) + 1*reg((8 * (%arg /u 8))<nuw>)
is considered as conanocial while base contains an addrec.
And modified formula we want to insert
reg({0,+,8}<nuw><nsw><%bb2>) + 1*reg((-8 * (%arg /u 8)))
is considered as not canonical.

Reviewed By: mkazantsev
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D122457
2022-03-29 14:05:04 +07:00
serge-sans-paille
01be9be2f2 Cleanup includes: final pass
Cleanup a few extra files, this closes the work on libLLVM dependencies on my
side.

Impact on libLLVM preprocessed output: -35876 lines

Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup
Differential Revision: https://reviews.llvm.org/D122576
2022-03-29 09:00:21 +02:00
luxufan
a5900401b1 [RISCV][test] Make PATH empty when testing --gcc-toolchain is multilib_riscv_elf_sdk
Due to D79842, clang dirver would search possible tool name in both possible
locations, then moving to the next name. The gcc toolchain `llvm-project/clang/test/Driver/
Inputs/multilib_riscv_elf_sdk` don't have a `riscv64-unknown-elf-ld` executable in
`llvm-project/clang/test/Driver/Inputs/multilib_riscv_elf_sdk/bin/`. So when searching
`riscv64-unknown-elf-ld`, if there is a `riscv64-unknown-elf-ld` in `PATH`, the
test would fail.

This patch makes the `PATH` empty when testing it.

Differential Revision: https://reviews.llvm.org/D122588
2022-03-29 14:51:23 +08:00
Liqin Weng
d660c0d793 [RISCV] Optimize LI+SLT to SLTI+XORI for immediates in specific range
This transform will reduce one GPR.

Reviewed By: craig.topper, benshi001

Differential Revision: https://reviews.llvm.org/D122051
2022-03-29 14:46:49 +08:00
LLVM GN Syncbot
5314582407 [gn build] Port 90cb325abd 2022-03-29 06:21:57 +00:00
Paul Kirth
90cb325abd Revert "[misexpect] Re-implement MisExpect Diagnostics"
This reverts commit 2add3fbd97.
2022-03-29 06:20:30 +00:00
Paul Kirth
6c77972bac Revert "[docs][misexpect][NFC] Fix malformed table in docs"
This reverts commit a427e18896.
2022-03-29 06:19:53 +00:00
Shraiysh Vaishay
1fe4b968c5 [flang][OpenMP] Added parallel sections translation
This patch adds translation for parallel sections from PFT to MLIR.

Reviewed By: kiranchandramohan, NimishMishra

Differential Revision: https://reviews.llvm.org/D122464
2022-03-29 11:16:38 +05:30
Nathan Ridge
9325e97a35 [clangd] Handle tabs in getIncrementalChangesAfterNewline()
Tabs are not handled by columnWidthUTF8() (they are considered
non-printable) so require additional logic to handle.

Fixes https://github.com/clangd/clangd/issues/1074

Differential Revision: https://reviews.llvm.org/D122554
2022-03-29 01:43:09 -04:00
Johannes Doerfert
b803f06901 [OpenMP] The test does not have check lines 2022-03-29 00:02:55 -05:00
Dominic Chen
0e1d2007aa [scudo] Use template specialization on Quarantine to avoid zero-length array
Use a separate templated QuarantineBlocks class to avoid a zero-length array

Differential Revision: https://reviews.llvm.org/D122518
2022-03-28 21:35:49 -07:00
Johannes Doerfert
b309bdb970 [OpenMP][FIX] Use clang++ for the C++ test case 2022-03-28 23:14:24 -05:00
Ben Shi
50de68bc2f [Driver][AVR] Emit proper warnings for different options
Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D122524
2022-03-29 12:05:21 +08:00
Craig Topper
45e85feba6 [RISCV] Pull APInt/computeKnonwbits specifics out of computeGREVOrGORC. NFC
This function now takes a uint64_t instead of an APInt. The caller
is responsible for masking the shift amount, extracting and inserting
into the KnownBits APInts, and inverting to compute zeros.

This is less code and cleaner division of responsibilities.
2022-03-28 20:53:54 -07:00
Johannes Doerfert
b316126887 [OpenMP][FIX] Avoid races in the handling of to be deleted mapping entries
If we decided to delete a mapping entry we did not act on it right away
but first issued and waited for memory copies. In the meantime some
other thread might reuse the entry. While there was some logic to avoid
colliding on the actual "deletion" part, there were two races happening:

1) The data transfer back of the thread deleting the entry and
   the data transfer back of the thread taking over the entry raced.
2) The update to the shadow map happened regardless if the entry was
   actually reused by another thread which left the shadow map in a
   inconsistent state.

To fix both issues we will now update the shadow map and delete the
entry only if we are sure the thread is responsible for deletion, hence
no other thread took over the entry and reused it. We also wait for a
potential former data transfer from the device to finish before we issue
another one that would race with it.

Fixes https://github.com/llvm/llvm-project/issues/54216

Differential Revision: https://reviews.llvm.org/D121058
2022-03-28 22:33:18 -05:00
Johannes Doerfert
ba93e4e33e [OpenMP][NFC] Add missing virtual destructor to silence warning 2022-03-28 22:33:18 -05:00
Phoebe Wang
cd26190a10 [X86][regcall] Support passing / returning structures
Currently, the regcall calling conversion in Clang doesn't match with
ICC when passing / returning structures. https://godbolt.org/z/axxKMKrW7

This patch tries to fix the problem to match with ICC.

Reviewed By: LuoYuanke

Differential Revision: https://reviews.llvm.org/D122104
2022-03-29 11:29:57 +08:00
Fangrui Song
48e251b1d6 Revert D122459 "[ELF] --emit-relocs: adjust offsets of .rel[a].eh_frame relocations"
This reverts commit 6faba31e0d.

It may cause "offset is outside the section".
2022-03-28 20:26:21 -07:00
Philip Reames
33deaa13b8 [memcpyopt] Common code into performCallSlotOptzn [NFC]
We have the same code repeated in both callers, sink it into callee.

The motivation here isn't just code style, we can also defer the relatively expensive aliasing checks until the cheap structural preconditions have been validated.  (e.g. Don't bother aliasing if src is not an alloca.)  This helps compile time significantly.
2022-03-28 20:10:13 -07:00
Philip Reames
7d6e8f2a96 [slp] Delete dead scalar instructions feeding vectorized instructions
If we vectorize a e.g. store, we leave around a bunch of getelementptrs for the individual scalar stores which we removed. We can go ahead and delete them as well.

This is purely for test output quality and readability. It should have no effect in any sane pipeline.

Differential Revision: https://reviews.llvm.org/D122493
2022-03-28 20:10:13 -07:00
Jacques Pienaar
0217d1178b [mlir] Fix leak in case of failed parse
A Block is optionally allocated & leaks in case of failed parse. Inline the
function and ensure Block gets freed unless parse is successful.

Differential Revision: https://reviews.llvm.org/D122112
2022-03-28 20:04:31 -07:00
zhongyunde
2b3becb41d [AArch64][GlobalISel] Add new MOVI pattern for fp constants
GlobalISel is used in option -O0, so add MOVI pattern for it,
which is done similar in gcc.(https://godbolt.org/z/8j6fzG3h6)

Fix https://github.com/llvm/llvm-project/issues/53651

Reviewed By: dmgreen, paquette

Differential Revision: https://reviews.llvm.org/D122559
2022-03-29 10:57:22 +08:00
long.chen
12ba76c6d1 Eliminate gcc7 compiler warnings
we will get warning:```parameter ‘op’ set but not used``` when template function with empty template parameter list.

Reviewed By: jpienaar

Differential Revision: https://reviews.llvm.org/D122527
2022-03-28 19:55:37 -07:00
Brad Smith
6e2c6c9def [libcxx] random_device, specify optimal entropy properties for all OS's using arc4random()
Reviewed By: ldionne

Differential Revision: https://reviews.llvm.org/D122522
2022-03-28 22:43:11 -04:00
Dominic Chen
a52868a55c Revert "[scudo] Use template specialization on Quarantine to avoid zero-length array"
This reverts commit 7dda44c189.
2022-03-28 19:08:55 -07:00
Chenbing Zheng
d9ef6ad05f [RISCV] [NFC] add some tests for overloaded intrinsics of FP16
Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D122564
2022-03-29 10:00:20 +08:00
Johannes Doerfert
7df2eba7fa [Attributor][OpenMP] Add assumption for non-call assembly instructions
Inline assembly is scary but we need to support it for the OpenMP GPU
device runtime. The new assumption expresses the fact that it may not
have call semantics, that is, it will not call another function but
simply perform an operation or side-effect. This is important for
reachability in the presence of inline assembly.

Differential Revision: https://reviews.llvm.org/D109986
2022-03-28 20:57:52 -05:00
Johannes Doerfert
bb0b23174e [InstCombineCalls] Optimize call of bitcast even w/ parameter attributes
Before we gave up if a call through bitcast had parameter attributes.
Interestingly, we allowed attributes for the return value already. We
now handle both the same way, namely, we drop the ones that are
incompatible with the new type and keep the rest. This cannot cause
"more UB" than initially present.

Differential Revision: https://reviews.llvm.org/D119967
2022-03-28 20:57:52 -05:00
Shao-Ce SUN
662b9fa02c [NFC][CodeGen] Add a setTargetDAGCombine use ArrayRef
Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D122557
2022-03-29 09:53:24 +08:00
Fangrui Song
cfbd5c8e4a [AArch64] Allow .variant_pcs before the symbol is registered
glibc sysdeps/aarch64/tst-vpcs-mod.S has something like:
```
.variant_pcs    vpcs_call
.global vpcs_call
```

This is supported by GNU as but leads to an error in MC. Use getOrCreateSymbol
to support a not-yet-registered symbol: call `registerSymbol` to ensure the
symbol exists even if there is no binding directive/label, to match GNU as.

While here, improve tests to check (1) a local symbol can get
STO_AARCH64_VARIANT_PCS (2) undefined .variant_pcs (3) an alias does not
inherit STO_AARCH64_VARIANT_PCS.

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D122507
2022-03-28 17:52:27 -07:00
Paul Kirth
a427e18896 [docs][misexpect][NFC] Fix malformed table in docs
Reviewed By: abrachet

Differential Revision: https://reviews.llvm.org/D122623
2022-03-29 00:14:07 +00:00
Craig Topper
01203918d1 [RISCV] Add computeKnownBits support for RISCVISD::GORC.
Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D121575
2022-03-28 16:56:33 -07:00