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https://github.com/capstone-engine/llvm-capstone.git
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ac51cf1960
Move to RISCVInstrInfo since we need RISCVSubtarget now. Instead of asking if only the lower 32 bits are used we can now ask if the lower N bits are used. This will be needed by a future patch.
88 lines
2.6 KiB
C++
88 lines
2.6 KiB
C++
//===-------------- RISCVStripWSuffix.cpp - -w Suffix Removal -------------===//
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//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===---------------------------------------------------------------------===//
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//
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// This pass removes the -w suffix from each addiw and slliw instructions
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// whenever all users are dependent only on the lower word of the result of the
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// instruction. We do this only for addiw and slliw because the -w forms are
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// less compressible.
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//
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//===---------------------------------------------------------------------===//
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#include "RISCV.h"
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#include "RISCVMachineFunctionInfo.h"
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using namespace llvm;
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static cl::opt<bool> DisableStripWSuffix("riscv-disable-strip-w-suffix",
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cl::desc("Disable strip W suffix"),
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cl::init(false), cl::Hidden);
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namespace {
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class RISCVStripWSuffix : public MachineFunctionPass {
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public:
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static char ID;
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RISCVStripWSuffix() : MachineFunctionPass(ID) {
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initializeRISCVStripWSuffixPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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StringRef getPassName() const override { return "RISCV Strip W Suffix"; }
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};
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} // end anonymous namespace
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char RISCVStripWSuffix::ID = 0;
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INITIALIZE_PASS(RISCVStripWSuffix, "riscv-strip-w-suffix",
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"RISCV Strip W Suffix", false, false)
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FunctionPass *llvm::createRISCVStripWSuffixPass() {
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return new RISCVStripWSuffix();
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}
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bool RISCVStripWSuffix::runOnMachineFunction(MachineFunction &MF) {
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if (skipFunction(MF.getFunction()) || DisableStripWSuffix)
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return false;
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MachineRegisterInfo &MRI = MF.getRegInfo();
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const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>();
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const RISCVInstrInfo &TII = *ST.getInstrInfo();
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if (!ST.is64Bit())
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return false;
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bool MadeChange = false;
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for (MachineBasicBlock &MBB : MF) {
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for (auto I = MBB.begin(), IE = MBB.end(); I != IE; ++I) {
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MachineInstr &MI = *I;
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switch (MI.getOpcode()) {
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case RISCV::ADDW:
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case RISCV::SLLIW:
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if (TII.hasAllWUsers(MI, MRI)) {
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unsigned Opc =
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MI.getOpcode() == RISCV::ADDW ? RISCV::ADD : RISCV::SLLI;
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MI.setDesc(TII.get(Opc));
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MadeChange = true;
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}
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break;
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}
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}
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}
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return MadeChange;
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}
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