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llvm-capstone/llvm/lib/Target/RISCV
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Manolis Tsamis d4012bc43f [RISCV] Add vendor-defined XTheadMAC (multiply-accumulate) extension 
The vendor-defined XTHeadMAC (no comparable standard extension exists
at the time of writing) extension adds multiply accumulate instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=4041e11db3ec3611921d10150572a92689aa3154

Co-authored-by: Philipp Tomsich <philipp.tomsich@vrull.eu>

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D143847
2023-02-14 20:25:47 +01:00
..
AsmParser
[MC] Simplify code with parseComma
2023-02-01 18:41:02 -08:00
Disassembler
[RISCV] Add vendor-defined XTheadMAC (multiply-accumulate) extension
2023-02-14 20:25:47 +01:00
GISel
[RISCV] Move GlobalISEL specific files to sub-directory [nfc]
2022-11-15 14:24:50 -08:00
MCA
[RISCV][llvm-mca] Use LMUL Instruments to provide more accurate reports on RISCV
2022-11-18 09:55:15 -08:00
MCTargetDesc
[RISCV] Rename InstFormatCSZN->InstFormatCU to match latest Zcb spec. NFC
2023-02-13 21:14:03 -08:00
TargetInfo
[RISCV] Re-enable JIT support
2022-08-11 11:41:02 +02:00
CMakeLists.txt
[RISCV] Add pass to remove W suffix from ADDIW and SLLIW to improve compressibility
2022-12-22 14:19:26 -08:00
RISCV.h
[RISCV] Add pass to remove W suffix from ADDIW and SLLIW to improve compressibility
2022-12-22 14:19:26 -08:00
RISCV.td
[RISCV] Move Processors and Features from RISCV.td to their own files.
2023-01-23 10:17:08 -08:00
RISCVAsmPrinter.cpp
[RISCV] Use canonical move instruction in RISCVAsmPrinter::EmitHwasanMemaccessSymbols.
2023-01-18 11:38:39 -08:00
RISCVCallingConv.td
…
RISCVCodeGenPrepare.cpp
[RISCV] isImpliedByDomCondition returns an Optional<bool> not a bool.
2022-08-12 22:21:05 -07:00
RISCVExpandAtomicPseudoInsts.cpp
[RISCV] Add asserts that we don't increase codesize during pseudo expansion
2023-01-31 07:49:54 -08:00
RISCVExpandPseudoInsts.cpp
[RISCV] Add asserts that we don't increase codesize during pseudo expansion
2023-01-31 07:49:54 -08:00
RISCVFeatures.td
[RISCV] Add vendor-defined XTheadMAC (multiply-accumulate) extension
2023-02-14 20:25:47 +01:00
RISCVFrameLowering.cpp
[CodeGen] Additional Register argument to storeRegToStackSlot/loadRegFromStackSlot
2022-12-17 11:55:34 +05:30
RISCVFrameLowering.h
Recommit "[RISCV] Enable the LocalStackSlotAllocation pass support"
2023-01-06 09:54:19 -08:00
RISCVGatherScatterLowering.cpp
[NFC] Use TypeSize::geFixedValue() instead of TypeSize::getFixedSize()
2023-01-11 16:49:38 +00:00
RISCVInsertVSETVLI.cpp
[RISCV][InsertVSETVLI] Handle partially transparent instructions in PRE
2023-01-27 11:52:09 -08:00
RISCVInstrFormats.td
[RISCV] Rename InstFormatCSZN->InstFormatCU to match latest Zcb spec. NFC
2023-02-13 21:14:03 -08:00
RISCVInstrFormatsC.td
[RISCV] Rename InstFormatCSZN->InstFormatCU to match latest Zcb spec. NFC
2023-02-13 21:14:03 -08:00
RISCVInstrFormatsV.td
[RISCV] Replace hardcoded constant with OPIVI.Value in tablegen. NFC
2022-11-30 20:58:40 -08:00
RISCVInstrInfo.cpp
[MachineOutliner] Make getOutliningType partially target-independent
2023-02-09 14:35:00 -05:00
RISCVInstrInfo.h
[MachineOutliner] Make getOutliningType partially target-independent
2023-02-09 14:35:00 -05:00
RISCVInstrInfo.td
[RISCV] Add vendor-defined XTheadMAC (multiply-accumulate) extension
2023-02-14 20:25:47 +01:00
RISCVInstrInfoA.td
[RISCV] Add target feature to force-enable atomics
2022-08-09 16:04:46 +02:00
RISCVInstrInfoC.td
[RISCV] Remove DecoderMethod from C_NOP_HINT. NFC
2023-02-06 07:25:56 -08:00
RISCVInstrInfoD.td
[RISCV] Move all isel cases for ISD::ConstantFP into RISCVDAGToDAGISel::Select.
2023-02-04 17:31:39 -08:00
RISCVInstrInfoF.td
[RISCV] Move all isel cases for ISD::ConstantFP into RISCVDAGToDAGISel::Select.
2023-02-04 17:31:39 -08:00
RISCVInstrInfoM.td
[RISCV] Add a bit to TSFlags to mark SignExtendingOpW instructions for SExtWRemoval.
2022-12-14 10:38:48 -08:00
RISCVInstrInfoV.td
[RISCV][CodeGen] Account for LMUL from VS2 for Vector Reduction Instructions
2023-02-07 17:43:23 -08:00
RISCVInstrInfoVPseudos.td
[RISCV][CodeGen] Account for LMUL from VS2 for Vector Reduction Instructions
2023-02-07 17:43:23 -08:00
RISCVInstrInfoVSDPatterns.td
[RISCV][NFC] Rename narrowing patterns to use W suffix
2023-01-26 11:17:14 +00:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Don't use constantpool for floating-point value if the value can be easily constructed by integer sequence and a floating-point move.
2023-02-03 22:42:08 -08:00
RISCVInstrInfoXTHead.td
[RISCV] Add vendor-defined XTheadMAC (multiply-accumulate) extension
2023-02-14 20:25:47 +01:00
RISCVInstrInfoXVentana.td
[RISCV] Add more XVentanaCondOps patterns.
2023-01-06 08:29:23 -08:00
RISCVInstrInfoZb.td
[RISCV] Simplify predicates with llvm::countr_zero (NFC)
2023-01-28 12:14:43 -08:00
RISCVInstrInfoZc.td
[RISCV] Rename InstFormatCSZN->InstFormatCU to match latest Zcb spec. NFC
2023-02-13 21:14:03 -08:00
RISCVInstrInfoZfh.td
[RISCV] Move all isel cases for ISD::ConstantFP into RISCVDAGToDAGISel::Select.
2023-02-04 17:31:39 -08:00
RISCVInstrInfoZicbo.td
[RISCV][NFC] Fix typo in comment in RISCVInstrInfoZicbo.td
2022-09-01 13:49:55 +01:00
RISCVInstrInfoZk.td
[RISCV] Add IsSignExtendingOpW to the Zknh SHA256 instructions.
2022-12-14 11:52:01 -08:00
RISCVISelDAGToDAG.cpp
[RISCV] Add vendor-defined XTheadMAC (multiply-accumulate) extension
2023-02-14 20:25:47 +01:00
RISCVISelDAGToDAG.h
[RISCV] Add vendor-defined XTheadMAC (multiply-accumulate) extension
2023-02-14 20:25:47 +01:00
RISCVISelLowering.cpp
DAG: Remove hasBitPreservingFPLogic
2023-02-14 10:25:24 -04:00
RISCVISelLowering.h
DAG: Remove hasBitPreservingFPLogic
2023-02-14 10:25:24 -04:00
RISCVMachineFunctionInfo.cpp
[RISCV] Teach SExtWRemoval to recognize sign extended values that come from arguments.
2022-10-04 15:39:10 -07:00
RISCVMachineFunctionInfo.h
CodeGen: Don't lazily construct MachineFunctionInfo
2022-12-21 10:49:32 -05:00
RISCVMacroFusion.cpp
[RISCV] Be more strict about LUI+ADDI macrofusion pre-RA.
2022-08-21 10:58:15 -07:00
RISCVMacroFusion.h
[RISCV] Add macrofusion infrastructure and one example usage.
2022-06-23 08:38:39 -07:00
RISCVMakeCompressible.cpp
[RISCV] Replace uses of hasStdExtC with COrZca.
2022-12-07 09:34:01 -08:00
RISCVMCInstLower.cpp
[RISCV] Pre-RA expand pseudos pass
2022-07-31 23:19:00 +02:00
RISCVMergeBaseOffset.cpp
[RISCV] Reduce duplicated code in RISCVMergeBaseOffsetOpt::detectFoldable. NFC
2022-12-20 07:16:43 -08:00
RISCVProcessors.td
[RISCV] Move Processors and Features from RISCV.td to their own files.
2023-01-23 10:17:08 -08:00
RISCVRedundantCopyElimination.cpp
[RISCV] Use analyzeBranch in RISCVRedundantCopyElimination.
2022-08-29 09:05:53 -07:00
RISCVRegisterInfo.cpp
[CodeGen] Make more use of MachineOperand::getOperandNo. NFC.
2023-02-07 11:50:57 +00:00
RISCVRegisterInfo.h
Recommit "[RISCV] Enable the LocalStackSlotAllocation pass support"
2023-01-06 09:54:19 -08:00
RISCVRegisterInfo.td
[RISCV] Add CoveredBySubRegs to the X*_PD register class.
2023-02-02 10:03:33 -08:00
RISCVSchedRocket.td
[RISCV] Merge WriteLDW and WriteLDWU schedule classes.
2022-10-28 11:57:33 -07:00
RISCVSchedSiFive7.td
[RISCV] Merge WriteLDW and WriteLDWU schedule classes.
2022-10-28 11:57:33 -07:00
RISCVSchedSyntacoreSCR1.td
[RISCV] Add Syntacore SCR1 CPU model
2022-12-14 11:45:44 +03:00
RISCVSchedule.td
[RISCV] Merge WriteLDW and WriteLDWU schedule classes.
2022-10-28 11:57:33 -07:00
RISCVScheduleV.td
[RISCV][CodeGen] Account for LMUL from VS2 for Vector Reduction Instructions
2023-02-07 17:43:23 -08:00
RISCVScheduleZb.td
[RISCV] Rename RISCVScheduleB.td to RISCVScheduleZb.td. NFC
2022-09-23 21:38:42 -07:00
RISCVSExtWRemoval.cpp
[RISCV] Fix miscompile in SExtWRemoval due to early return ignoring other sources
2023-02-08 11:45:48 -08:00
RISCVStripWSuffix.cpp
[RISCV] Refactor RISCV::hasAllWUsers to hasAllNBitUsers similar to RISCVISelDAGToDAG's version. NFC
2022-12-28 12:49:23 -08:00
RISCVSubtarget.cpp
[RISCV] Default to -ffixed-x18 for Fuchsia
2023-02-05 18:51:18 -08:00
RISCVSubtarget.h
[RISCV] Use OS-specific stack-guard ABI for Fuchsia
2023-02-05 18:45:59 -08:00
RISCVSystemOperands.td
…
RISCVTargetMachine.cpp
Remove no longer needed includes of LegacyPassManager.h
2023-02-06 13:38:57 +01:00
RISCVTargetMachine.h
CodeGen: Don't lazily construct MachineFunctionInfo
2022-12-21 10:49:32 -05:00
RISCVTargetObjectFile.cpp
…
RISCVTargetObjectFile.h
…
RISCVTargetTransformInfo.cpp
[Target] Use llvm::count{l,r}_{zero,one} (NFC)
2023-01-28 09:23:07 -08:00
RISCVTargetTransformInfo.h
[LoopVectorize][TTI] NFCI: Clarify enum for the tail folding style.
2023-02-03 14:59:57 +00:00