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ad7a1805be
Iterate through memory accesses in execution order (first all implicit reads, then explicit accesses, then implicit writes). In the test case this caused an implicit load to be handled as if it was loaded after the write. That is, the value being written before it is available. This fixes llvm.org/PR33323 llvm-svn: 304810
40 lines
1.1 KiB
Plaintext
40 lines
1.1 KiB
Plaintext
{
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"arrays" : [
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{
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"name" : "MemRef_symmat",
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"sizes" : [ "*", "1000" ],
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"type" : "double"
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}
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],
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"context" : "{ : }",
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"name" : "%for.body98---%for.cond87.loopexit",
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"statements" : [
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{
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"accesses" : [
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{
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"kind" : "write",
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"relation" : "{ Stmt_for_body105[i0, i1] -> MemRef_add119[] }"
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}
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],
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"domain" : "{ Stmt_for_body105[i0, i1] : 0 <= i0 <= 998 and 0 <= i1 <= 999 }",
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"name" : "Stmt_for_body105",
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"schedule" : "{ Stmt_for_body105[i0, i1] -> [i0, 0, i1] }"
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},
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{
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"accesses" : [
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{
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"kind" : "write",
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"relation" : "{ Stmt_for_end122[i0] -> MemRef_symmat[1 + i0, 0] }"
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},
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{
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"kind" : "read",
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"relation" : "{ Stmt_for_end122[i0] -> MemRef_add119[] }"
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}
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],
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"domain" : "{ Stmt_for_end122[i0] : 0 <= i0 <= 998 }",
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"name" : "Stmt_for_end122",
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"schedule" : "{ Stmt_for_end122[i0] -> [i0, 1, 0] }"
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}
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]
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}
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