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Add braces to if, else, for, while ... (#11504)

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This commit is contained in:
Neven Sajko 2018-09-13 10:17:26 +02:00 committed by radare
parent 4ed384b230
commit 4a722e80d8
310 changed files with 16519 additions and 11703 deletions
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4
binr/r2agent/r2agent.c
View File

@ -102,7 +102,9 @@ int main(int argc, char **argv) {
const char *result = page_index;
rs = r_socket_http_accept (s, 0, timeout);
if (!rs) continue;
if (!rs) {
continue;
}
if (!strcmp (rs->method, "GET")) {
if (!strncmp (rs->path, "/proc/kill/", 11)) {
// TODO: show page here?

4
binr/rabin2/rabin2.c
View File

@ -879,7 +879,9 @@ int main(int argc, char **argv) {
*p2++ = 0;
data = malloc (strlen (p2)+1);
datalen = r_hex_str2bin (p2, data);
if (datalen < 0) datalen = -datalen;
if (datalen < 0) {
datalen = -datalen;
}
} else {
data = NULL;
datalen = 0;

8
binr/radare2/radare2.c
View File

@ -1427,12 +1427,16 @@ int main(int argc, char **argv, char **envp) {
r.num->value = 0;
break;
}
if (lock) r_th_lock_enter (lock);
if (lock) {
r_th_lock_enter (lock);
}
/* -1 means invalid command, -2 means quit prompt loop */
if ((ret = r_core_prompt_exec (&r)) == -2) {
break;
}
if (lock) r_th_lock_leave (lock);
if (lock) {
r_th_lock_leave (lock);
}
if (rabin_th && !r_th_wait_async (rabin_th)) {
// eprintf ("rabin thread end \n");
r_th_kill_free (rabin_th);

8
binr/rafind2/rafind2.c
View File

@ -83,7 +83,9 @@ static int hit(RSearchKeyword *kw, void *user, ut64 addr) {
static int show_help(char *argv0, int line) {
printf ("Usage: %s [-mXnzZhqv] [-a align] [-b sz] [-f/t from/to] [-[e|s|S] str] [-x hex] file|dir ..\n", argv0);
if (line) return 0;
if (line) {
return 0;
}
printf (
" -a [align] only accept aligned hits\n"
" -b [size] set block size\n"
@ -136,7 +138,9 @@ static int rafind_open_file(char *file) {
r_cons_new ();
rs = r_search_new (mode);
if (!rs) return 1;
if (!rs) {
return 1;
}
buf = calloc (1, bsize);
if (!buf) {
eprintf ("Cannot allocate %"PFMT64d" bytes\n", bsize);

65
binr/ragg2/ragg2.c
View File

@ -15,38 +15,39 @@ static int usage(int v) {
printf ("Usage: ragg2 [-FOLsrxhvz] [-a arch] [-b bits] [-k os] [-o file] [-I path]\n"
" [-i sc] [-e enc] [-B hex] [-c k=v] [-C file] [-p pad] [-q off]\n"
" [-q off] [-dDw off:hex] file|f.asm|-\n");
if (v) printf (
" -a [arch] select architecture (x86, mips, arm)\n"
" -b [bits] register size (32, 64, ..)\n"
" -B [hexpairs] append some hexpair bytes\n"
" -c [k=v] set configuration options\n"
" -C [file] append contents of file\n"
" -d [off:dword] patch dword (4 bytes) at given offset\n"
" -D [off:qword] patch qword (8 bytes) at given offset\n"
" -e [encoder] use specific encoder. see -L\n"
" -f [format] output format (raw, c, pe, elf, mach0, python, javascript)\n"
" -F output native format (osx=mach0, linux=elf, ..)\n"
" -h show this help\n"
" -i [shellcode] include shellcode plugin, uses options. see -L\n"
" -I [path] add include path\n"
" -k [os] operating system's kernel (linux,bsd,osx,w32)\n"
" -L list all plugins (shellcodes and encoders)\n"
" -n [dword] append 32bit number (4 bytes)\n"
" -N [dword] append 64bit number (8 bytes)\n"
" -o [file] output file\n"
" -O use default output file (filename without extension or a.out)\n"
" -p [padding] add padding after compilation (padding=n10s32)\n"
" ntas : begin nop, trap, 'a', sequence\n"
" NTAS : same as above, but at the end\n"
" -P [size] prepend debruijn pattern\n"
" -q [fragment] debruijn pattern offset\n"
" -r show raw bytes instead of hexpairs\n"
" -s show assembler\n"
" -v show version\n"
" -w [off:hex] patch hexpairs at given offset\n"
" -x execute\n"
" -z output in C string syntax\n"
);
if (v) {
printf (
" -a [arch] select architecture (x86, mips, arm)\n"
" -b [bits] register size (32, 64, ..)\n"
" -B [hexpairs] append some hexpair bytes\n"
" -c [k=v] set configuration options\n"
" -C [file] append contents of file\n"
" -d [off:dword] patch dword (4 bytes) at given offset\n"
" -D [off:qword] patch qword (8 bytes) at given offset\n"
" -e [encoder] use specific encoder. see -L\n"
" -f [format] output format (raw, c, pe, elf, mach0, python, javascript)\n"
" -F output native format (osx=mach0, linux=elf, ..)\n"
" -h show this help\n"
" -i [shellcode] include shellcode plugin, uses options. see -L\n"
" -I [path] add include path\n"
" -k [os] operating system's kernel (linux,bsd,osx,w32)\n"
" -L list all plugins (shellcodes and encoders)\n"
" -n [dword] append 32bit number (4 bytes)\n"
" -N [dword] append 64bit number (8 bytes)\n"
" -o [file] output file\n"
" -O use default output file (filename without extension or a.out)\n"
" -p [padding] add padding after compilation (padding=n10s32)\n"
" ntas : begin nop, trap, 'a', sequence\n"
" NTAS : same as above, but at the end\n"
" -P [size] prepend debruijn pattern\n"
" -q [fragment] debruijn pattern offset\n"
" -r show raw bytes instead of hexpairs\n"
" -s show assembler\n"
" -v show version\n"
" -w [off:hex] patch hexpairs at given offset\n"
" -x execute\n"
" -z output in C string syntax\n");
}
return 1;
}

73
binr/rasm2/rasm2.c
View File

@ -84,8 +84,9 @@ static void rasm2_list(RAsm *la, const char *arch) {
if (h->cpus && !strcmp (arch, h->name)) {
char *c = strdup (h->cpus);
int n = r_str_split (c, ',');
for (i = 0; i < n; i++)
for (i = 0; i < n; i++) {
printf ("%s\n", r_str_word_get0 (c, i));
}
free (c);
break;
}
@ -94,15 +95,29 @@ static void rasm2_list(RAsm *la, const char *arch) {
if (h->bits == 27) {
strcat (bits, "27");
} else {
if (h->bits & 8) strcat (bits, "8 ");
if (h->bits & 16) strcat (bits, "16 ");
if (h->bits & 32) strcat (bits, "32 ");
if (h->bits & 64) strcat (bits, "64 ");
if (h->bits & 8) {
strcat (bits, "8 ");
}
if (h->bits & 16) {
strcat (bits, "16 ");
}
if (h->bits & 32) {
strcat (bits, "32 ");
}
if (h->bits & 64) {
strcat (bits, "64 ");
}
}
feat = "__";
if (h->assemble && h->disassemble) feat = "ad";
if (h->assemble && !h->disassemble) feat = "a_";
if (!h->assemble && h->disassemble) feat = "_d";
if (h->assemble && h->disassemble) {
feat = "ad";
}
if (h->assemble && !h->disassemble) {
feat = "a_";
}
if (!h->assemble && h->disassemble) {
feat = "_d";
}
feat2 = has_esil (anal, h->name);
if (quiet) {
printf ("%s\n", h->name);
@ -157,12 +172,15 @@ static int showanal(RAnal *lanal, RAnalOp *op, ut64 offset, ut8 *buf, int len, b
printf ("{\"opcode\": \"0x%08" PFMT64x "\",", offset);
printf ("\"bytes\": \"%s\",", bytes);
printf ("\"type\": \"%s\",", optype);
if (op->jump != -1LL)
if (op->jump != -1LL) {
printf ("{\"jump\": \"0x%08" PFMT64x ",", op->jump);
if (op->fail != -1LL)
}
if (op->fail != -1LL) {
printf ("{\"fail\": \"0x%08" PFMT64x ",", op->fail);
if (op->val != -1LL)
}
if (op->val != -1LL) {
printf ("{\"value\": \"0x%08" PFMT64x ",", op->val);
}
printf ("\"stackop\": \"%s\",", stackop);
printf ("\"esil\": \"%s\",", r_strbuf_get (&op->esil));
printf ("\"stackptr\": \"0x%08" PFMT64x "\"", op->stackptr);
@ -171,14 +189,17 @@ static int showanal(RAnal *lanal, RAnalOp *op, ut64 offset, ut8 *buf, int len, b
printf ("offset: 0x%08" PFMT64x "\n", offset);
printf ("bytes: %s\n", bytes);
printf ("type: %s\n", optype);
if (op->jump != -1LL)
if (op->jump != -1LL) {
printf ("jump: 0x%08" PFMT64x "\n", op->jump);
if (op->fail != -1LL)
}
if (op->fail != -1LL) {
printf ("fail: 0x%08" PFMT64x "\n", op->fail);
}
//if (op->ref != -1LL)
// printf ("ref: 0x%08"PFMT64x"\n", op->ref);
if (op->val != -1LL)
if (op->val != -1LL) {
printf ("value: 0x%08" PFMT64x "\n", op->val);
}
printf ("stackop: %s\n", stackop);
printf ("esil: %s\n", r_strbuf_get (&op->esil));
printf ("stackptr: %" PFMT64d "\n", op->stackptr);
@ -332,7 +353,9 @@ static void print_buf(char *str) {
printf ("\\x%c%c", *str, str[1]);
}
printf ("\"\n");
} else printf ("%s\n", str);
} else {
printf ("%s\n", str);
}
}
static bool print_label(void *user, const char *k, void *v) {
@ -443,8 +466,9 @@ int main (int argc, char *argv[]) {
&__lib_anal_cb, &__lib_anal_dt, NULL);
path = r_sys_getenv (R_LIB_ENV);
if (path && *path)
if (path && *path) {
r_lib_opendir (l, path);
}
if (1) {
char *homeplugindir = r_str_home (R2_HOME_PLUGINS);
@ -544,7 +568,9 @@ int main (int argc, char *argv[]) {
break;
case 'O':
fd = open (optarg, O_TRUNC | O_RDWR | O_CREAT, 0644);
if (fd != -1) dup2 (fd, 1);
if (fd != -1) {
dup2 (fd, 1);
}
break;
case 'p':
use_spp = true;
@ -595,8 +621,9 @@ int main (int argc, char *argv[]) {
goto beach;
}
r_anal_use (anal, arch);
if (!strcmp (arch, "bf"))
if (!strcmp (arch, "bf")) {
ascii = 1;
}
} else if (env_arch) {
if (!r_asm_use (a, env_arch)) {
eprintf ("rasm2: Unknown asm plugin '%s'\n", env_arch);
@ -680,8 +707,9 @@ int main (int argc, char *argv[]) {
content = r_file_slurp (file, &length);
if (content) {
if (len && len > 0 && len < length)
if (len && len > 0 && len < length) {
length = len;
}
content[length] = '\0';
if (skip && length > skip) {
if (bin) {
@ -710,7 +738,9 @@ int main (int argc, char *argv[]) {
int length;
do {
length = read (0, buf, sizeof (buf) - 1);
if (length < 1) break;
if (length < 1) {
break;
}
if (len > 0 && len < length) {
length = len;
}
@ -726,8 +756,9 @@ int main (int argc, char *argv[]) {
}
if (!bin || !dis) {
int buflen = strlen ((const char *)buf);
if (buf[buflen] == '\n')
if (buf[buflen] == '\n') {
buf[buflen - 1] = '\0';
}
}
if (dis) {
ret = rasm_disasm ((char *)buf, offset, length, a->bits, ascii, bin, dis - 1);

36
libr/anal/anal_ex.c
View File

@ -331,19 +331,25 @@ R_API ut64 r_anal_ex_map_anal_ex_to_anal_bb_type (ut64 ranal2_op_type) {
R_ANAL_OP_TYPE_COND : 0;
ut64 code_op_val = ranal2_op_type & (R_ANAL_EX_CODE_OP | 0x1FF);
if (conditional)
if (conditional) {
bb_type |= R_ANAL_BB_TYPE_COND;
if (ranal2_op_type & R_ANAL_EX_LOAD_OP)
}
if (ranal2_op_type & R_ANAL_EX_LOAD_OP) {
bb_type |= R_ANAL_BB_TYPE_LD;
if (ranal2_op_type & R_ANAL_EX_BIN_OP)
}
if (ranal2_op_type & R_ANAL_EX_BIN_OP) {
bb_type |= R_ANAL_BB_TYPE_BINOP;
if (ranal2_op_type & R_ANAL_EX_LOAD_OP)
}
if (ranal2_op_type & R_ANAL_EX_LOAD_OP) {
bb_type |= R_ANAL_BB_TYPE_LD;
if (ranal2_op_type & R_ANAL_EX_STORE_OP)
}
if (ranal2_op_type & R_ANAL_EX_STORE_OP) {
bb_type |= R_ANAL_BB_TYPE_ST;
}
/* mark bb with a comparison */
if (ranal2_op_type & R_ANAL_EX_BINOP_CMP)
if (ranal2_op_type & R_ANAL_EX_BINOP_CMP) {
bb_type |= R_ANAL_BB_TYPE_CMP;
}
/* change in control flow here */
if (code_op_val & R_ANAL_EX_CODEOP_JMP) {
@ -362,11 +368,13 @@ R_API ut64 r_anal_ex_map_anal_ex_to_anal_bb_type (ut64 ranal2_op_type) {
bb_type |= R_ANAL_BB_TYPE_TAIL;
}
if ( ranal2_op_type & R_ANAL_EX_UNK_OP && code_op_val & R_ANAL_EX_CODEOP_JMP)
if (ranal2_op_type & R_ANAL_EX_UNK_OP && code_op_val & R_ANAL_EX_CODEOP_JMP) {
bb_type |= R_ANAL_BB_TYPE_FOOT;
}
if ( conditional && code_op_val & R_ANAL_EX_CODEOP_JMP)
if (conditional && code_op_val & R_ANAL_EX_CODEOP_JMP) {
bb_type |= R_ANAL_BB_TYPE_BODY;
}
return bb_type;
}
@ -414,9 +422,15 @@ ut64 extract_load_store_op(ut64 ranal2_op_type) {
ut64 extract_unknown_op(ut64 ranal2_op_type) {
if ( (ranal2_op_type & R_ANAL_EX_CODEOP_JMP) == R_ANAL_EX_CODEOP_JMP ) return R_ANAL_OP_TYPE_UJMP;
if ( (ranal2_op_type & R_ANAL_EX_CODEOP_CALL) == R_ANAL_EX_CODEOP_CALL) return R_ANAL_OP_TYPE_UCALL;
if ( (ranal2_op_type & R_ANAL_EX_LDST_OP_PUSH) == R_ANAL_EX_LDST_OP_PUSH) return R_ANAL_OP_TYPE_UPUSH;
if ((ranal2_op_type & R_ANAL_EX_CODEOP_JMP) == R_ANAL_EX_CODEOP_JMP) {
return R_ANAL_OP_TYPE_UJMP;
}
if ((ranal2_op_type & R_ANAL_EX_CODEOP_CALL) == R_ANAL_EX_CODEOP_CALL) {
return R_ANAL_OP_TYPE_UCALL;
}
if ((ranal2_op_type & R_ANAL_EX_LDST_OP_PUSH) == R_ANAL_EX_LDST_OP_PUSH) {
return R_ANAL_OP_TYPE_UPUSH;
}
return R_ANAL_OP_TYPE_UNK;
}

29
libr/anal/cond.c
View File

@ -29,14 +29,18 @@ R_API RAnalCond *r_anal_cond_new() {
}
R_API void r_anal_cond_fini (RAnalCond *c) {
if (!c) return;
if (!c) {
return;
}
r_anal_value_free (c->arg[0]);
r_anal_value_free (c->arg[1]);
c->arg[0] = c->arg[1] = NULL;
}
R_API void r_anal_cond_free (RAnalCond *c) {
if (!c) return;
if (!c) {
return;
}
r_anal_cond_fini (c);
free (c);
}
@ -44,7 +48,9 @@ R_API void r_anal_cond_free (RAnalCond *c) {
// XXX?
R_API RAnalCond *r_anal_cond_clone(RAnalCond *cond) {
RAnalCond *c = R_NEW (RAnalCond);
if (!c) return NULL;
if (!c) {
return NULL;
}
memcpy (c, cond, sizeof (RAnalCond));
return c;
}
@ -53,10 +59,11 @@ static inline const char *condstring(RAnalCond *cond) {
const char *condstr_single[] = { "!", "", "0<", "0<=", "0>", "0>=" };
const char *condstr[] = { "==", "!=", ">=", ">", "<=", "<" };
if (cond) {
if (cond->arg[1])
if (cond->arg[1]) {
return condstr[cond->type % 6];
else
} else {
return condstr_single[cond->type % 6];
}
}
return "";
}
@ -91,21 +98,24 @@ R_API int r_anal_cond_eval(RAnal *anal, RAnalCond *cond) {
R_API char *r_anal_cond_to_string(RAnalCond *cond) {
char *val0, *val1, *out = NULL;
const char *cnd;
if (!cond)
if (!cond) {
return NULL;
}
cnd = condstring (cond);
val0 = r_anal_value_to_string (cond->arg[0]);
val1 = r_anal_value_to_string (cond->arg[1]);
if (val0) {
if (R_ANAL_COND_SINGLE (cond)) {
int val0len = strlen (val0) + 10;
if ((out = malloc (val0len)))
if ((out = malloc (val0len))) {
snprintf (out, val0len, "%s%s", cnd, val0);
}
} else {
if (val1) {
int val0len = strlen (val0) + strlen (val1) + 10;
if ((out = malloc (val0len)))
if ((out = malloc (val0len))) {
snprintf (out, val0len, "%s %s %s", val0, cnd, val1);
}
}
}
}
@ -116,8 +126,9 @@ R_API char *r_anal_cond_to_string(RAnalCond *cond) {
R_API RAnalCond *r_anal_cond_new_from_op(RAnalOp *op) {
RAnalCond *cond;
if (!(cond = r_anal_cond_new ()))
if (!(cond = r_anal_cond_new ())) {
return NULL;
}
//v->reg[0] = op->src[0];
//v->reg[1] = op->src[1];
cond->arg[0] = op->src[0];

4
libr/anal/cycles.c
View File

@ -16,7 +16,9 @@ R_API RAnalCycleFrame *r_anal_cycle_frame_new() {
}
R_API void r_anal_cycle_frame_free(RAnalCycleFrame *cf) {
if (!cf) return;
if (!cf) {
return;
}
r_list_free (cf->hooks);
free (cf);
}

62
libr/anal/data.c
View File

@ -5,7 +5,9 @@
#define MINLEN 1
static int is_string(const ut8 *buf, int size, int *len) {
int i;
if (size < 1) return 0;
if (size < 1) {
return 0;
}
if (size > 3 && buf[0] && !buf[1] && buf[2] && !buf[3]) {
*len = 1; // XXX: TODO: Measure wide string length
return 2; // is wide
@ -42,8 +44,12 @@ static int is_null(const ut8 *buf, int size) {
}
static int is_invalid(const ut8 *buf, int size) {
if (size < 1) return 1;
if (size > 8) size = 8;
if (size < 1) {
return 1;
}
if (size > 8) {
size = 8;
}
return (!memcmp (buf, "\xff\xff\xff\xff\xff\xff\xff\xff", size))? 1: 0;
}
@ -52,10 +58,13 @@ static ut64 is_pointer(RAnal *anal, const ut8 *buf, int size) {
ut64 n;
ut8 buf2[32];
RIOBind *iob = &anal->iob;
if (size > sizeof (buf2))
if (size > sizeof (buf2)) {
size = sizeof (buf2);
}
n = r_mem_get_num (buf, size);
if (!n) return 1; // null pointer
if (!n) {
return 1; // null pointer
}
#if USE_IS_VALID_OFFSET
int r = iob->is_valid_offset (iob->io, n, 0);
return r? n: 0LL;
@ -94,7 +103,9 @@ R_API char *r_anal_data_to_string(RAnalData *d, RConsPrintablePalette *pal) {
ut32 n32;
char *line;
if (!d) return NULL;
if (!d) {
return NULL;
}
line = malloc (mallocsz);
if (!line) {
@ -203,7 +214,9 @@ R_API char *r_anal_data_to_string(RAnalData *d, RConsPrintablePalette *pal) {
R_API RAnalData *r_anal_data_new_string(ut64 addr, const char *p, int len, int type) {
RAnalData *ad = R_NEW0 (RAnalData);
if (!ad) return NULL;
if (!ad) {
return NULL;
}
ad->str = NULL;
ad->addr = addr;
ad->type = type;
@ -330,7 +343,9 @@ R_API RAnalData *r_anal_data(RAnal *anal, ut64 addr, const ut8 *buf, int size, i
}
if (size >= word) {
n = is_number (buf, word);
if (n) return r_anal_data_new (addr, R_ANAL_DATA_TYPE_NUMBER, n, buf, word);
if (n) {
return r_anal_data_new (addr, R_ANAL_DATA_TYPE_NUMBER, n, buf, word);
}
}
return r_anal_data_new (addr, R_ANAL_DATA_TYPE_UNKNOWN, dst, buf, R_MIN (word, size));
}
@ -344,8 +359,9 @@ R_API const char *r_anal_data_kind(RAnal *a, ut64 addr, const ut8 *buf, int len)
RAnalData *data;
int word = a->bits / 8;
for (i = j = 0; i < len; j++) {
if (str && !buf[i])
if (str && !buf[i]) {
str++;
}
data = r_anal_data (a, addr + i, buf + i, len - i, 0);
if (!data) {
i += word;
@ -357,7 +373,9 @@ R_API const char *r_anal_data_kind(RAnal *a, ut64 addr, const ut8 *buf, int len)
i += word;
break;
case R_ANAL_DATA_TYPE_NUMBER:
if (data->ptr > 1000) num++;
if (data->ptr > 1000) {
num++;
}
i += word;
break;
case R_ANAL_DATA_TYPE_UNKNOWN:
@ -367,7 +385,9 @@ R_API const char *r_anal_data_kind(RAnal *a, ut64 addr, const ut8 *buf, int len)
case R_ANAL_DATA_TYPE_STRING:
if (data->len > 0) {
i += data->len;
} else i += word;
} else {
i += word;
}
str++;
break;
default:
@ -375,10 +395,20 @@ R_API const char *r_anal_data_kind(RAnal *a, ut64 addr, const ut8 *buf, int len)
}
r_anal_data_free (data);
}
if (j < 1) return "unknown";
if ((inv * 100 / j) > 60) return "invalid";
if ((unk * 100 / j) > 60) return "code";
if ((num * 100 / j) > 60) return "code";
if ((str * 100 / j) > 40) return "text";
if (j < 1) {
return "unknown";
}
if ((inv * 100 / j) > 60) {
return "invalid";
}
if ((unk * 100 / j) > 60) {
return "code";
}
if ((num * 100 / j) > 60) {
return "code";
}
if ((str * 100 / j) > 40) {
return "text";
}
return "data";
}

3
libr/anal/diff.c
View File

@ -98,8 +98,9 @@ R_API int r_anal_diff_fingerprint_fcn(RAnal *anal, RAnalFunction *fcn) {
r_list_foreach (fcn->bbs, iter, bb) {
len += bb->size;
fcn->fingerprint = realloc (fcn->fingerprint, len + 1);
if (!fcn->fingerprint)
if (!fcn->fingerprint) {
return 0;
}
memcpy (fcn->fingerprint+len-bb->size, bb->fingerprint, bb->size);
}
return len;

118
libr/anal/esil.c
View File

@ -30,7 +30,9 @@ static inline ut64 genmask(int bits) {
ut64 m = UT64_MAX;
if (bits < 64) {
m = (ut64)(((ut64)(2) << bits) - 1);
if (!m) m = UT64_MAX;
if (!m) {
m = UT64_MAX;
}
}
return m;
}
@ -169,12 +171,14 @@ R_API int r_anal_esil_fire_interrupt(RAnalEsil *esil, int interrupt) {
if (esil->anal) {
RAnalPlugin *ap = esil->anal->cur;
if (ap && ap->esil_intr) {
if (ap->esil_intr (esil, interrupt))
if (ap->esil_intr (esil, interrupt)) {
return true;
}
}
}
if (!esil->interrupts)
if (!esil->interrupts) {
return false;
}
i = sdb_itoa ((ut64)interrupt, t, 16);
if (!sdb_num_exists (esil->interrupts, i)) {
//eprintf ("0x%08"PFMT64x" Invalid interrupt/syscall 0x%08x\n", esil->address, interrupt);
@ -409,8 +413,12 @@ R_API int r_anal_esil_mem_write(RAnalEsil *esil, ut64 addr, const ut8 *buf, int
static int internal_esil_reg_read(RAnalEsil *esil, const char *regname, ut64 *num, int *size) {
RRegItem *reg = r_reg_get (esil->anal->reg, regname, -1);
if (reg) {
if (size) *size = reg->size;
if (num) *num = r_reg_get_value (esil->anal->reg, reg);
if (size) {
*size = reg->size;
}
if (num) {
*num = r_reg_get_value (esil->anal->reg, reg);
}
return true;
}
return false;
@ -530,8 +538,9 @@ R_API int r_anal_esil_get_parm_type(RAnalEsil *esil, const char *str) {
}
return R_ANAL_ESIL_PARM_NUM;
not_a_number:
if (r_reg_get (esil->anal->reg, str, -1))
if (r_reg_get (esil->anal->reg, str, -1)) {
return R_ANAL_ESIL_PARM_REG;
}
return R_ANAL_ESIL_PARM_INVALID;
}
@ -657,11 +666,15 @@ R_API int r_anal_esil_get_parm_size(RAnalEsil *esil, const char *str, ut64 *num,
switch (parm_type) {
case R_ANAL_ESIL_PARM_INTERNAL:
// *num = esil_internal_read (esil, str, num);
if (size) *size = esil->anal->bits;
if (size) {
*size = esil->anal->bits;
}
return esil_internal_read (esil, str, num);
case R_ANAL_ESIL_PARM_NUM:
*num = r_num_get (NULL, str);
if (size) *size = esil->anal->bits;
if (size) {
*size = esil->anal->bits;
}
return true;
case R_ANAL_ESIL_PARM_REG:
if (!r_anal_esil_reg_read (esil, str, num, size)) {
@ -716,7 +729,9 @@ R_API int r_anal_esil_reg_read(RAnalEsil *esil, const char *regname, ut64 *num,
}
return esil_internal_read (esil, regname, num);
}
if (!num) num = &localnum;
if (!num) {
num = &localnum;
}
*num = 0LL;
if (size) {
*size = esil->anal->bits;
@ -1404,8 +1419,9 @@ static int esil_break(RAnalEsil *esil) {
static int esil_clear(RAnalEsil *esil) {
char *r;
while ((r = r_anal_esil_pop (esil)))
while ((r = r_anal_esil_pop (esil))) {
free (r);
}
return 1;
}
@ -2022,7 +2038,9 @@ static int esil_mem_oreq_n(RAnalEsil *esil, int bits) {
r_anal_esil_pushnum (esil, d); //push the new dst-value
r_anal_esil_push (esil, dst); //push the dst-addr
ret &= (!!esil_poke_n (esil, bits)); //write
} else ret = 0;
} else {
ret = 0;
}
}
if (!ret) {
ERR ("esil_mem_oreq_n: invalid parameters");
@ -2066,7 +2084,9 @@ static int esil_mem_xoreq_n(RAnalEsil *esil, int bits) {
r_anal_esil_pushnum (esil, d);
r_anal_esil_push (esil, dst);
ret &= (!!esil_poke_n (esil, bits));
} else ret = 0;
} else {
ret = 0;
}
}
if (!ret) {
ERR ("esil_mem_xoreq_n: invalid parameters");
@ -2110,7 +2130,9 @@ static int esil_mem_andeq_n(RAnalEsil *esil, int bits) {
r_anal_esil_pushnum (esil, d);
r_anal_esil_push (esil, dst);
ret &= (!!esil_poke_n (esil, bits));
} else ret = 0;
} else {
ret = 0;
}
}
if (!ret) {
ERR ("esil_mem_andeq_n: invalid parameters");
@ -2154,10 +2176,13 @@ static int esil_mem_addeq_n(RAnalEsil *esil, int bits) {
r_anal_esil_pushnum (esil, d);
r_anal_esil_push (esil, dst);
ret &= (!!esil_poke_n (esil, bits));
} else ret = 0;
} else {
ret = 0;
}
}
if (!ret)
if (!ret) {
ERR ("esil_mem_addeq_n: invalid parameters");
}
free (dst);
free (src0);
free (src1);
@ -2197,10 +2222,13 @@ static int esil_mem_subeq_n(RAnalEsil *esil, int bits) {
r_anal_esil_pushnum (esil, d);
r_anal_esil_push (esil, dst);
ret &= (!!esil_poke_n (esil, bits));
} else ret = 0;
} else {
ret = 0;
}
}
if (!ret)
if (!ret) {
ERR ("esil_mem_subeq_n: invalid parameters");
}
free (dst);
free (src0);
free (src1);
@ -2298,11 +2326,14 @@ static int esil_mem_diveq_n(RAnalEsil *esil, int bits) {
r_anal_esil_pushnum (esil, d);
r_anal_esil_push (esil, dst);
ret &= (!!esil_poke_n (esil, bits));
} else ret = 0;
} else {
ret = 0;
}
}
}
if (!ret)
if (!ret) {
ERR ("esil_mem_diveq_n: invalid parameters");
}
free (dst);
free (src0);
free (src1);
@ -2342,10 +2373,13 @@ static int esil_mem_muleq_n(RAnalEsil *esil, int bits, ut64 bitmask) {
r_anal_esil_pushnum (esil, d);
r_anal_esil_push (esil, dst);
ret &= (!!esil_poke_n (esil, bits));
} else ret = 0;
} else {
ret = 0;
}
}
if (!ret)
if (!ret) {
ERR ("esil_mem_muleq_n: invalid parameters");
}
free (dst);
free (src0);
free (src1);
@ -2391,10 +2425,13 @@ static int esil_mem_inceq_n(RAnalEsil *esil, int bits) {
r_anal_esil_pushnum (esil, s);
r_anal_esil_push (esil, off);
ret &= (!!esil_poke_n (esil, bits));
} else ret = 0;
} else {
ret = 0;
}
}
if (!ret)
if (!ret) {
ERR ("esil_mem_inceq_n: invalid parameters");
}
free (src);
free (off);
return ret;
@ -2432,10 +2469,13 @@ static int esil_mem_deceq_n(RAnalEsil *esil, int bits) {
r_anal_esil_pushnum (esil, s);
r_anal_esil_push (esil, off);
ret &= (!!esil_poke_n (esil, bits));
} else ret = 0;
} else {
ret = 0;
}
}
if (!ret)
if (!ret) {
ERR ("esil_mem_deceq_n: invalid parameters");
}
free (src);
free (off);
return ret;
@ -2528,10 +2568,13 @@ static int esil_mem_lsreq_n(RAnalEsil *esil, int bits) {
r_anal_esil_pushnum (esil, d);
r_anal_esil_push (esil, dst);
ret &= (!!esil_poke_n (esil, bits));
} else ret = 0;
} else {
ret = 0;
}
}
if (!ret)
if (!ret) {
ERR ("esil_mem_lsreq_n: invalid parameters");
}
free (dst);
free (src0);
free (src1);
@ -2558,10 +2601,12 @@ static int esil_mem_lsreq(RAnalEsil *esil) {
static int esil_num(RAnalEsil *esil) {
char *dup_me;
ut64 dup;
if (!esil)
if (!esil) {
return false;
if (!(dup_me = r_anal_esil_pop (esil)))
}
if (!(dup_me = r_anal_esil_pop (esil))) {
return false;
}
if (!r_anal_esil_get_parm (esil, dup_me, &dup)) {
free (dup_me);
return false;
@ -2807,7 +2852,9 @@ static int runword(RAnalEsil *esil, const char *word) {
r_anal_esil_parse (esil, esil->Reil->if_buf);
return 1;
}
if (iscommand (esil, word, &op)) esil->Reil->cmd_count++;
if (iscommand (esil, word, &op)) {
esil->Reil->cmd_count++;
}
return 1;
}
@ -2852,8 +2899,9 @@ static const char *gotoWord(const char *str, int n) {
const char *ostr = str;
int count = 0;
while (*str) {
if (count == n)
if (count == n) {
return ostr;
}
str++;
if (*str == ',') {
ostr = str + 1;
@ -3018,7 +3066,9 @@ R_API int r_anal_esil_condition(RAnalEsil *esil, const char *str) {
if (!esil) {
return false;
}
while (*str == ' ') str++; // use proper string chop?
while (*str == ' ') {
str++; // use proper string chop?
}
(void) r_anal_esil_parse (esil, str);
popped = r_anal_esil_pop (esil);
if (popped) {
@ -3171,7 +3221,9 @@ static void r_anal_esil_setup_ops(RAnalEsil *esil) {
/* register callbacks using this anal module. */
R_API int r_anal_esil_setup(RAnalEsil *esil, RAnal *anal, int romem, int stats, int nonull) {
if (!esil) return false;
if (!esil) {
return false;
}
//esil->debug = 0;
esil->anal = anal;
esil->parse_goto_count = anal->esil_goto_limit;

120
libr/anal/esil2reil.c
View File

@ -66,7 +66,9 @@ RAnalReilArg *reil_pop_arg(RAnalEsil *esil) {
continue;
}
// Strip all spaces
if (buf[i] == ' ') continue;
if (buf[i] == ' ') {
continue;
}
tmp_buf[j] = buf[i];
j++;
}
@ -99,7 +101,9 @@ void get_next_temp_reg(RAnalEsil *esil, char *buf) {
}
void reil_make_arg(RAnalEsil *esil, RAnalReilArg *arg, char *name) {
if (!arg) return;
if (!arg) {
return;
}
RAnalReilArgType type;
type = reil_get_arg_type(esil, name);
arg->size = 0;
@ -110,7 +114,9 @@ void reil_make_arg(RAnalEsil *esil, RAnalReilArg *arg, char *name) {
// Free ins and all its arguments
void reil_free_inst(RAnalReilInst *ins) {
if (!ins) return;
if (!ins) {
return;
}
if (ins->arg[0]) R_FREE(ins->arg[0]);
if (ins->arg[1]) R_FREE(ins->arg[1]);
if (ins->arg[2]) R_FREE(ins->arg[2]);
@ -166,18 +172,22 @@ void reil_cast_size(RAnalEsil *esil, RAnalReilArg *src, RAnalReilArg *dst) {
snprintf (tmp_buf, REGBUFSZ-1, "0:%d", dst->size);
r_anal_esil_push (esil, tmp_buf);
ins = R_NEW0 (RAnalReilInst);
if (!ins) return;
if (!ins) {
return;
}
ins->opcode = REIL_OR;
ins->arg[0] = src;
ins->arg[1] = reil_pop_arg (esil);
ins->arg[2] = R_NEW0(RAnalReilArg);
get_next_temp_reg (esil, tmp_buf);
reil_make_arg (esil, ins->arg[2], tmp_buf);
if (ins->arg[2])
if (ins->arg[2]) {
ins->arg[2]->size = dst->size;
}
reil_print_inst (esil, ins);
if (ins->arg[2])
if (ins->arg[2]) {
reil_push_arg (esil, ins->arg[2]);
}
reil_free_inst (ins);
}
@ -189,7 +199,9 @@ static int reil_eq(RAnalEsil *esil) {
RAnalReilArg *dst, *src;
dst = reil_pop_arg (esil);
if (!dst) return false;
if (!dst) {
return false;
}
src = reil_pop_arg (esil);
if (!src) {
R_FREE (dst);
@ -205,7 +217,9 @@ static int reil_eq(RAnalEsil *esil) {
} else if (src_type == ARG_REG) {
// No direct register to register transfer.
ins = R_NEW0 (RAnalReilInst);
if (!ins) return false;
if (!ins) {
return false;
}
ins->opcode = REIL_STR;
ins->arg[0] = src;
ins->arg[1] = R_NEW0 (RAnalReilArg);
@ -307,7 +321,9 @@ static int reil_binop(RAnalEsil *esil, RAnalReilOpcode opcode) {
RAnalReilArg *op2, *op1;
op2 = reil_pop_arg(esil);
if (!op2) return false;
if (!op2) {
return false;
}
op1 = reil_pop_arg(esil);
if (!op1) {
R_FREE (op2);
@ -336,11 +352,13 @@ static int reil_binop(RAnalEsil *esil, RAnalReilOpcode opcode) {
reil_make_arg(esil, ins->arg[2], tmp_buf);
// Choose the larger of the two sizes as the size of dst
dst_size = ins->arg[0]->size;
if (dst_size < ins->arg[1]->size)
if (dst_size < ins->arg[1]->size) {
dst_size = ins->arg[1]->size;
}
// REIL_LT has a dst_size of 1.
if (opcode == REIL_LT)
if (opcode == REIL_LT) {
dst_size = 1;
}
ins->arg[2]->size = dst_size;
reil_print_inst(esil, ins);
reil_push_arg(esil, ins->arg[2]);
@ -352,7 +370,9 @@ static int reil_binop(RAnalEsil *esil, RAnalReilOpcode opcode) {
static int reil_bineqop(RAnalEsil *esil, RAnalReilOpcode opcode) {
int ret = 1;
RAnalReilArg *op = reil_pop_arg(esil);
if (!op) return false;
if (!op) {
return false;
}
reil_push_arg(esil, op);
ret &= reil_binop(esil, opcode);
@ -388,7 +408,9 @@ static int reil_cmp(RAnalEsil *esil) {
RAnalReilArg *op2, *op1;
op2 = reil_pop_arg (esil);
if (!op2) return false;
if (!op2) {
return false;
}
op1 = reil_pop_arg (esil);
if (!op1) {
R_FREE (op2);
@ -432,7 +454,9 @@ static int reil_smaller_equal(RAnalEsil *esil) {
RAnalReilArg *op2, *op1;
op2 = reil_pop_arg(esil);
if (!op2) return false;
if (!op2) {
return false;
}
op1 = reil_pop_arg(esil);
if (!op1) {
R_FREE (op2);
@ -474,7 +498,9 @@ static int reil_larger_equal(RAnalEsil *esil) {
RAnalReilArg *op2, *op1;
op2 = reil_pop_arg(esil);
if (!op2) return false;
if (!op2) {
return false;
}
op1 = reil_pop_arg(esil);
if (!op1) {
R_FREE (op2);
@ -516,7 +542,9 @@ static int reil_deceq(RAnalEsil *esil) {
static int reil_inc(RAnalEsil *esil) {
RAnalReilArg *op = reil_pop_arg(esil);
if (!op) return false;
if (!op) {
return false;
}
r_anal_esil_pushnum(esil, 1);
reil_push_arg(esil, op);
@ -565,8 +593,9 @@ static int reil_neg(RAnalEsil *esil) {
}
get_next_temp_reg (esil, tmp_buf);
reil_make_arg(esil, ins->arg[2], tmp_buf);
if (ins->arg[0]->size < ins->arg[1]->size)
if (ins->arg[0]->size < ins->arg[1]->size) {
ins->arg[1]->size = ins->arg[0]->size;
}
ins->arg[2]->size = 1;
reil_print_inst (esil, ins);
@ -577,7 +606,9 @@ static int reil_neg(RAnalEsil *esil) {
static int reil_negeq(RAnalEsil *esil) {
RAnalReilArg *op = reil_pop_arg(esil);
if (!op) return false;
if (!op) {
return false;
}
reil_push_arg (esil, op);
reil_neg (esil);
reil_push_arg (esil, op);
@ -590,7 +621,9 @@ static int reil_not(RAnalEsil *esil) {
char tmp_buf[REGBUFSZ];
RAnalReilInst *ins;
RAnalReilArg *op = reil_pop_arg (esil);
if (!op) return false;
if (!op) {
return false;
}
ins = R_NEW0 (RAnalReilInst);
if (!ins) {
@ -624,7 +657,9 @@ static int reil_if(RAnalEsil *esil) {
RAnalReilArg *op2, *op1;
op2 = reil_pop_arg (esil);
if (!op2) return false;
if (!op2) {
return false;
}
op1 = reil_pop_arg (esil);
if (!op1) {
R_FREE (op2);
@ -657,7 +692,9 @@ static int reil_peek(RAnalEsil *esil) {
RAnalReilInst *ins;
char tmp_buf[REGBUFSZ];
RAnalReilArg *op1 = reil_pop_arg(esil);
if (!op1) return false;
if (!op1) {
return false;
}
ins = R_NEW0 (RAnalReilInst);
if (!ins) {
@ -690,7 +727,9 @@ static int reil_peek(RAnalEsil *esil) {
static int reil_peekn(RAnalEsil *esil, ut8 n) {
RAnalReilArg *op2;
RAnalReilArg *op1 = reil_pop_arg (esil);
if (!op1) return false;
if (!op1) {
return false;
}
reil_push_arg (esil, op1);
reil_peek (esil);
@ -702,7 +741,9 @@ static int reil_peekn(RAnalEsil *esil, ut8 n) {
R_FREE (op1);
op1 = reil_pop_arg (esil);
if (!op1) return false;
if (!op1) {
return false;
}
op2 = R_NEW0 (RAnalReilArg);
if (!op2) {
@ -731,7 +772,9 @@ static int reil_poken(RAnalEsil *esil, ut8 n) {
RAnalReilArg *op2, *op1;
op2 = reil_pop_arg (esil);
if (!op2) return false;
if (!op2) {
return false;
}
op1 = reil_pop_arg (esil);
if (!op1) {
R_FREE (op2);
@ -784,7 +827,9 @@ static int reil_poken(RAnalEsil *esil, ut8 n) {
}
ins = R_NEW0 (RAnalReilInst);
if (!ins) return false;
if (!ins) {
return false;
}
ins->opcode = REIL_STM;
ins->arg[2] = reil_pop_arg (esil);
ins->arg[0] = reil_pop_arg (esil);
@ -814,7 +859,9 @@ static int reil_mem_bineq_n(RAnalEsil *esil, RAnalReilOpcode opcode, ut8 size) {
RAnalReilArg *op2, *op1;
op2 = reil_pop_arg (esil);
if (!op2) return false;
if (!op2) {
return false;
}
op1 = reil_pop_arg (esil);
if (!op1) {
R_FREE (op2);
@ -872,7 +919,9 @@ static int reil_mem_muleq8(RAnalEsil *esil) { return reil_mem_bineq_n(esil, REIL
static int reil_mem_inceq_n(RAnalEsil *esil, ut8 size) {
int ret = 1;
RAnalReilArg *op1 = reil_pop_arg(esil);
if (!op1) return false;
if (!op1) {
return false;
}
r_anal_esil_pushnum(esil, 1);
reil_push_arg(esil, op1);
@ -893,7 +942,9 @@ static int reil_mem_inceq8(RAnalEsil *esil) { return reil_mem_inceq_n(esil, 8);
static int reil_mem_deceq_n(RAnalEsil *esil, ut8 size) {
int ret = 1;
RAnalReilArg *op1 = reil_pop_arg(esil);
if (!op1) return false;
if (!op1) {
return false;
}
r_anal_esil_pushnum(esil, 1);
reil_push_arg(esil, op1);
@ -976,7 +1027,9 @@ void reil_generate_partity_flag(RAnalEsil *esil) {
r_anal_esil_pushnum(esil, 0xff);
reil_and(esil);
op = reil_pop_arg(esil);
if (!op) return;
if (!op) {
return;
}
r_anal_esil_pushnum(esil, 7);
reil_push_arg(esil, op);
@ -1029,7 +1082,9 @@ void reil_generate_signature(RAnalEsil *esil) {
reil_and(esil);
op = reil_pop_arg(esil);
if (!op) return;
if (!op) {
return;
}
r_anal_esil_pushnum(esil, esil->Reil->lastsz - 1);
reil_push_arg(esil, op);
@ -1039,8 +1094,9 @@ void reil_generate_signature(RAnalEsil *esil) {
}
void reil_generate_overflow_flag(RAnalEsil *esil) {
if (esil->Reil->lastsz < 2)
r_anal_esil_pushnum(esil, 0);
if (esil->Reil->lastsz < 2) {
r_anal_esil_pushnum (esil, 0);
}
reil_generate_borrow_flag(esil, esil->Reil->lastsz);
reil_generate_carry_flag(esil, esil->Reil->lastsz - 2);

6
libr/anal/esil_stats.c
View File

@ -48,9 +48,11 @@ R_API void r_anal_esil_mem_ro(RAnalEsil *esil, int mem_readonly) {
R_API void r_anal_esil_stats(RAnalEsil *esil, int enable) {
if (enable) {
if (esil->stats)
if (esil->stats) {
sdb_reset (esil->stats);
else esil->stats = sdb_new0();
} else {
esil->stats = sdb_new0 ();
}
// reset sdb->stats
esil->cb.hook_reg_read = hook_reg_read;
esil->cb.hook_mem_read = hook_mem_read;

6
libr/anal/labels.c
View File

@ -40,8 +40,9 @@ R_API int r_anal_fcn_label_set (RAnal *anal, RAnalFunction *fcn, const char *nam
}
R_API int r_anal_fcn_label_del (RAnal *anal, RAnalFunction *fcn, const char *name, ut64 addr) {
if (!anal || !fcn || !name)
if (!anal || !fcn || !name) {
return false;
}
sdb_array_remove (DB, LABELS, ADDRLABEL (addr, name), 0);
sdb_unset (DB, LABEL (name), 0);
sdb_unset (DB, ADDR (addr), 0);
@ -61,8 +62,9 @@ R_API int r_anal_fcn_labels(RAnal *anal, RAnalFunction *fcn, int rad) {
char *name;
} loc;
token = strchr (cur, '/');
if (!token)
if (!token) {
break;
}
*token = ',';
sdb_fmt_tobin (cur, "qz", &loc);
switch (rad) {

21
libr/anal/meta.c
View File

@ -226,7 +226,9 @@ R_API int r_meta_del(RAnal *a, int type, ut64 addr, ut64 size) {
"meta.%c.0x%"PFMT64x,
type, sdb_atoi (s));
sdb_unset (DB, key, 0);
if (!next) break;
if (!next) {
break;
}
}
free (dtr);
}
@ -298,7 +300,9 @@ R_API void r_meta_item_free(void *_item) {
R_API RAnalMetaItem *r_meta_item_new(int type) {
RAnalMetaItem *mi = R_NEW0 (RAnalMetaItem);
if (mi) mi->type = type;
if (mi) {
mi->type = type;
}
return mi;
}
@ -558,7 +562,9 @@ R_API void r_meta_print(RAnal *a, RAnalMetaItem *d, int rad, bool show_full) {
{
const char *type = r_meta_type_to_string (d->type);
char *s = sdb_encode ((const ut8*)pstr, -1);
if (!s) s = strdup (pstr);
if (!s) {
s = strdup (pstr);
}
if (rad) {
if (!strcmp (type, "CCu")) {
a->cb_printf ("%s base64:%s @ 0x%08"PFMT64x"\n",
@ -668,8 +674,9 @@ R_API void r_meta_print(RAnal *a, RAnalMetaItem *d, int rad, bool show_full) {
}
break;
}
if (str)
if (str) {
free (str);
}
}
}
@ -764,8 +771,9 @@ static int meta_unset_cb(void *user, const char *k, const char *v) {
RAnalMetaUserItem *ui = user;
RAnal *a = ui->anal;
RAnalMetaItem it = {0};
if (!strstr(k, ".0x"))
if (!strstr (k, ".0x")) {
return 1;
}
meta_deserialize (&it, k, v);
if (it.space != -1) {
it.space = -1;
@ -789,8 +797,9 @@ static int meta_count_cb(void *user, const char *k, const char *v) {
RAnalMetaUserItem *ui = user;
myMetaUser *mu = ui->user;
RAnalMetaItem it = {0};
if (!strstr(k, ".0x"))
if (!strstr (k, ".0x")) {
return 1;
}
meta_deserialize (&it, k, v);
if (mu) {
if (it.space == mu->ctx) {

84
libr/anal/op.c
View File

@ -238,8 +238,10 @@ R_API int r_anal_op_execute(RAnal *anal, RAnalOp *op) {
if (div == 0) {
eprintf ("r_anal_op_execute: division by zero\n");
eprintf ("TODO: throw RAnalException\n");
} else r_anal_value_set_ut64 (anal, op->dst,
r_anal_value_to_ut64 (anal, op->src[0])/div);
} else {
r_anal_value_set_ut64 (anal, op->dst,
r_anal_value_to_ut64 (anal, op->src[0]) / div);
}
}
break;
case R_ANAL_OP_TYPE_MUL:
@ -392,9 +394,15 @@ R_API char *r_anal_op_to_string(RAnal *anal, RAnalOp *op) {
char *r0 = r_anal_value_to_string (op->dst);
char *a0 = r_anal_value_to_string (op->src[0]);
char *a1 = r_anal_value_to_string (op->src[1]);
if (!r0) r0 = strdup ("?");
if (!a0) a0 = strdup ("?");
if (!a1) a1 = strdup ("?");
if (!r0) {
r0 = strdup ("?");
}
if (!a0) {
a0 = strdup ("?");
}
if (!a1) {
a1 = strdup ("?");
}
switch (op->type) {
case R_ANAL_OP_TYPE_MOV:
@ -443,12 +451,18 @@ R_API char *r_anal_op_to_string(RAnal *anal, RAnalOp *op) {
f = r_anal_get_fcn_in (anal, op->jump, R_ANAL_FCN_TYPE_NULL);
if ((bb = r_anal_bb_from_offset (anal, op->addr))) {
cstr = r_anal_cond_to_string (bb->cond);
if (f) snprintf (ret, sizeof (ret), "if (%s) %s()", cstr, f->name);
else snprintf (ret, sizeof (ret), "if (%s) 0x%"PFMT64x"()", cstr, op->jump);
if (f) {
snprintf (ret, sizeof (ret), "if (%s) %s()", cstr, f->name);
} else {
snprintf (ret, sizeof (ret), "if (%s) 0x%" PFMT64x "()", cstr, op->jump);
}
free (cstr);
} else {
if (f) snprintf (ret, sizeof (ret), "if (unk) %s()", f->name);
else snprintf (ret, sizeof (ret), "if (unk) 0x%"PFMT64x"()", op->jump);
if (f) {
snprintf (ret, sizeof (ret), "if (unk) %s()", f->name);
} else {
snprintf (ret, sizeof (ret), "if (unk) 0x%" PFMT64x "()", op->jump);
}
}
break;
case R_ANAL_OP_TYPE_ADD:
@ -475,22 +489,30 @@ R_API char *r_anal_op_to_string(RAnal *anal, RAnalOp *op) {
case R_ANAL_OP_TYPE_DIV:
if (!a1 || !strcmp (a0, a1)) {
snprintf (ret, sizeof (ret), "%s /= %s", r0, a0);
} else snprintf (ret, sizeof (ret), "%s = %s / %s", r0, a0, a1);
} else {
snprintf (ret, sizeof (ret), "%s = %s / %s", r0, a0, a1);
}
break;
case R_ANAL_OP_TYPE_AND:
if (!a1 || !strcmp (a0, a1)) {
snprintf (ret, sizeof (ret), "%s &= %s", r0, a0);
} else snprintf (ret, sizeof (ret), "%s = %s & %s", r0, a0, a1);
} else {
snprintf (ret, sizeof (ret), "%s = %s & %s", r0, a0, a1);
}
break;
case R_ANAL_OP_TYPE_OR:
if (!a1 || !strcmp (a0, a1)) {
snprintf (ret, sizeof (ret), "%s |= %s", r0, a0);
} else snprintf (ret, sizeof (ret), "%s = %s | %s", r0, a0, a1);
} else {
snprintf (ret, sizeof (ret), "%s = %s | %s", r0, a0, a1);
}
break;
case R_ANAL_OP_TYPE_XOR:
if (!a1 || !strcmp (a0, a1)) {
snprintf (ret, sizeof (ret), "%s ^= %s", r0, a0);
} else snprintf (ret, sizeof (ret), "%s = %s ^ %s", r0, a0, a1);
} else {
snprintf (ret, sizeof (ret), "%s = %s ^ %s", r0, a0, a1);
}
break;
case R_ANAL_OP_TYPE_LEA:
snprintf (ret, sizeof (ret), "%s -> %s", r0, a0);
@ -587,15 +609,33 @@ R_API const char *r_anal_op_family_to_string(int n) {
R_API int r_anal_op_family_from_string(const char *f) {
// TODO: use array of strings or so ..
if (!strcmp (f, "cpu")) return R_ANAL_OP_FAMILY_CPU;
if (!strcmp (f, "fpu")) return R_ANAL_OP_FAMILY_FPU;
if (!strcmp (f, "mmx")) return R_ANAL_OP_FAMILY_MMX;
if (!strcmp (f, "sse")) return R_ANAL_OP_FAMILY_SSE;
if (!strcmp (f, "priv")) return R_ANAL_OP_FAMILY_PRIV;
if (!strcmp (f, "virt")) return R_ANAL_OP_FAMILY_VIRT;
if (!strcmp (f, "crpt")) return R_ANAL_OP_FAMILY_CRYPTO;
if (!strcmp (f, "io")) return R_ANAL_OP_FAMILY_IO;
if (!strcmp (f, "thrd")) return R_ANAL_OP_FAMILY_THREAD;
if (!strcmp (f, "cpu")) {
return R_ANAL_OP_FAMILY_CPU;
}
if (!strcmp (f, "fpu")) {
return R_ANAL_OP_FAMILY_FPU;
}
if (!strcmp (f, "mmx")) {
return R_ANAL_OP_FAMILY_MMX;
}
if (!strcmp (f, "sse")) {
return R_ANAL_OP_FAMILY_SSE;
}
if (!strcmp (f, "priv")) {
return R_ANAL_OP_FAMILY_PRIV;
}
if (!strcmp (f, "virt")) {
return R_ANAL_OP_FAMILY_VIRT;
}
if (!strcmp (f, "crpt")) {
return R_ANAL_OP_FAMILY_CRYPTO;
}
if (!strcmp (f, "io")) {
return R_ANAL_OP_FAMILY_IO;
}
if (!strcmp (f, "thrd")) {
return R_ANAL_OP_FAMILY_THREAD;
}
return R_ANAL_OP_FAMILY_UNKNOWN;
}

84
libr/anal/p/anal_6502.c
View File

@ -28,10 +28,18 @@ enum {
static void _6502_anal_update_flags(RAnalOp *op, int flags) {
/* FIXME: $b9 instead of $b8 to prevent the bug triggered by: A = 0 - 0xff - 1 */
if (flags & _6502_FLAGS_B) r_strbuf_append (&op->esil, ",$b9,C,=");
if (flags & _6502_FLAGS_C) r_strbuf_append (&op->esil, ",$c7,C,=");
if (flags & _6502_FLAGS_Z) r_strbuf_append (&op->esil, ",$z,Z,=");
if (flags & _6502_FLAGS_N) r_strbuf_append (&op->esil, ",$s,N,=");
if (flags & _6502_FLAGS_B) {
r_strbuf_append (&op->esil, ",$b9,C,=");
}
if (flags & _6502_FLAGS_C) {
r_strbuf_append (&op->esil, ",$c7,C,=");
}
if (flags & _6502_FLAGS_Z) {
r_strbuf_append (&op->esil, ",$z,Z,=");
}
if (flags & _6502_FLAGS_N) {
r_strbuf_append (&op->esil, ",$s,N,=");
}
}
/* ORA, AND, EOR, ADC, STA, LDA, CMP and SBC share this pattern */
@ -235,7 +243,9 @@ static void _6502_anal_esil_mov(RAnalOp *op, ut8 data0) {
r_strbuf_setf (&op->esil, "%s,%s,=",src,dst);
// don't update NZ on txs
if (data0 != 0x9a) _6502_anal_update_flags (op, _6502_FLAGS_NZ);
if (data0 != 0x9a) {
_6502_anal_update_flags (op, _6502_FLAGS_NZ);
}
}
static void _6502_anal_esil_push(RAnalOp *op, ut8 data0) {
@ -253,7 +263,9 @@ static void _6502_anal_esil_pop(RAnalOp *op, ut8 data0) {
// stack is on page one: sp + 0x100
r_strbuf_setf (&op->esil, "sp,++=,sp,0x100,+,[1],%s,=", reg);
if (data0==0x68) _6502_anal_update_flags (op, _6502_FLAGS_NZ);
if (data0 == 0x68) {
_6502_anal_update_flags (op, _6502_FLAGS_NZ);
}
}
static void _6502_anal_esil_flags(RAnalOp *op, ut8 data0) {
@ -463,9 +475,11 @@ static int _6502_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int le
// FIXME: support BCD mode
op->type = R_ANAL_OP_TYPE_ADD;
_6502_anal_esil_get_addr_pattern1 (op, data, len, addrbuf, buffsize);
if (data[0] == 0x69) // immediate mode
if (data[0] == 0x69) { // immediate mode
r_strbuf_setf (&op->esil, "%s,a,+=,C,NUM,$c7,C,=,a,+=,$c7,C,|=", addrbuf);
else r_strbuf_setf (&op->esil, "%s,[1],a,+=,C,NUM,$c7,C,=,a,+=,$c7,C,|=", addrbuf);
} else {
r_strbuf_setf (&op->esil, "%s,[1],a,+=,C,NUM,$c7,C,=,a,+=,$c7,C,|=", addrbuf);
}
_6502_anal_update_flags (op, _6502_FLAGS_NZ);
// fix Z
r_strbuf_append (&op->esil, ",a,a,=,$z,Z,=");
@ -483,9 +497,11 @@ static int _6502_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int le
// FIXME: support BCD mode
op->type = R_ANAL_OP_TYPE_SUB;
_6502_anal_esil_get_addr_pattern1 (op, data, len, addrbuf, buffsize);
if (data[0] == 0xe9) // immediate mode
if (data[0] == 0xe9) { // immediate mode
r_strbuf_setf (&op->esil, "C,!,%s,+,a,-=", addrbuf);
else r_strbuf_setf (&op->esil, "C,!,%s,[1],+,a,-=", addrbuf);
} else {
r_strbuf_setf (&op->esil, "C,!,%s,[1],+,a,-=", addrbuf);
}
_6502_anal_update_flags (op, _6502_FLAGS_BNZ);
// fix Z and revert C
r_strbuf_append (&op->esil, ",a,a,=,$z,Z,=,C,!=");
@ -501,9 +517,11 @@ static int _6502_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int le
case 0x11: // ora ($ff),y
op->type = R_ANAL_OP_TYPE_OR;
_6502_anal_esil_get_addr_pattern1 (op, data, len, addrbuf, buffsize);
if (data[0] == 0x09) // immediate mode
if (data[0] == 0x09) { // immediate mode
r_strbuf_setf (&op->esil, "%s,a,|=", addrbuf);
else r_strbuf_setf (&op->esil, "%s,[1],a,|=", addrbuf);
} else {
r_strbuf_setf (&op->esil, "%s,[1],a,|=", addrbuf);
}
_6502_anal_update_flags (op, _6502_FLAGS_NZ);
break;
// AND
@ -517,9 +535,11 @@ static int _6502_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int le
case 0x31: // and ($ff),y
op->type = R_ANAL_OP_TYPE_AND;
_6502_anal_esil_get_addr_pattern1 (op, data, len, addrbuf, buffsize);
if (data[0] == 0x29) // immediate mode
if (data[0] == 0x29) { // immediate mode
r_strbuf_setf (&op->esil, "%s,a,&=", addrbuf);
else r_strbuf_setf (&op->esil, "%s,[1],a,&=", addrbuf);
} else {
r_strbuf_setf (&op->esil, "%s,[1],a,&=", addrbuf);
}
_6502_anal_update_flags (op, _6502_FLAGS_NZ);
break;
// EOR
@ -533,9 +553,11 @@ static int _6502_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int le
case 0x51: // eor ($ff),y
op->type = R_ANAL_OP_TYPE_XOR;
_6502_anal_esil_get_addr_pattern1 (op, data, len, addrbuf, buffsize);
if (data[0] == 0x49) // immediate mode
if (data[0] == 0x49) { // immediate mode
r_strbuf_setf (&op->esil, "%s,a,^=", addrbuf);
else r_strbuf_setf (&op->esil, "%s,[1],a,^=", addrbuf);
} else {
r_strbuf_setf (&op->esil, "%s,[1],a,^=", addrbuf);
}
_6502_anal_update_flags (op, _6502_FLAGS_NZ);
break;
// ASL
@ -645,9 +667,11 @@ static int _6502_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int le
case 0xd1: // cmp ($ff),y
op->type = R_ANAL_OP_TYPE_CMP;
_6502_anal_esil_get_addr_pattern1 (op, data, len, addrbuf, buffsize);
if (data[0] == 0xc9) // immediate mode
if (data[0] == 0xc9) { // immediate mode
r_strbuf_setf (&op->esil, "%s,a,==", addrbuf);
else r_strbuf_setf (&op->esil, "%s,[1],a,==", addrbuf);
} else {
r_strbuf_setf (&op->esil, "%s,[1],a,==", addrbuf);
}
_6502_anal_update_flags (op, _6502_FLAGS_BNZ);
// invert C, since C=1 when A-M >= 0
r_strbuf_append (&op->esil, ",C,!,C,=");
@ -658,9 +682,11 @@ static int _6502_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int le
case 0xec: // cpx $ffff
op->type = R_ANAL_OP_TYPE_CMP;
_6502_anal_esil_get_addr_pattern3 (op, data, len, addrbuf, buffsize, 0);
if (data[0] == 0xe0) // immediate mode
if (data[0] == 0xe0) { // immediate mode
r_strbuf_setf (&op->esil, "%s,x,==", addrbuf);
else r_strbuf_setf (&op->esil, "%s,[1],x,==", addrbuf);
} else {
r_strbuf_setf (&op->esil, "%s,[1],x,==", addrbuf);
}
_6502_anal_update_flags (op, _6502_FLAGS_BNZ);
// invert C, since C=1 when A-M >= 0
r_strbuf_append (&op->esil, ",C,!,C,=");
@ -671,9 +697,11 @@ static int _6502_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int le
case 0xcc: // cpy $ffff
op->type = R_ANAL_OP_TYPE_CMP;
_6502_anal_esil_get_addr_pattern3 (op, data, len, addrbuf, buffsize, 0);
if (data[0] == 0xc0) // immediate mode
if (data[0] == 0xc0) { // immediate mode
r_strbuf_setf (&op->esil, "%s,y,==", addrbuf);
else r_strbuf_setf (&op->esil, "%s,[1],y,==", addrbuf);
} else {
r_strbuf_setf (&op->esil, "%s,[1],y,==", addrbuf);
}
_6502_anal_update_flags (op, _6502_FLAGS_BNZ);
// invert C, since C=1 when A-M >= 0
r_strbuf_append (&op->esil, ",C,!,C,=");
@ -770,9 +798,11 @@ static int _6502_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int le
case 0xb1: // lda ($ff),y
op->type = R_ANAL_OP_TYPE_LOAD;
_6502_anal_esil_get_addr_pattern1 (op, data, len, addrbuf, buffsize);
if (data[0] == 0xa9) // immediate mode
if (data[0] == 0xa9) { // immediate mode
r_strbuf_setf (&op->esil, "%s,a,=", addrbuf);
else r_strbuf_setf (&op->esil, "%s,[1],a,=", addrbuf);
} else {
r_strbuf_setf (&op->esil, "%s,[1],a,=", addrbuf);
}
_6502_anal_update_flags (op, _6502_FLAGS_NZ);
break;
// LDX
@ -798,9 +828,11 @@ static int _6502_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int le
case 0xbc: // ldy $ffff,x
op->type = R_ANAL_OP_TYPE_LOAD;
_6502_anal_esil_get_addr_pattern3 (op, data, len, addrbuf, buffsize, 'x');
if (data[0] == 0xa0) // immediate mode
if (data[0] == 0xa0) { // immediate mode
r_strbuf_setf (&op->esil, "%s,y,=", addrbuf);
else r_strbuf_setf (&op->esil, "%s,[1],y,=", addrbuf);
} else {
r_strbuf_setf (&op->esil, "%s,[1],y,=", addrbuf);
}
_6502_anal_update_flags (op, _6502_FLAGS_NZ);
break;
// STA

3
libr/anal/p/anal_arc.c
View File

@ -1017,8 +1017,9 @@ static int arc_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int len)
const ut8 *b = (ut8 *)data;
memset (op, '\0', sizeof (RAnalOp));
if (anal->bits == 16)
if (anal->bits == 16) {
return arcompact_op (anal, op, addr, data, len);
}
/* ARCtangent A4 */
op->size = 4;

22
libr/anal/p/anal_avr.c
View File

@ -199,8 +199,9 @@ static CPU_CONST *const_by_name(CPU_MODEL *cpu, int type, char *c) {
}
}
}
if (cpu->inherit_cpu_p)
if (cpu->inherit_cpu_p) {
return const_by_name (cpu->inherit_cpu_p, type, c);
}
eprintf ("ERROR: CONSTANT key[%s] NOT FOUND.\n", c);
return NULL;
}
@ -226,8 +227,9 @@ static CPU_CONST *const_by_value(CPU_MODEL *cpu, int type, ut32 v) {
}
}
}
if (cpu->inherit_cpu_p)
if (cpu->inherit_cpu_p) {
return const_by_value (cpu->inherit_cpu_p, type, v);
}
return NULL;
}
@ -365,10 +367,11 @@ static void __generic_sub_update_flags(RAnalOp *op, char t_d, ut64 v_d, char t_r
"|,vf,=,",
d, rk, d, rk);
ESIL_A ("0,RPICK,0x80,&,!,!,nf,=,"); // N
if (carry)
if (carry) {
ESIL_A ("0,RPICK,!,zf,&,zf,=,"); // Z
else
ESIL_A ("0,RPICK,!,zf,=,"); // Z
} else {
ESIL_A ("0,RPICK,!,zf,=,"); // Z
}
ESIL_A ("%s,0x80,&,!," "%s,0x80,&,!,!," "&," // C
"%s,0x80,&,!,!," "0,RPICK,0x80,&,!,!," "&,"
"%s,0x80,&,!," "0,RPICK,0x80,&,!,!," "&,"
@ -2131,12 +2134,15 @@ RAMPX, RAMPY, RAMPZ, RAMPD and EIND:
}
static int archinfo(RAnal *anal, int q) {
if (q == R_ANAL_ARCHINFO_ALIGN)
if (q == R_ANAL_ARCHINFO_ALIGN) {
return 2;
if (q == R_ANAL_ARCHINFO_MAX_OP_SIZE)
}
if (q == R_ANAL_ARCHINFO_MAX_OP_SIZE) {
return 4;
if (q == R_ANAL_ARCHINFO_MIN_OP_SIZE)
}
if (q == R_ANAL_ARCHINFO_MIN_OP_SIZE) {
return 2;
}
return 2; // XXX
}

6
libr/anal/p/anal_bf.c
View File

@ -9,8 +9,9 @@
static int countChar (const ut8 *buf, int len, char ch) {
int i;
for (i = 0; i < len; i++) {
if (buf[i] != ch)
if (buf[i] != ch) {
break;
}
}
return i;
}
@ -45,8 +46,9 @@ static int bf_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf, int len) {
int lev = 0, i = 1;
len--;
while (i < len && *p) {
if (*p == '[')
if (*p == '[') {
lev++;
}
if (*p == ']') {
lev--;
if (lev==-1) {

9
libr/anal/p/anal_ebc.c
View File

@ -24,8 +24,9 @@ static void ebc_anal_jmp8(RAnalOp *op, ut64 addr, const ut8 *buf) {
static void ebc_anal_jmp(RAnalOp *op, ut64 addr, const ut8 *buf) {
op->fail = addr + 6;
op->jump = (ut64)*(int32_t*)(buf + 2);
if (TEST_BIT(buf[1], 4))
if (TEST_BIT (buf[1], 4)) {
op->jump += addr + 6;
}
if (buf[1] & 0x7) {
op->type = R_ANAL_OP_TYPE_UJMP;
} else {
@ -61,8 +62,9 @@ static int ebc_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf, int len)
ebc_command_t cmd;
ut8 opcode = buf[0] & EBC_OPCODE_MASK;
if (!op)
if (!op) {
return 2;
}
memset(op, 0, sizeof (RAnalOp));
op->addr = addr;
@ -71,8 +73,9 @@ static int ebc_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf, int len)
ret = op->size = ebc_decode_command(buf, &cmd);
if (ret < 0)
if (ret < 0) {
return ret;
}
switch (opcode) {
case EBC_JMP8:

279
libr/anal/p/anal_gb.c
View File

@ -28,9 +28,11 @@ static ut8 gb_op_calljump(RAnal *a, RAnalOp *op, const ut8 *data, ut64 addr)
r_meta_set_string (a, R_META_TYPE_COMMENT, addr, "--> unpredictable");
return false;
}
if (!GB_IS_VBANK_DST (data[1], data[2]))
if (!GB_IS_VBANK_DST (data[1], data[2])) {
op->jump = GB_SOFTCAST(data[1], data[2]);
else op->jump = GB_IB_DST (data[1], data[2], addr);
} else {
op->jump = GB_IB_DST (data[1], data[2], addr);
}
return true;
}
@ -66,9 +68,11 @@ static inline void gb_anal_esil_ccall (RAnalOp *op, const ut8 data)
default:
cond = 'C';
}
if (op->cond == R_ANAL_COND_EQ)
if (op->cond == R_ANAL_COND_EQ) {
r_strbuf_setf (&op->esil, "%c,?{,2,sp,-=,pc,sp,=[2],%"PFMT64d",pc,=,}", cond, (op->jump & 0xffff));
else r_strbuf_setf (&op->esil, "%c,!,?{,2,sp,-=,pc,sp,=[2],%"PFMT64d",pc,=,}", cond, (op->jump & 0xffff));
} else {
r_strbuf_setf (&op->esil, "%c,!,?{,2,sp,-=,pc,sp,=[2],%" PFMT64d ",pc,=,}", cond, (op->jump & 0xffff));
}
}
static inline void gb_anal_esil_ret (RAnalOp *op)
@ -79,12 +83,16 @@ static inline void gb_anal_esil_ret (RAnalOp *op)
static inline void gb_anal_esil_cret (RAnalOp *op, const ut8 data)
{
char cond;
if ((data & 0xd0) == 0xd0)
if ((data & 0xd0) == 0xd0) {
cond = 'C';
else cond = 'Z';
if (op->cond == R_ANAL_COND_EQ)
} else {
cond = 'Z';
}
if (op->cond == R_ANAL_COND_EQ) {
r_strbuf_setf (&op->esil, "%c,?{,sp,[2],pc,=,2,sp,+=,}", cond);
else r_strbuf_setf (&op->esil, "%c,!,?{,sp,[2],pc,=,2,sp,+=,}", cond);
} else {
r_strbuf_setf (&op->esil, "%c,!,?{,sp,[2],pc,=,2,sp,+=,}", cond);
}
}
static inline void gb_anal_esil_cjmp (RAnalOp *op, const ut8 data)
@ -100,9 +108,11 @@ static inline void gb_anal_esil_cjmp (RAnalOp *op, const ut8 data)
default:
cond = 'C';
}
if (op->cond == R_ANAL_COND_EQ)
if (op->cond == R_ANAL_COND_EQ) {
r_strbuf_setf (&op->esil, "%c,?{,0x%"PFMT64x",pc,=,}", cond, (op->jump & 0xffff));
else r_strbuf_setf (&op->esil, "%c,!,?{,0x%"PFMT64x",pc,=,}", cond, (op->jump & 0xffff));
} else {
r_strbuf_setf (&op->esil, "%c,!,?{,0x%" PFMT64x ",pc,=,}", cond, (op->jump & 0xffff));
}
}
static inline void gb_anal_esil_jmp (RAnalOp *op)
@ -126,20 +136,26 @@ static inline void gb_anal_id (RAnal *anal, RAnalOp *op, const ut8 data) {
if (data == 0x34 || data == 0x35) {
op->dst->memref = 1;
op->dst->reg = r_reg_get (anal->reg, "hl", R_REG_TYPE_GPR);
if (op->type == R_ANAL_OP_TYPE_ADD)
if (op->type == R_ANAL_OP_TYPE_ADD) {
r_strbuf_set (&op->esil, "1,hl,[1],+,hl,=[1],$c3,H,=,$z,Z,=,0,N,=");
else r_strbuf_set (&op->esil, "1,hl,[1],-,hl,=[1],$b4,H,=,$z,Z,=,1,N,=");
} else {
r_strbuf_set (&op->esil, "1,hl,[1],-,hl,=[1],$b4,H,=,$z,Z,=,1,N,=");
}
} else {
if (!(data & (1<<2))) {
op->dst->reg = r_reg_get (anal->reg, regs_16[data>>4], R_REG_TYPE_GPR);
if (op->type == R_ANAL_OP_TYPE_ADD)
if (op->type == R_ANAL_OP_TYPE_ADD) {
r_strbuf_setf (&op->esil, "1,%s,+=", regs_16[data>>4]);
else r_strbuf_setf (&op->esil, "1,%s,-=", regs_16[data>>4]);
} else {
r_strbuf_setf (&op->esil, "1,%s,-=", regs_16[data >> 4]);
}
} else {
op->dst->reg = r_reg_get (anal->reg, regs_8[data>>3], R_REG_TYPE_GPR);
if (op->type == R_ANAL_OP_TYPE_ADD)
if (op->type == R_ANAL_OP_TYPE_ADD) {
r_strbuf_setf (&op->esil, "1,%s,+=,$c3,H,=,$z,Z,=,0,N,=", regs_8[data>>3]);
else r_strbuf_setf (&op->esil, "1,%s,-=,$b4,H,=,$z,Z,=,1,N,=", regs_8[data>>3]);
} else {
r_strbuf_setf (&op->esil, "1,%s,-=,$b4,H,=,$z,Z,=,1,N,=", regs_8[data >> 3]);
}
}
}
}
@ -157,9 +173,11 @@ static inline void gb_anal_add_sp (RReg *reg, RAnalOp *op, const ut8 data) {
op->src[0] = r_anal_value_new ();
op->dst->reg = r_reg_get (reg, "sp", R_REG_TYPE_GPR);
op->src[0]->imm = (st8)data;
if (data < 128)
if (data < 128) {
r_strbuf_setf (&op->esil, "0x%02x,sp,+=", data);
else r_strbuf_setf (&op->esil, "0x%02x,sp,-=", 0 - (st8)data);
} else {
r_strbuf_setf (&op->esil, "0x%02x,sp,-=", 0 - (st8)data);
}
r_strbuf_append (&op->esil, ",0,Z,=,0,N,=");
}
@ -194,9 +212,11 @@ static inline void gb_anal_mov_hl_sp (RReg *reg, RAnalOp *op, const ut8 data) {
op->dst->reg = r_reg_get (reg, regs_16[2], R_REG_TYPE_GPR);
op->src[0]->reg = r_reg_get (reg, regs_16[3], R_REG_TYPE_GPR);
op->src[1]->imm = (st8)data;
if (data < 128)
if (data < 128) {
r_strbuf_setf (&op->esil, "0x%02x,sp,+,hl,=", data);
else r_strbuf_setf (&op->esil, "0x%02x,sp,-,hl,=", 0 - (st8)data);
} else {
r_strbuf_setf (&op->esil, "0x%02x,sp,-,hl,=", 0 - (st8)data);
}
r_strbuf_append (&op->esil, ",0,Z,=,0,N,=");
}
@ -215,8 +235,9 @@ static inline void gb_anal_mov_ime (RReg *reg, RAnalOp *op, const ut8 data) {
op->src[0]->absolute = true;
op->src[0]->imm = (data != 0xf3);
r_strbuf_setf (&op->esil, "%d,ime,=", (int)op->src[0]->imm);
if (data == 0xd9)
if (data == 0xd9) {
r_strbuf_append (&op->esil, ",");
}
}
static inline void gb_anal_mov_scf (RReg *reg, RAnalOp *op) {
@ -247,8 +268,11 @@ static inline void gb_anal_cond (RReg *reg, RAnalOp *op, const ut8 data) {
op->dst = r_anal_value_new ();
op->src[0] = r_anal_value_new ();
op->src[0]->imm = 1;
if (data & 0x8) op->cond = R_ANAL_COND_EQ;
else op->cond = R_ANAL_COND_NE;
if (data & 0x8) {
op->cond = R_ANAL_COND_EQ;
} else {
op->cond = R_ANAL_COND_NE;
}
switch (data) {
case 0x20:
case 0x28:
@ -284,9 +308,11 @@ static inline void gb_anal_and_res (RAnal *anal, RAnalOp *op, const ut8 data) {
op->src[0]->imm = ((~(0x1 << ((data >> 3) & 7))) & 0xff);
op->dst->memref = ((data & 7) == 6);
op->dst->reg = r_reg_get (anal->reg, regs_x[data & 7], R_REG_TYPE_GPR);
if (op->dst->memref)
if (op->dst->memref) {
r_strbuf_setf (&op->esil, "0x%02x,%s,[1],&,%s,=[1]", op->src[0]->imm, regs_x[data & 7], regs_x[data & 7]);
else r_strbuf_setf (&op->esil, "0x%02x,%s,&=", op->src[0]->imm, regs_x[data & 7]);
} else {
r_strbuf_setf (&op->esil, "0x%02x,%s,&=", op->src[0]->imm, regs_x[data & 7]);
}
}
static inline void gb_anal_and_bit (RReg *reg, RAnalOp *op, const ut8 data) {
@ -295,9 +321,11 @@ static inline void gb_anal_and_bit (RReg *reg, RAnalOp *op, const ut8 data) {
op->src[0]->imm = 1<<((data>>3) & 7);
op->dst->memref = ((data & 7) == 6);
op->dst->reg = r_reg_get (reg, regs_x[data & 7], R_REG_TYPE_GPR);
if (op->dst->memref)
if (op->dst->memref) {
r_strbuf_setf (&op->esil, "%i,%s,[1],&,0,==,$z,Z,=,0,N,=,1,H,=", op->src[0]->imm, regs_x[data & 7]);
else r_strbuf_setf (&op->esil, "%i,%s,&,0,==,$z,Z,=,0,N,=,1,H,=", op->src[0]->imm, regs_x[data & 7]);
} else {
r_strbuf_setf (&op->esil, "%i,%s,&,0,==,$z,Z,=,0,N,=,1,H,=", op->src[0]->imm, regs_x[data & 7]);
}
}
static inline void gb_anal_or_set (RAnal *anal, RAnalOp *op, const ut8 data) {
@ -306,9 +334,11 @@ static inline void gb_anal_or_set (RAnal *anal, RAnalOp *op, const ut8 data) {
op->src[0]->imm = (data>>3) & 7;
op->dst->memref = ((data & 7) == 6);
op->dst->reg = r_reg_get (anal->reg, regs_x[data & 7], R_REG_TYPE_GPR);
if (op->dst->memref)
if (op->dst->memref) {
r_strbuf_setf (&op->esil, "0x%02x,%s,[1],|,%s,=[1]", op->src[0]->imm, regs_x[data & 7], regs_x[data & 7], op->src[0]->imm);
else r_strbuf_setf (&op->esil, "0x%02x,%s,|=", op->src[0]->imm, regs_x[data & 7]);
} else {
r_strbuf_setf (&op->esil, "0x%02x,%s,|=", op->src[0]->imm, regs_x[data & 7]);
}
}
static void gb_anal_xoaasc (RReg *reg, RAnalOp *op, const ut8 *data) {
@ -319,20 +349,26 @@ static void gb_anal_xoaasc (RReg *reg, RAnalOp *op, const ut8 *data) {
op->src[0]->memref = ((data[0] & 7) == 6);
switch (op->type) {
case R_ANAL_OP_TYPE_XOR:
if (op->src[0]->memref)
if (op->src[0]->memref) {
r_strbuf_setf (&op->esil, "%s,[1],a,^=,$z,Z,=,0,N,=,0,H,=,0,C,=", regs_x[data[0] & 7]);
else r_strbuf_setf (&op->esil, "%s,a,^=,$z,Z,=,0,N,=,0,H,=,0,C,=", regs_x[data[0] & 7]);
break;
} else {
r_strbuf_setf (&op->esil, "%s,a,^=,$z,Z,=,0,N,=,0,H,=,0,C,=", regs_x[data[0] & 7]);
}
break;
case R_ANAL_OP_TYPE_OR:
if (op->src[0]->memref)
if (op->src[0]->memref) {
r_strbuf_setf (&op->esil, "%s,[1],a,|=,$z,Z,=,0,N,=,0,H,=,0,C,=", regs_x[data[0] &7]);
else r_strbuf_setf (&op->esil, "%s,a,|=,$z,Z,=,0,N,=,0,H,=,0,C,=", regs_x[data[0] & 7]);
break;
} else {
r_strbuf_setf (&op->esil, "%s,a,|=,$z,Z,=,0,N,=,0,H,=,0,C,=", regs_x[data[0] & 7]);
}
break;
case R_ANAL_OP_TYPE_AND:
if (op->src[0]->memref)
if (op->src[0]->memref) {
r_strbuf_setf (&op->esil, "%s,[1],a,&=,$z,Z,=,0,N,=,1,H,=,0,C,=", regs_x[data[0] & 7]);
else r_strbuf_setf (&op->esil, "%s,a,&=,$z,Z,=,0,N,=,1,H,=,0,C,=", regs_x[data[0] & 7]);
break;
} else {
r_strbuf_setf (&op->esil, "%s,a,&=,$z,Z,=,0,N,=,1,H,=,0,C,=", regs_x[data[0] & 7]);
}
break;
case R_ANAL_OP_TYPE_ADD:
if (op->src[0]->memref) {
if (data[0] > 0x87) {
@ -372,10 +408,12 @@ static void gb_anal_xoaasc (RReg *reg, RAnalOp *op, const ut8 *data) {
}
break;
case R_ANAL_OP_TYPE_CMP:
if (op->src[0]->memref)
if (op->src[0]->memref) {
r_strbuf_setf (&op->esil, "%s,[1],a,==,$z,Z,=,$b4,H,=,$b8,C,=,1,N,=", regs_x[data[0] & 7]);
else r_strbuf_setf (&op->esil, "%s,a,==,$z,Z,=,$b4,H,=,$b8,C,=,1,N,=", regs_x[data[0] & 7]);
break;
} else {
r_strbuf_setf (&op->esil, "%s,a,==,$z,Z,=,$b4,H,=,$b8,C,=,1,N,=", regs_x[data[0] & 7]);
}
break;
}
}
@ -402,16 +440,20 @@ static void gb_anal_xoaasc_imm (RReg *reg, RAnalOp *op, const ut8 *data) //xor ,
op->src[1] = r_anal_value_new ();
op->src[1]->reg = r_reg_get (reg, "C", R_REG_TYPE_GPR);
r_strbuf_append (&op->esil, "a,+=,C,NUM,$c7,C,=,$c3,H,=,a,+=,$c7,C,|=,$c3,H,|=,a,a,=,$z,Z,=,0,N,=");
} else r_strbuf_append (&op->esil, "a,+=,$c3,H,=,$c7,C,=,0,N,=,a,a,=,$z,Z,=");
break;
} else {
r_strbuf_append (&op->esil, "a,+=,$c3,H,=,$c7,C,=,0,N,=,a,a,=,$z,Z,=");
}
break;
case R_ANAL_OP_TYPE_SUB:
r_strbuf_setf (&op->esil, "0x%02x,", data[1]);
if (data[0] == 0xde) { //sbc
op->src[1] = r_anal_value_new ();
op->src[1]->reg = r_reg_get (reg, "C", R_REG_TYPE_GPR);
r_strbuf_append (&op->esil, "a,-=,C,NUM,$b8,C,=,$b4,H,=,a,-=,$b8,C,|=,$b4,H,|=,a,a,=,$z,Z,=,1,N,=");
} else r_strbuf_append (&op->esil, "a,-=,$b4,H,=,$b8,C,=,1,N,=,a,a,=,$z,Z,=");
break;
} else {
r_strbuf_append (&op->esil, "a,-=,$b4,H,=,$b8,C,=,1,N,=,a,a,=,$z,Z,=");
}
break;
case R_ANAL_OP_TYPE_CMP:
r_strbuf_setf (&op->esil, "%d,a,==,$z,Z,=,$b4,H,=,$b8,C,=,1,N,=", data[1]);
break;
@ -481,10 +523,12 @@ static inline void gb_anal_store_hl (RReg *reg, RAnalOp *op, const ut8 *data) {
op->src[0]->reg = r_reg_get (reg, regs_8[data[0] & 0x07], R_REG_TYPE_GPR);
r_strbuf_setf (&op->esil, "%s,hl,=[1]", regs_8[data[0] & 0x07]);
}
if (data[0] == 0x32)
if (data[0] == 0x32) {
r_strbuf_set (&op->esil, "a,hl,=[1],1,hl,-=");
if (data[0] == 0x22)
}
if (data[0] == 0x22) {
r_strbuf_set (&op->esil, "a,hl,=[1],1,hl,+=");
}
}
static void gb_anal_store (RReg *reg, RAnalOp *op, const ut8 *data)
@ -528,7 +572,9 @@ static inline void gb_anal_cb_swap (RReg *reg, RAnalOp* op, const ut8 data)
if ((data & 7) == 6) {
op->dst->memref = 1;
r_strbuf_setf (&op->esil, "4,%s,[1],>>,4,%s,[1],<<,|,%s,=[1],$z,Z,=", regs_x[data & 7], regs_x[data & 7], regs_x[data & 7]);
} else r_strbuf_setf (&op->esil, "4,%s,>>,4,%s,<<,|,%s,=,$z,Z,=", regs_x[data & 7], regs_x[data & 7], regs_x[data & 7]);
} else {
r_strbuf_setf (&op->esil, "4,%s,>>,4,%s,<<,|,%s,=,$z,Z,=", regs_x[data & 7], regs_x[data & 7], regs_x[data & 7]);
}
}
static inline void gb_anal_cb_rlc (RReg *reg, RAnalOp *op, const ut8 data)
@ -540,7 +586,9 @@ static inline void gb_anal_cb_rlc (RReg *reg, RAnalOp *op, const ut8 data)
if ((data & 7) == 6) {
op->dst->memref = 1;
r_strbuf_setf (&op->esil, "7,%s,[1],>>,1,&,C,=,1,%s,[1],<<,C,|,%s,=[1],$z,Z,=,0,H,=,0,N,=", regs_x[data & 7], regs_x[data & 7], regs_x[data & 7]);
} else r_strbuf_setf (&op->esil, "1,%s,<<=,$c7,C,=,C,%s,|=,$z,Z,=,0,H,=,0,N,=", regs_x[data & 7], regs_x[data & 7]);
} else {
r_strbuf_setf (&op->esil, "1,%s,<<=,$c7,C,=,C,%s,|=,$z,Z,=,0,H,=,0,N,=", regs_x[data & 7], regs_x[data & 7]);
}
}
static inline void gb_anal_cb_rl (RReg *reg, RAnalOp *op, const ut8 data)
@ -552,7 +600,9 @@ static inline void gb_anal_cb_rl (RReg *reg, RAnalOp *op, const ut8 data)
if ((data & 7) == 6) {
op->dst->memref = 1;
r_strbuf_setf (&op->esil, "1,%s,<<,C,|,%s,=[1],$c7,C,=,$z,Z,=,0,H,=,0,N,=", regs_x[data & 7], regs_x[data & 7]);
} else r_strbuf_setf (&op->esil, "1,%s,<<,C,|,%s,=,$c7,C,=,$z,Z,=,0,H,=,0,N,=", regs_x[data & 7], regs_x[data & 7]);
} else {
r_strbuf_setf (&op->esil, "1,%s,<<,C,|,%s,=,$c7,C,=,$z,Z,=,0,H,=,0,N,=", regs_x[data & 7], regs_x[data & 7]);
}
}
static inline void gb_anal_cb_rrc (RReg *reg, RAnalOp *op, const ut8 data)
@ -564,7 +614,9 @@ static inline void gb_anal_cb_rrc (RReg *reg, RAnalOp *op, const ut8 data)
if ((data &7) == 6) {
op->dst->memref = 1;
r_strbuf_setf (&op->esil, "1,%s,[1],&,C,=,1,%s,[1],>>,7,C,<<,|,%s,=[1],$z,Z,=,0,H,=,0,N,=", regs_x[data & 7], regs_x[data & 7], regs_x[data & 7]);
} else r_strbuf_setf (&op->esil, "1,%s,&,C,=,1,%s,>>,7,C,<<,|,%s,=,$z,Z,=,0,H,=,0,N,=", regs_x[data & 7], regs_x[data & 7], regs_x[data & 7]);
} else {
r_strbuf_setf (&op->esil, "1,%s,&,C,=,1,%s,>>,7,C,<<,|,%s,=,$z,Z,=,0,H,=,0,N,=", regs_x[data & 7], regs_x[data & 7], regs_x[data & 7]);
}
}
static inline void gb_anal_cb_rr (RReg *reg, RAnalOp *op, const ut8 data)
@ -576,7 +628,9 @@ static inline void gb_anal_cb_rr (RReg *reg, RAnalOp *op, const ut8 data)
if ((data & 7) == 6) {
op->dst->memref = 1;
r_strbuf_setf (&op->esil, "1,%s,[1],&,H,=,1,%s,[1],>>,7,C,<<,|,%s,=[1],H,C,=,0,H,=,0,N,=", regs_x[data & 7], regs_x[data & 7], regs_x[data & 7]);
} else r_strbuf_setf (&op->esil, "1,%s,&,H,=,1,%s,>>,7,C,<<,|,%s,=,H,C,=,0,H,=,0,N,=", regs_x[data & 7], regs_x[data & 7], regs_x[data & 7]); //HACK
} else {
r_strbuf_setf (&op->esil, "1,%s,&,H,=,1,%s,>>,7,C,<<,|,%s,=,H,C,=,0,H,=,0,N,=", regs_x[data & 7], regs_x[data & 7], regs_x[data & 7]); //HACK
}
}
static inline void gb_anal_cb_sla (RReg *reg, RAnalOp *op, const ut8 data) //sra+sla+srl in one function, like xoaasc
@ -586,9 +640,11 @@ static inline void gb_anal_cb_sla (RReg *reg, RAnalOp *op, const ut8 data)
op->src[0]->imm = 1;
op->dst->reg = r_reg_get (reg, regs_x[data & 7], R_REG_TYPE_GPR);
op->dst->memref = ((data & 7) == 6);
if (op->dst->memref)
if (op->dst->memref) {
r_strbuf_setf (&op->esil, "1,%s,[1],<<,%s,=[1],$c7,C,=,%s,[1],%s,=[1],$z,Z,=,0,H,=,0,N,=", regs_x[data & 7], regs_x[data & 7], regs_x[data & 7], regs_x[data & 7]);
else r_strbuf_setf (&op->esil, "1,%s,<<=,$c7,C,=,%s,%s,=,$z,Z,=,0,H,=0,N,=", regs_x[data & 7], regs_x[data & 7], regs_x[data & 7]); // %s,%s,= is a HACK for $z
} else {
r_strbuf_setf (&op->esil, "1,%s,<<=,$c7,C,=,%s,%s,=,$z,Z,=,0,H,=0,N,=", regs_x[data & 7], regs_x[data & 7], regs_x[data & 7]); // %s,%s,= is a HACK for $z
}
}
static inline void gb_anal_cb_sra (RReg *reg, RAnalOp *op, const ut8 data) {
@ -597,9 +653,11 @@ static inline void gb_anal_cb_sra (RReg *reg, RAnalOp *op, const ut8 data) {
op->src[0]->imm = 1;
op->dst->reg = r_reg_get (reg, regs_x[data & 7], R_REG_TYPE_GPR);
op->dst->memref = ((data & 7) == 6);
if (op->dst->memref)
if (op->dst->memref) {
r_strbuf_setf (&op->esil, "1,%s,[1],&,C,=,0x80,%s,[1],&,1,%s,[1],>>,|,%s,=[1],$z,Z,=,0,N,=,0,H,=", regs_x[data & 7], regs_x[data & 7], regs_x[data & 7], regs_x[data & 7]); //spaguesil
else r_strbuf_setf (&op->esil, "1,%s,&,C,=,0x80,%s,&,1,%s,>>,|,%s,=,$z,Z,=,0,N,=,0,H,=", regs_x[data & 7], regs_x[data & 7], regs_x[data & 7], regs_x[data & 7]);
} else {
r_strbuf_setf (&op->esil, "1,%s,&,C,=,0x80,%s,&,1,%s,>>,|,%s,=,$z,Z,=,0,N,=,0,H,=", regs_x[data & 7], regs_x[data & 7], regs_x[data & 7], regs_x[data & 7]);
}
}
static inline void gb_anal_cb_srl (RReg *reg, RAnalOp *op, const ut8 data) {
@ -608,16 +666,19 @@ static inline void gb_anal_cb_srl (RReg *reg, RAnalOp *op, const ut8 data) {
op->src[0]->imm = 1;
op->dst->reg = r_reg_get (reg, regs_x[data & 7], R_REG_TYPE_GPR);
op->dst->memref = ((data & 7) == 6);
if (op->dst->memref)
if (op->dst->memref) {
r_strbuf_setf (&op->esil, "1,%s,[1],&,C,=,1,%s,[1],>>,%s,=[1],$z,Z,=,0,N,=,0,H,=", regs_x[data & 7], regs_x[data & 7], regs_x[data & 7]);
else r_strbuf_setf (&op->esil, "1,%s,&,C,=,1,%s,>>=,$z,Z,=,0,N,=,0,H,=", regs_x[data & 7], regs_x[data & 7]);
} else {
r_strbuf_setf (&op->esil, "1,%s,&,C,=,1,%s,>>=,$z,Z,=,0,N,=,0,H,=", regs_x[data & 7], regs_x[data & 7]);
}
}
static int gb_custom_daa (RAnalEsil *esil) {
ut8 a, H, C, Z;
ut64 n;
if (!esil || !esil->anal || !esil->anal->reg)
if (!esil || !esil->anal || !esil->anal->reg) {
return false;
}
r_anal_esil_reg_read (esil, "H", &n, NULL);
H = (ut8)n;
r_anal_esil_reg_read (esil, "C", &n, NULL);
@ -627,18 +688,22 @@ static int gb_custom_daa (RAnalEsil *esil) {
a = (ut8)n;
r_anal_esil_reg_read (esil, "N", &n, NULL);
if (n) {
if (C)
if (C) {
a = (a - 0x60) & 0xff;
else r_anal_esil_reg_write (esil, "C", 0LL);
if (H)
} else {
r_anal_esil_reg_write (esil, "C", 0LL);
}
if (H) {
a = (a - 0x06) & 0xff;
}
} else {
if (C || (a > 0x99)) {
a = (a + 0x60) & 0xff;
r_anal_esil_reg_write (esil, "C", 1LL);
}
if (H || ((a & 0x0f) > 0x09))
a += 0x06;;
if (H || ((a & 0x0f) > 0x09)) {
a += 0x06;
};
}
esil->cur = a;
Z = (a == 0);
@ -650,8 +715,9 @@ static int gb_custom_daa (RAnalEsil *esil) {
static int gb_anop(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int len){
int ilen = gbOpLength (gb_op[data[0]].type);
if (ilen > len)
ilen=0;
if (ilen > len) {
ilen = 0;
}
memset (op, '\0', sizeof (RAnalOp));
op->addr = addr;
op->type = R_ANAL_OP_TYPE_UNK;
@ -1152,13 +1218,16 @@ static int gb_anop(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int len
op->type = R_ANAL_OP_TYPE_CJMP;
op->eob = true; //halt migth wait for interrupts
op->fail = addr + ilen;
if(len > 1)
if (len > 1) {
op->jump = addr + gbOpLength (gb_op[data[1]].type) + ilen;
}
break;
case 0xcd:
if ( gb_op_calljump (anal, op, data, addr))
if (gb_op_calljump (anal, op, data, addr)) {
op->type = R_ANAL_OP_TYPE_CALL;
else op->type = R_ANAL_OP_TYPE_UCALL;
} else {
op->type = R_ANAL_OP_TYPE_UCALL;
}
op->fail = addr + ilen;
op->eob = true;
gb_anal_esil_call (op);
@ -1169,9 +1238,11 @@ static int gb_anop(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int len
case 0xd4:
case 0xdc:
gb_anal_cond (anal->reg, op, data[0]);
if( gb_op_calljump (anal, op, data, addr))
if (gb_op_calljump (anal, op, data, addr)) {
op->type = R_ANAL_OP_TYPE_CCALL;
else op->type = R_ANAL_OP_TYPE_UCCALL;
} else {
op->type = R_ANAL_OP_TYPE_UCCALL;
}
op->fail = addr + ilen;
op->eob = true;
gb_anal_esil_ccall (op, data[0]);
@ -1267,58 +1338,74 @@ static int gb_anop(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int len
switch (data[1]>>3)
{
case 0:
if ((data[1]&7) == 6)
if ((data[1] & 7) == 6) {
op->cycles = 16;
else op->cycles = 8;
} else {
op->cycles = 8;
}
op->type = R_ANAL_OP_TYPE_ROL;
gb_anal_cb_rlc (anal->reg, op, data[1]);
break;
case 1:
if ((data[1] & 7) == 6)
if ((data[1] & 7) == 6) {
op->cycles = 16;
else op->cycles = 8;
} else {
op->cycles = 8;
}
op->type = R_ANAL_OP_TYPE_ROR;
gb_anal_cb_rrc (anal->reg, op, data[1]);
break;
case 2:
if ((data[1]&7) == 6)
if ((data[1] & 7) == 6) {
op->cycles = 16;
else op->cycles = 8;
} else {
op->cycles = 8;
}
op->type = R_ANAL_OP_TYPE_ROL;
gb_anal_cb_rl (anal->reg, op, data[1]);
break;
case 3:
if ((data[1]&7) == 6)
if ((data[1] & 7) == 6) {
op->cycles = 16;
else op->cycles = 8;
} else {
op->cycles = 8;
}
op->type = R_ANAL_OP_TYPE_ROR;
gb_anal_cb_rr (anal->reg, op, data[1]);
break;
case 4:
if ((data [1] & 7) == 6)
if ((data[1] & 7) == 6) {
op->cycles = 16;
else op->cycles = 8;
} else {
op->cycles = 8;
}
op->type = R_ANAL_OP_TYPE_SAL;
gb_anal_cb_sla (anal->reg, op, data[1]);
break;
case 6:
if ((data[1] & 7) == 6)
if ((data[1] & 7) == 6) {
op->cycles = 16;
else op->cycles = 8;
} else {
op->cycles = 8;
}
op->type = R_ANAL_OP_TYPE_ROL;
gb_anal_cb_swap (anal->reg, op, data[1]);
break;
case 5:
if ((data [1] & 7) == 6)
if ((data[1] & 7) == 6) {
op->cycles = 16;
else op->cycles = 8;
} else {
op->cycles = 8;
}
op->type = R_ANAL_OP_TYPE_SAR;
gb_anal_cb_sra (anal->reg, op, data[1]);
break;
case 7:
if ((data [1] & 7) == 6)
if ((data[1] & 7) == 6) {
op->cycles = 16;
else op->cycles = 8;
} else {
op->cycles = 8;
}
op->type = R_ANAL_OP_TYPE_SHR;
gb_anal_cb_srl (anal->reg, op, data[1]);
break;
@ -1330,9 +1417,11 @@ static int gb_anop(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int len
case 13:
case 14:
case 15:
if ((data[1]&7) == 6)
if ((data[1] & 7) == 6) {
op->cycles = 12;
else op->cycles = 8;
} else {
op->cycles = 8;
}
op->type = R_ANAL_OP_TYPE_ACMP;
gb_anal_and_bit (anal->reg, op, data[1]);
break; //bit
@ -1344,9 +1433,11 @@ static int gb_anop(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int len
case 21:
case 22:
case 23:
if ((data[1]&7) == 6)
if ((data[1] & 7) == 6) {
op->cycles = 16;
else op->cycles = 8;
} else {
op->cycles = 8;
}
gb_anal_and_res (anal, op, data[1]);
op->type = R_ANAL_OP_TYPE_AND;
break; //res
@ -1358,9 +1449,11 @@ static int gb_anop(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int len
case 29:
case 30:
case 31:
if ((data[1]&7) == 6)
if ((data[1] & 7) == 6) {
op->cycles = 16;
else op->cycles = 8;
} else {
op->cycles = 8;
}
gb_anal_or_set (anal, op, data[1]);
op->type = R_ANAL_OP_TYPE_OR;
break; //set

52
libr/anal/p/anal_h8300.c
View File

@ -86,8 +86,9 @@ static void h8300_anal_jsr(RAnalOp *op, ut64 addr, const ut8 *buf) {
static int analop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf) {
int ret = -1;
ut8 opcode = buf[0];
if (!op)
if (!op) {
return 2;
}
r_strbuf_init (&op->esil);
r_strbuf_set (&op->esil, "");
switch (opcode >> 4) {
@ -450,10 +451,11 @@ static int analop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf) {
rsB(), rsB(), rdB(1));
return 0;
case H8300_BST_BIST: /*TODO*/
if(! (buf[1] & 0x80) ) //BST
if (!(buf[1] & 0x80)) { //BST
r_strbuf_appendf(&op->esil,"%d,C,<<,r%u%c,|=",rs(),rdB(1));
else //BIST
r_strbuf_appendf(&op->esil,"%d,C,!,<<,r%u%c,|=",rs(),rdB(1));
} else { //BIST
r_strbuf_appendf (&op->esil, "%d,C,!,<<,r%u%c,|=", rs (), rdB (1));
}
return 0;
case H8300_MOV_R82IND16: /*TODO*/ return 0;
case H8300_MOV_IND162R16: /*TODO*/ return 0;
@ -482,42 +484,46 @@ static int analop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf) {
rs(), rs(), rdB(1));
return 0;
case H8300_BOR_BIOR: /*TODO*/
if(! (buf[1] & 0x80) ) //BOR
if (!(buf[1] & 0x80)) { //BOR
//C|=(rd&(1<<imm))>>imm
r_strbuf_appendf(&op->esil, "%d,%d,1,<<,r%u%c,&,>>,C,|=",
rs(), rs(), rdB(1));
else //BIOR
} else { //BIOR
//C|=!(rd&(1<<imm))>>imm
r_strbuf_appendf(&op->esil, "%d,%d,1,<<,r%u%c,&,>>,!,C,|=",
rs(), rs(), rdB(1));
r_strbuf_appendf (&op->esil, "%d,%d,1,<<,r%u%c,&,>>,!,C,|=",
rs (), rs (), rdB (1));
}
return 0;
case H8300_BXOR_BIXOR: /*TODO*/
if(! (buf[1] & 0x80) ) //BXOR
if (!(buf[1] & 0x80)) { //BXOR
//C^=(rd&(1<<imm))>>imm
r_strbuf_appendf(&op->esil, "%d,%d,1,<<,r%u%c,&,>>,C,^=",
rs(), rs(), rdB(1));
else //BIXOR
r_strbuf_appendf(&op->esil, "%d,%d,1,<<,r%u%c,&,>>,!,C,^=",
rs(), rs(), rdB(1));
} else { //BIXOR
r_strbuf_appendf (&op->esil, "%d,%d,1,<<,r%u%c,&,>>,!,C,^=",
rs (), rs (), rdB (1));
}
return 0;
case H8300_BAND_BIAND:
/*TODO check functionality*/
//C&=(rd&(1<<imm))>>imm
if(! (buf[1] & 0x80) ) //BAND
if (!(buf[1] & 0x80)) { //BAND
r_strbuf_appendf(&op->esil, "%d,%d,1,<<,r%u%c,&,>>,C,&=",
rs(), rs(), rdB(1));
else //BIAND
r_strbuf_appendf(&op->esil, "%d,%d,1,<<,r%u%c,&,>>,!,C,&=",
rs(), rs(), rdB(1));
} else { //BIAND
r_strbuf_appendf (&op->esil, "%d,%d,1,<<,r%u%c,&,>>,!,C,&=",
rs (), rs (), rdB (1));
}
return 0;
case H8300_BILD_IMM2R8:
/*TODO*/
if(! (buf[1] & 0x80) ) //BLD
if (!(buf[1] & 0x80)) { //BLD
r_strbuf_appendf(&op->esil, "%d,%d,1,<<,r%u%c,&,>>,C,=",
rs(), rs(), rdB(1));
else //BILD
r_strbuf_appendf(&op->esil, "%d,%d,1,<<,r%u%c,&,>>,!,C,=",
rs(), rs(), rdB(1));
} else { //BILD
r_strbuf_appendf (&op->esil, "%d,%d,1,<<,r%u%c,&,>>,!,C,=",
rs (), rs (), rdB (1));
}
return 0;
case H8300_MOV_IMM162R16: /*TODO*/ return 0;
case H8300_EEPMOV: /*TODO*/ return 0;
@ -539,8 +545,9 @@ static int h8300_op(RAnal *anal, RAnalOp *op, ut64 addr,
ut8 opcode = buf[0];
struct h8300_cmd cmd;
if (!op)
if (!op) {
return 2;
}
memset(op, 0, sizeof (RAnalOp));
@ -549,8 +556,9 @@ static int h8300_op(RAnal *anal, RAnalOp *op, ut64 addr,
op->ptr = op->val = -1;
ret = op->size = h8300_decode_command(buf, &cmd);
if (ret < 0)
if (ret < 0) {
return ret;
}
switch (opcode >> 4) {
case H8300_MOV_4BIT_2:
case H8300_MOV_4BIT_3:

17
libr/anal/p/anal_i4004.c
View File

@ -91,8 +91,9 @@ static const char *i4004_f[16] = {
static int i4004_get_ins_len (ut8 hex) {
ut8 high = (hex & 0xf0)>>4;
int ret = i4004_ins_len[high];
if (ret == 3)
if (ret == 3) {
ret = (hex & 1) ? 1 : 2;
}
return ret;
}
@ -100,13 +101,17 @@ static int i4004_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf, int len
char basm[128];
const size_t basz = sizeof (basm)-1;
int rlen = i4004_get_ins_len (*buf);
if (!op) return 2;
if (!op) {
return 2;
}
r_strbuf_init (&op->esil);
ut8 high = (*buf & 0xf0)>>4;
ut8 low = (*buf & 0xf);
basm[0] = 0;
if (rlen > len) return op->size = 0;
if (rlen > len) {
return op->size = 0;
}
switch (high) {
case 0:
if (low) {
@ -121,9 +126,11 @@ static int i4004_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf, int len
op->fail = addr + rlen;
break;
case 2:
if (rlen == 1)
if (rlen == 1) {
snprintf (basm, basz, "scr r%d", (low & 0xe));
else snprintf (basm, basz, "fim r%d, 0x%02x", (low & 0xe), buf[1]);
} else {
snprintf (basm, basz, "fim r%d, 0x%02x", (low & 0xe), buf[1]);
}
break;
case 3:
op->type = R_ANAL_OP_TYPE_MOV;

57
libr/anal/p/anal_java.c
View File

@ -147,8 +147,9 @@ static int java_recursive_descent(RAnal *anal, RAnalState *state, ut64 addr) {
RAnalBlock *bb;
RAnalBlock *current_head;
if (!anal || !state || !state->current_bb || state->current_bb_head)
if (!anal || !state || !state->current_bb || state->current_bb_head) {
return 0;
}
bb = state->current_bb;
current_head = state->current_bb_head;
@ -171,7 +172,9 @@ static int java_recursive_descent(RAnal *anal, RAnalState *state, ut64 addr) {
// if (bb->type2 & R_ANAL_EX_OBJ_OP) handle_bb_obj_op (anal, state);
// if (bb->type2 & R_ANAL_EX_STACK_OP) handle_bb_stack_op (anal, state);
// if (bb->type2 & R_ANAL_EX_BIN_OP) handle_bb_bin_op (anal, state);
if (bb->type2 & R_ANAL_EX_CODE_OP) handle_bb_cf_recursive_descent (anal, state);
if (bb->type2 & R_ANAL_EX_CODE_OP) {
handle_bb_cf_recursive_descent (anal, state);
}
// if (bb->type2 & R_ANAL_EX_DATA_OP) handle_bb_data_op (anal, state);
return 0;
}
@ -196,7 +199,9 @@ static int java_linear_sweep(RAnal *anal, RAnalState *state, ut64 addr) {
// if (bb->type2 & R_ANAL_EX_OBJ_OP) handle_bb_obj_op (anal, state);
// if (bb->type2 & R_ANAL_EX_STACK_OP) handle_bb_stack_op (anal, state);
// if (bb->type2 & R_ANAL_EX_BIN_OP) handle_bb_bin_op (anal, state);
if (bb->type2 & R_ANAL_EX_CODE_OP) handle_bb_cf_linear_sweep (anal, state);
if (bb->type2 & R_ANAL_EX_CODE_OP) {
handle_bb_cf_linear_sweep (anal, state);
}
// if (bb->type2 & R_ANAL_EX_DATA_OP) handle_bb_data_op (anal, state);
return 0;
}
@ -234,14 +239,17 @@ static int handle_bb_cf_recursive_descent (RAnal *anal, RAnalState *state) {
// visited some other time
if (!r_anal_state_search_bb (state, bb->jump)) {
jmp_list = r_anal_ex_perform_analysis ( anal, state, bb->jump );
if (jmp_list)
bb->jumpbb = (RAnalBlock *) r_list_get_n (jmp_list, 0);
if (bb->jumpbb)
if (jmp_list) {
bb->jumpbb = (RAnalBlock *)r_list_get_n (jmp_list, 0);
}
if (bb->jumpbb) {
bb->jump = bb->jumpbb->addr;
}
} else {
bb->jumpbb = r_anal_state_search_bb (state, bb->jump);
if (bb->jumpbb)
if (bb->jumpbb) {
bb->jump = bb->jumpbb->addr;
}
}
if (state->done == 1) {
@ -259,8 +267,9 @@ static int handle_bb_cf_recursive_descent (RAnal *anal, RAnalState *state) {
// visited some other time
if (!r_anal_state_search_bb (state, bb->jump)) {
jmp_list = r_anal_ex_perform_analysis ( anal, state, bb->jump );
if (jmp_list)
bb->jumpbb = (RAnalBlock *) r_list_get_n (jmp_list, 0);
if (jmp_list) {
bb->jumpbb = (RAnalBlock *)r_list_get_n (jmp_list, 0);
}
if (bb->jumpbb) {
bb->jump = bb->jumpbb->addr;
}
@ -277,8 +286,9 @@ static int handle_bb_cf_recursive_descent (RAnal *anal, RAnalState *state) {
if (!r_anal_state_search_bb (state, bb->fail)) {
jmp_list = r_anal_ex_perform_analysis ( anal, state, bb->fail );
if (jmp_list)
bb->failbb = (RAnalBlock *) r_list_get_n (jmp_list, 0);
if (jmp_list) {
bb->failbb = (RAnalBlock *)r_list_get_n (jmp_list, 0);
}
if (bb->failbb) {
bb->fail = bb->failbb->addr;
}
@ -297,7 +307,9 @@ static int handle_bb_cf_recursive_descent (RAnal *anal, RAnalState *state) {
}
result = R_ANAL_RET_END;
if (encountered_stop) state->done = 1;
if (encountered_stop) {
state->done = 1;
}
}
break;
@ -313,8 +325,9 @@ static int handle_bb_cf_recursive_descent (RAnal *anal, RAnalState *state) {
if (caseop) {
if (r_anal_state_addr_is_valid (state, caseop->jump) ) {
jmp_list = r_anal_ex_perform_analysis ( anal, state, caseop->jump );
if (jmp_list)
caseop->jumpbb = (RAnalBlock *) r_list_get_n (jmp_list, 0);
if (jmp_list) {
caseop->jumpbb = (RAnalBlock *)r_list_get_n (jmp_list, 0);
}
if (state->done == 1) {
IFDBG eprintf (" Looks like this jmp (bb @ 0x%04"PFMT64x") found a return.\n", addr);
state->done = 0;
@ -324,7 +337,9 @@ static int handle_bb_cf_recursive_descent (RAnal *anal, RAnalState *state) {
}
}
r_list_free (jmp_list);
if (encountered_stop) state->done = 1;
if (encountered_stop) {
state->done = 1;
}
}
result = R_ANAL_RET_END;
@ -587,7 +602,9 @@ static int java_analyze_fns_from_buffer( RAnal *anal, ut64 start, ut64 end, int
//analyze_all = 1;
buf_len = anal->iob.desc_size (anal->iob.io->desc);
if (buf_len == UT64_MAX) buf_len = 1024;
if (buf_len == UT64_MAX) {
buf_len = 1024;
}
end = start + buf_len;
}
@ -614,7 +631,9 @@ static int java_analyze_fns_from_buffer( RAnal *anal, ut64 start, ut64 end, int
r_anal_fcn_tree_insert (&anal->fcn_tree, fcn);
r_list_append (anal->fcns, fcn);
offset += r_anal_fcn_size (fcn);
if (!analyze_all) break;
if (!analyze_all) {
break;
}
}
free (buffer);
return result;
@ -867,7 +886,9 @@ static void java_update_anal_types (RAnal *anal, RBinJavaObj *bin_obj) {
if (the_list) {
r_list_foreach (the_list, iter, str) {
IFDBG eprintf ("Adding type: %s to known types.\n", str);
if (str) sdb_set (D, str, "type", 0);
if (str) {
sdb_set (D, str, "type", 0);
}
}
}
r_list_free (the_list);

22
libr/anal/p/anal_m68k_cs.c
View File

@ -145,22 +145,30 @@ static int analop(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len) {
// XXX no arch->cpu ?!?! CS_MODE_MICRO, N64
op->delay = 0;
// replace this with the asm.features?
if (a->cpu && strstr (a->cpu, "68000"))
if (a->cpu && strstr (a->cpu, "68000")) {
mode |= CS_MODE_M68K_000;
if (a->cpu && strstr (a->cpu, "68010"))
}
if (a->cpu && strstr (a->cpu, "68010")) {
mode |= CS_MODE_M68K_010;
if (a->cpu && strstr (a->cpu, "68020"))
}
if (a->cpu && strstr (a->cpu, "68020")) {
mode |= CS_MODE_M68K_020;
if (a->cpu && strstr (a->cpu, "68030"))
}
if (a->cpu && strstr (a->cpu, "68030")) {
mode |= CS_MODE_M68K_030;
if (a->cpu && strstr (a->cpu, "68040"))
}
if (a->cpu && strstr (a->cpu, "68040")) {
mode |= CS_MODE_M68K_040;
if (a->cpu && strstr (a->cpu, "68060"))
}
if (a->cpu && strstr (a->cpu, "68060")) {
mode |= CS_MODE_M68K_060;
}
op->size = 4;
if (handle == 0) {
ret = cs_open (CS_ARCH_M68K, mode, &handle);
if (ret != CS_ERR_OK) goto fin;
if (ret != CS_ERR_OK) {
goto fin;
}
cs_option (handle, CS_OPT_DETAIL, CS_OPT_ON);
}
n = cs_disasm (handle, (ut8*)buf, len, addr, 1, &insn);

411
libr/anal/p/anal_mips_cs.c
View File

@ -190,209 +190,208 @@ static int analop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len
}
}
if (insn)
switch (insn->id) {
case MIPS_INS_NOP:
r_strbuf_setf (&op->esil, ",");
break;
case MIPS_INS_BREAK:
r_strbuf_setf (&op->esil, "%d,%d,TRAP", IMM (0), IMM (0));
break;
case MIPS_INS_SD:
r_strbuf_appendf (&op->esil, "%s,%s,=[8]",
ARG (0), ARG (1));
break;
case MIPS_INS_SW:
case MIPS_INS_SWL:
case MIPS_INS_SWR:
r_strbuf_appendf (&op->esil, "%s,%s,=[4]",
ARG (0), ARG (1));
break;
case MIPS_INS_SH:
r_strbuf_appendf (&op->esil, "%s,%s,=[2]",
ARG (0), ARG (1));
break;
case MIPS_INS_SWC1:
case MIPS_INS_SWC2:
r_strbuf_setf (&op->esil, "%s,$", ARG (1));
break;
case MIPS_INS_SB:
r_strbuf_appendf (&op->esil, "%s,%s,=[1]",
ARG (0), ARG (1));
break;
case MIPS_INS_CMP:
case MIPS_INS_CMPU:
case MIPS_INS_CMPGU:
case MIPS_INS_CMPGDU:
case MIPS_INS_CMPI:
r_strbuf_appendf (&op->esil, "%s,%s,==", ARG (1), ARG (0));
break;
case MIPS_INS_SHRAV:
case MIPS_INS_SHRAV_R:
case MIPS_INS_SHRA:
case MIPS_INS_SHRA_R:
case MIPS_INS_SRA:
r_strbuf_appendf (&op->esil, "%s,%s,>>,31,%s,>>,?{,32,%s,-,%s,1,<<,1,-,<<,}{,0,},|,%s,=,",
ARG (2), ARG (1), ARG (1), ARG (2), ARG (2), ARG (0));
break;
case MIPS_INS_SHRL:
// suffix 'S' forces conditional flag to be updated
case MIPS_INS_SRLV:
case MIPS_INS_SRL:
r_strbuf_appendf (&op->esil, "%s,%s,>>,%s,=", ARG (2), ARG (1), ARG (0));
break;
case MIPS_INS_SLLV:
case MIPS_INS_SLL:
r_strbuf_appendf (&op->esil, "%s,%s,<<,%s,=", ARG (2), ARG (1), ARG (0));
break;
case MIPS_INS_BAL:
case MIPS_INS_JAL:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "" ES_CALL_D ("%s"), ARG (0));
break;
case MIPS_INS_JALR:
case MIPS_INS_JALRS:
if (OPCOUNT () < 2) {
if (insn) {
switch (insn->id) {
case MIPS_INS_NOP:
r_strbuf_setf (&op->esil, ",");
break;
case MIPS_INS_BREAK:
r_strbuf_setf (&op->esil, "%d,%d,TRAP", IMM (0), IMM (0));
break;
case MIPS_INS_SD:
r_strbuf_appendf (&op->esil, "%s,%s,=[8]",
ARG (0), ARG (1));
break;
case MIPS_INS_SW:
case MIPS_INS_SWL:
case MIPS_INS_SWR:
r_strbuf_appendf (&op->esil, "%s,%s,=[4]",
ARG (0), ARG (1));
break;
case MIPS_INS_SH:
r_strbuf_appendf (&op->esil, "%s,%s,=[2]",
ARG (0), ARG (1));
break;
case MIPS_INS_SWC1:
case MIPS_INS_SWC2:
r_strbuf_setf (&op->esil, "%s,$", ARG (1));
break;
case MIPS_INS_SB:
r_strbuf_appendf (&op->esil, "%s,%s,=[1]",
ARG (0), ARG (1));
break;
case MIPS_INS_CMP:
case MIPS_INS_CMPU:
case MIPS_INS_CMPGU:
case MIPS_INS_CMPGDU:
case MIPS_INS_CMPI:
r_strbuf_appendf (&op->esil, "%s,%s,==", ARG (1), ARG (0));
break;
case MIPS_INS_SHRAV:
case MIPS_INS_SHRAV_R:
case MIPS_INS_SHRA:
case MIPS_INS_SHRA_R:
case MIPS_INS_SRA:
r_strbuf_appendf (&op->esil, "%s,%s,>>,31,%s,>>,?{,32,%s,-,%s,1,<<,1,-,<<,}{,0,},|,%s,=,",
ARG (2), ARG (1), ARG (1), ARG (2), ARG (2), ARG (0));
break;
case MIPS_INS_SHRL:
// suffix 'S' forces conditional flag to be updated
case MIPS_INS_SRLV:
case MIPS_INS_SRL:
r_strbuf_appendf (&op->esil, "%s,%s,>>,%s,=", ARG (2), ARG (1), ARG (0));
break;
case MIPS_INS_SLLV:
case MIPS_INS_SLL:
r_strbuf_appendf (&op->esil, "%s,%s,<<,%s,=", ARG (2), ARG (1), ARG (0));
break;
case MIPS_INS_BAL:
case MIPS_INS_JAL:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "" ES_CALL_D ("%s"), ARG (0));
} else {
PROTECT_ZERO () {
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "" ES_CALL_DR ("%s","%s"), ARG (0), ARG (1));
break;
case MIPS_INS_JALR:
case MIPS_INS_JALRS:
if (OPCOUNT () < 2) {
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "" ES_CALL_D ("%s"), ARG (0));
} else {
PROTECT_ZERO () {
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "" ES_CALL_DR ("%s", "%s"), ARG (0), ARG (1));
}
}
}
break;
case MIPS_INS_JALRC: // no delay
if (OPCOUNT () < 2) {
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "" ES_CALL_ND ("%s"), ARG (0));
} else {
PROTECT_ZERO () {
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "" ES_CALL_NDR ("%s","%s"), ARG (0), ARG (1));
break;
case MIPS_INS_JALRC: // no delay
if (OPCOUNT () < 2) {
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "" ES_CALL_ND ("%s"), ARG (0));
} else {
PROTECT_ZERO () {
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "" ES_CALL_NDR ("%s", "%s"), ARG (0), ARG (1));
}
}
}
break;
case MIPS_INS_JRADDIUSP:
// increment stackpointer in X and jump to %ra
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "%d,sp,+=,"ES_J ("ra"), ARG (0));
break;
case MIPS_INS_JR:
case MIPS_INS_JRC:
case MIPS_INS_J:
case MIPS_INS_B: // ???
// jump to address with conditional
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "" ES_J ("%s"), ARG (0));
break;
case MIPS_INS_BNE: // bne $s, $t, offset
case MIPS_INS_BNEL:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "%s,%s,==,$z,!,?{,"ES_J ("%s")",}",
ARG (0), ARG (1), ARG (2));
break;
case MIPS_INS_BEQ:
case MIPS_INS_BEQL:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "%s,%s,==,$z,?{,"ES_J ("%s")",}",
ARG (0), ARG (1), ARG (2));
break;
case MIPS_INS_BZ:
case MIPS_INS_BEQZ:
case MIPS_INS_BEQZC:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "%s,0,==,$z,?{,"ES_J ("%s")",}",
ARG (0), ARG (1));
break;
case MIPS_INS_BNEZ:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "%s,0,==,$z,!,?{,"ES_J ("%s")",}",
ARG (0), ARG (1));
break;
case MIPS_INS_BEQZALC:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "%s,0,==,$z,?{,"ES_CALL_ND ("%s")",}",
ARG (0), ARG (1));
break;
case MIPS_INS_BLEZ:
case MIPS_INS_BLEZC:
case MIPS_INS_BLEZL:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "0,%s,==,$z,?{,"ES_J ("%s")",BREAK,},",
ARG (0), ARG (1));
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "1,"ES_IS_NEGATIVE ("%s")",==,$z,?{,"ES_J ("%s")",}",
ARG (0), ARG (1));
break;
case MIPS_INS_BGEZ:
case MIPS_INS_BGEZC:
case MIPS_INS_BGEZL:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "0,"ES_IS_NEGATIVE ("%s")",==,$z,?{,"ES_J ("%s")",}",
ARG (0), ARG (1));
break;
case MIPS_INS_BGEZAL:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "0,"ES_IS_NEGATIVE ("%s")",==,$z,?{,"ES_CALL_D ("%s")",}",
ARG (0), ARG (1));
break;
case MIPS_INS_BGEZALC:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "0,"ES_IS_NEGATIVE ("%s")",==,$z,?{,"ES_CALL_ND ("%s")",}",
ARG (0), ARG (1));
break;
case MIPS_INS_BGTZALC:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "0,%s,==,$z,?{,BREAK,},", ARG(0));
r_strbuf_appendf (&op->esil, "0,"ES_IS_NEGATIVE ("%s")",==,$z,?{,"ES_CALL_ND ("%s")",}",
ARG (0), ARG (1));
break;
case MIPS_INS_BLTZAL:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "1,"ES_IS_NEGATIVE ("%s")",==,$z,?{,"ES_CALL_D ("%s")",}", ARG(0), ARG(1));
break;
case MIPS_INS_BLTZ:
case MIPS_INS_BLTZC:
case MIPS_INS_BLTZL:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "1,"ES_IS_NEGATIVE ("%s")",==,$z,?{,"ES_J ("%s")",}",
ARG (0), ARG (1));
break;
case MIPS_INS_BGTZ:
case MIPS_INS_BGTZC:
case MIPS_INS_BGTZL:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "0,%s,==,$z,?{,BREAK,},", ARG (0));
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "0,"ES_IS_NEGATIVE ("%s")",==,$z,?{,"ES_J("%s")",}",
ARG (0), ARG (1));
break;
case MIPS_INS_BTEQZ:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "0,t,==,$z,?{,"ES_J ("%s")",}", ARG (0));
break;
case MIPS_INS_BTNEZ:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "0,t,==,$z,!,?{,"ES_J ("%s")",}", ARG (0));
break;
case MIPS_INS_MOV:
case MIPS_INS_MOVE:
PROTECT_ZERO () {
r_strbuf_appendf (&op->esil, "%s,%s,=", ARG (1), REG (0));
}
break;
case MIPS_INS_MOVZ:
case MIPS_INS_MOVF:
PROTECT_ZERO () {
r_strbuf_appendf (&op->esil, "0,%s,==,$z,?{,%s,%s,=,}",
ARG (2), ARG (1), REG (0));
}
break;
case MIPS_INS_MOVT:
PROTECT_ZERO () {
r_strbuf_appendf (&op->esil, "1,%s,==,$z,?{,%s,%s,=,}",
ARG (2), ARG (1), REG (0));
}
break;
case MIPS_INS_FSUB:
case MIPS_INS_SUB:
case MIPS_INS_SUBU:
case MIPS_INS_DSUB:
case MIPS_INS_DSUBU:
PROTECT_ZERO () {
r_strbuf_appendf(&op->esil, "%s,%s,-,%s,=",
ARG (2), ARG (1), ARG (0));
}
break;
case MIPS_INS_NEG:
case MIPS_INS_NEGU:
r_strbuf_appendf (&op->esil, "%s,0,-,%s,=,",
ARG (1), ARG (0));
break;
break;
case MIPS_INS_JRADDIUSP:
// increment stackpointer in X and jump to %ra
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "%d,sp,+=," ES_J ("ra"), ARG (0));
break;
case MIPS_INS_JR:
case MIPS_INS_JRC:
case MIPS_INS_J:
case MIPS_INS_B: // ???
// jump to address with conditional
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "" ES_J ("%s"), ARG (0));
break;
case MIPS_INS_BNE: // bne $s, $t, offset
case MIPS_INS_BNEL:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "%s,%s,==,$z,!,?{," ES_J ("%s") ",}",
ARG (0), ARG (1), ARG (2));
break;
case MIPS_INS_BEQ:
case MIPS_INS_BEQL:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "%s,%s,==,$z,?{," ES_J ("%s") ",}",
ARG (0), ARG (1), ARG (2));
break;
case MIPS_INS_BZ:
case MIPS_INS_BEQZ:
case MIPS_INS_BEQZC:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "%s,0,==,$z,?{," ES_J ("%s") ",}",
ARG (0), ARG (1));
break;
case MIPS_INS_BNEZ:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "%s,0,==,$z,!,?{," ES_J ("%s") ",}",
ARG (0), ARG (1));
break;
case MIPS_INS_BEQZALC:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "%s,0,==,$z,?{," ES_CALL_ND ("%s") ",}",
ARG (0), ARG (1));
break;
case MIPS_INS_BLEZ:
case MIPS_INS_BLEZC:
case MIPS_INS_BLEZL:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "0,%s,==,$z,?{," ES_J ("%s") ",BREAK,},",
ARG (0), ARG (1));
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "1," ES_IS_NEGATIVE ("%s") ",==,$z,?{," ES_J ("%s") ",}",
ARG (0), ARG (1));
break;
case MIPS_INS_BGEZ:
case MIPS_INS_BGEZC:
case MIPS_INS_BGEZL:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "0," ES_IS_NEGATIVE ("%s") ",==,$z,?{," ES_J ("%s") ",}",
ARG (0), ARG (1));
break;
case MIPS_INS_BGEZAL:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "0," ES_IS_NEGATIVE ("%s") ",==,$z,?{," ES_CALL_D ("%s") ",}",
ARG (0), ARG (1));
break;
case MIPS_INS_BGEZALC:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "0," ES_IS_NEGATIVE ("%s") ",==,$z,?{," ES_CALL_ND ("%s") ",}",
ARG (0), ARG (1));
break;
case MIPS_INS_BGTZALC:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "0,%s,==,$z,?{,BREAK,},", ARG (0));
r_strbuf_appendf (&op->esil, "0," ES_IS_NEGATIVE ("%s") ",==,$z,?{," ES_CALL_ND ("%s") ",}",
ARG (0), ARG (1));
break;
case MIPS_INS_BLTZAL:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "1," ES_IS_NEGATIVE ("%s") ",==,$z,?{," ES_CALL_D ("%s") ",}", ARG (0), ARG (1));
break;
case MIPS_INS_BLTZ:
case MIPS_INS_BLTZC:
case MIPS_INS_BLTZL:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "1," ES_IS_NEGATIVE ("%s") ",==,$z,?{," ES_J ("%s") ",}",
ARG (0), ARG (1));
break;
case MIPS_INS_BGTZ:
case MIPS_INS_BGTZC:
case MIPS_INS_BGTZL:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "0,%s,==,$z,?{,BREAK,},", ARG (0));
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "0," ES_IS_NEGATIVE ("%s") ",==,$z,?{," ES_J ("%s") ",}",
ARG (0), ARG (1));
break;
case MIPS_INS_BTEQZ:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "0,t,==,$z,?{," ES_J ("%s") ",}", ARG (0));
break;
case MIPS_INS_BTNEZ:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () "0,t,==,$z,!,?{," ES_J ("%s") ",}", ARG (0));
break;
case MIPS_INS_MOV:
case MIPS_INS_MOVE:
PROTECT_ZERO () {
r_strbuf_appendf (&op->esil, "%s,%s,=", ARG (1), REG (0));
}
break;
case MIPS_INS_MOVZ:
case MIPS_INS_MOVF:
PROTECT_ZERO () {
r_strbuf_appendf (&op->esil, "0,%s,==,$z,?{,%s,%s,=,}",
ARG (2), ARG (1), REG (0));
}
break;
case MIPS_INS_MOVT:
PROTECT_ZERO () {
r_strbuf_appendf (&op->esil, "1,%s,==,$z,?{,%s,%s,=,}",
ARG (2), ARG (1), REG (0));
}
break;
case MIPS_INS_FSUB:
case MIPS_INS_SUB:
case MIPS_INS_SUBU:
case MIPS_INS_DSUB:
case MIPS_INS_DSUBU:
PROTECT_ZERO () {
r_strbuf_appendf (&op->esil, "%s,%s,-,%s,=",
ARG (2), ARG (1), ARG (0));
}
break;
case MIPS_INS_NEG:
case MIPS_INS_NEGU:
r_strbuf_appendf (&op->esil, "%s,0,-,%s,=,",
ARG (1), ARG (0));
break;
/** signed -- sets overflow flag */
case MIPS_INS_ADD:
{
PROTECT_ZERO () {
r_strbuf_appendf(&op->esil, "%s,%s,+,%s,=",
ARG (1), ARG (2), ARG (0));
/** signed -- sets overflow flag */
case MIPS_INS_ADD: {
PROTECT_ZERO () {
r_strbuf_appendf (&op->esil, "%s,%s,+,%s,=",
ARG (1), ARG (2), ARG (0));
#if 0
r_strbuf_appendf (&op->esil,
"0,32,%s,%s,+,>>,>,?{,1,TRAP,}{,%s,%s,+,%s,=,}",
@ -584,6 +583,7 @@ static int analop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len
default:
return -1;
}
}
return 0;
}
@ -701,17 +701,21 @@ static int analop(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf, int len)
// XXX no arch->cpu ?!?! CS_MODE_MICRO, N64
op->delay = 0;
op->type = R_ANAL_OP_TYPE_ILL;
if (len<4)
if (len < 4) {
return -1;
}
op->size = 4;
if (hndl == 0) {
ret = cs_open (CS_ARCH_MIPS, mode, &hndl);
if (ret != CS_ERR_OK) goto fin;
if (ret != CS_ERR_OK) {
goto fin;
}
cs_option (hndl, CS_OPT_DETAIL, CS_OPT_ON);
}
n = cs_disasm (hndl, (ut8*)buf, len, addr, 1, &insn);
if (n<1 || insn->size<1)
if (n < 1 || insn->size < 1) {
goto beach;
}
op->type = R_ANAL_OP_TYPE_NULL;
op->delay = 0;
op->jump = UT64_MAX;
@ -997,8 +1001,9 @@ static int analop(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf, int len)
beach:
set_opdir (op);
if (anal->decode) {
if (analop_esil (anal, op, addr, buf, len, &hndl, insn) != 0)
if (analop_esil (anal, op, addr, buf, len, &hndl, insn) != 0) {
r_strbuf_fini (&op->esil);
}
}
if (anal->fillval) {
op_fillval (anal, op, &hndl, insn);

10
libr/anal/p/anal_mips_gnu.c
View File

@ -15,7 +15,9 @@ static const char* mips_reg_decode(unsigned reg_num) {
"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
"t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra"
};
if (reg_num < 32) return REGISTERS[reg_num];
if (reg_num < 32) {
return REGISTERS[reg_num];
}
return NULL;
}
@ -24,8 +26,9 @@ static int mips_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *b, int len) {
// WIP char buf[10]; int reg; int family;
int optype, oplen = (anal->bits==16)?2:4;
if (!op)
if (!op) {
return oplen;
}
memset (op, 0, sizeof (RAnalOp));
op->type = R_ANAL_OP_TYPE_UNK;
@ -242,8 +245,9 @@ static int mips_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *b, int len) {
int rs = ((b[0]&3)<<3)+(b[1]>>5);
int rt = b[1]&31;
int imm = (b[2]<<8)+b[3];
if (((optype >> 2) ^ 0x3) && (imm & 0x8000))
if (((optype >> 2) ^ 0x3) && (imm & 0x8000)) {
imm = 0 - (0x10000 - imm);
}
switch (optype) {
case 1: // if (rt) { /* bgez */ } else { /* bltz */ }
case 4: // beq

97
libr/anal/p/anal_nios2.c
View File

@ -7,8 +7,9 @@
#include <r_anal.h>
static int nios2_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *b, int len) {
if (!op)
if (!op) {
return 1;
}
/* Ayeeee! What's inside op? Do we have an initialized RAnalOp? Are we going to have a leak here? :-( */
memset (op, 0, sizeof (RAnalOp)); /* We need to refactorize this. Something like r_anal_op_init would be more appropiate */
r_strbuf_init (&op->esil);
@ -36,54 +37,54 @@ static int nios2_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *b, int len)
// blt, r19, r5, 0x8023480
op->type = R_ANAL_OP_TYPE_LOAD;
// TODO: address
} else
switch (b[0]) {
case 0x3a:
if (b[1]>=0xa0 && b[1]<=0xaf && b[3]==0x3d) {
op->type = R_ANAL_OP_TYPE_TRAP;
} else
if ((b[1]>=0xe0&&b[1]<=0xe7) && b[2]==0x3e && !b[3]) {
// nextpc ra
op->type = R_ANAL_OP_TYPE_RET;
} else {
switch (b[0]) {
case 0x3a:
if (b[1] >= 0xa0 && b[1] <= 0xaf && b[3] == 0x3d) {
op->type = R_ANAL_OP_TYPE_TRAP;
} else if ((b[1] >= 0xe0 && b[1] <= 0xe7) && b[2] == 0x3e && !b[3]) {
// nextpc ra
op->type = R_ANAL_OP_TYPE_RET;
}
break;
case 0x01:
// jmpi
op->type = R_ANAL_OP_TYPE_JMP;
break;
case 0x00:
case 0x20:
case 0x40:
case 0x80:
case 0xc0:
//
op->type = R_ANAL_OP_TYPE_CALL;
break;
case 0x26:
// beq
break;
case 0x07:
case 0x47:
case 0x87:
case 0xc7:
// ldb
op->type = R_ANAL_OP_TYPE_LOAD;
break;
case 0x0d:
case 0x2d:
case 0x4d:
case 0x8d:
case 0xcd:
// sth && sthio
op->type = R_ANAL_OP_TYPE_LOAD;
break;
case 0x06:
case 0x46:
case 0x86:
case 0xc6:
// br
op->type = R_ANAL_OP_TYPE_CALL;
break;
}
break;
case 0x01:
// jmpi
op->type = R_ANAL_OP_TYPE_JMP;
break;
case 0x00:
case 0x20:
case 0x40:
case 0x80:
case 0xc0:
//
op->type = R_ANAL_OP_TYPE_CALL;
break;
case 0x26:
// beq
break;
case 0x07:
case 0x47:
case 0x87:
case 0xc7:
// ldb
op->type = R_ANAL_OP_TYPE_LOAD;
break;
case 0x0d:
case 0x2d:
case 0x4d:
case 0x8d:
case 0xcd:
// sth && sthio
op->type = R_ANAL_OP_TYPE_LOAD;
break;
case 0x06:
case 0x46:
case 0x86:
case 0xc6:
// br
op->type = R_ANAL_OP_TYPE_CALL;
break;
}
return op->size;
}

24
libr/anal/p/anal_pic.c
View File

@ -738,10 +738,12 @@ static int anal_pic_pic18_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf
ut16 b = *(ut16 *)buf;
switch (b >> 9) {
case 0x76: //call
if (len < 4)
if (len < 4) {
goto beach;
if (*(ut32 *)buf >> 28 != 0xf)
}
if (*(ut32 *)buf >> 28 != 0xf) {
goto beach;
}
op->size = 4;
op->type = R_ANAL_OP_TYPE_CALL;
return op->size;
@ -764,10 +766,12 @@ static int anal_pic_pic18_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf
r_strbuf_setf (&op->esil, ",");
return op->size;
case 0xc: //movff
if (len < 4)
if (len < 4) {
goto beach;
if (*(ut32 *)buf >> 28 != 0xf)
}
if (*(ut32 *)buf >> 28 != 0xf) {
goto beach;
}
op->size = 4;
op->type = R_ANAL_OP_TYPE_MOV;
return op->size;
@ -808,10 +812,12 @@ static int anal_pic_pic18_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf
pic18_cond_branch (op, addr, buf, "c");
return op->size;
case 0xef: //goto
if (len < 4)
if (len < 4) {
goto beach;
if (*(ut32 *)buf >> 28 != 0xf)
}
if (*(ut32 *)buf >> 28 != 0xf) {
goto beach;
}
op->size = 4;
op->cycles = 2;
ut32 dword_instr = *(ut32 *)buf;
@ -865,10 +871,12 @@ static int anal_pic_pic18_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf
switch (b >> 6) { //LFSR
case 0x3b8: //lfsr
if (len < 4)
if (len < 4) {
goto beach;
if (*(ut32 *)buf >> 28 != 0xf)
}
if (*(ut32 *)buf >> 28 != 0xf) {
goto beach;
}
op->size = 4;
op->type = R_ANAL_OP_TYPE_LOAD;
return op->size;

37
libr/anal/p/anal_ppc_cs.c
View File

@ -43,8 +43,12 @@ static const char* cmask64(const char *mb_c, const char *me_c) {
static char cmask[32];
ut64 mb = 0;
ut64 me = 0;
if (mb_c) mb = strtol (mb_c, NULL, 16);
if (me_c) me = strtol (me_c, NULL, 16);
if (mb_c) {
mb = strtol (mb_c, NULL, 16);
}
if (me_c) {
me = strtol (me_c, NULL, 16);
}
snprintf (cmask, sizeof (cmask), "0x%"PFMT64x"", mask64 (mb, me));
return cmask;
}
@ -53,8 +57,12 @@ static const char* cmask32(const char *mb_c, const char *me_c) {
static char cmask[32];
ut32 mb = 0;
ut32 me = 0;
if (mb_c) mb = strtol (mb_c, NULL, 16);
if (me_c) me = strtol (me_c, NULL, 16);
if (mb_c) {
mb = strtol (mb_c, NULL, 16);
}
if (me_c) {
me = strtol (me_c, NULL, 16);
}
snprintf (cmask, sizeof (cmask), "0x%"PFMT32x"", mask32 (mb, me));
return cmask;
}
@ -595,8 +603,11 @@ static int analop(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len) {
case PPC_INS_CMPWI:
op->type = R_ANAL_OP_TYPE_CMP;
op->sign = true;
if (ARG (2)[0] == '\0') esilprintf (op, "%s,%s,-,0xff,&,cr0,=", ARG (1), ARG (0));
else esilprintf (op, "%s,%s,-,0xff,&,%s,=", ARG (2), ARG (1), ARG (0));
if (ARG (2)[0] == '\0') {
esilprintf (op, "%s,%s,-,0xff,&,cr0,=", ARG (1), ARG (0));
} else {
esilprintf (op, "%s,%s,-,0xff,&,%s,=", ARG (2), ARG (1), ARG (0));
}
break;
case PPC_INS_MFLR:
op->type = R_ANAL_OP_TYPE_MOV;
@ -630,13 +641,19 @@ static int analop(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len) {
case PPC_INS_EXTSB:
op->sign = true;
op->type = R_ANAL_OP_TYPE_MOV;
if (a->bits == 64) esilprintf (op, "%s,0x80,&,?{,0xFFFFFFFFFFFFFF00,%s,|,%s,=,}", ARG (1), ARG (1), ARG (0));
else esilprintf (op, "%s,0x80,&,?{,0xFFFFFF00,%s,|,%s,=,}", ARG (1), ARG (1), ARG (0));
if (a->bits == 64) {
esilprintf (op, "%s,0x80,&,?{,0xFFFFFFFFFFFFFF00,%s,|,%s,=,}", ARG (1), ARG (1), ARG (0));
} else {
esilprintf (op, "%s,0x80,&,?{,0xFFFFFF00,%s,|,%s,=,}", ARG (1), ARG (1), ARG (0));
}
break;
case PPC_INS_EXTSH:
op->sign = true;
if (a->bits == 64) esilprintf (op, "%s,0x8000,&,?{,0xFFFFFFFFFFFF0000,%s,|,%s,=,}", ARG (1), ARG (1), ARG (0));
else esilprintf (op, "%s,0x8000,&,?{,0xFFFF0000,%s,|,%s,=,}", ARG (1), ARG (1), ARG (0));
if (a->bits == 64) {
esilprintf (op, "%s,0x8000,&,?{,0xFFFFFFFFFFFF0000,%s,|,%s,=,}", ARG (1), ARG (1), ARG (0));
} else {
esilprintf (op, "%s,0x8000,&,?{,0xFFFF0000,%s,|,%s,=,}", ARG (1), ARG (1), ARG (0));
}
break;
case PPC_INS_EXTSW:
op->sign = true;

4
libr/anal/p/anal_ppc_gnu.c
View File

@ -34,7 +34,9 @@ static int ppc_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *bytes, int len
// bctr
} else {
op->jump = (aa)?(baddr):(addr+baddr);
if (lk) op->fail = addr+4;
if (lk) {
op->fail = addr + 4;
}
}
op->eob = 1;
break;

17
libr/anal/p/anal_riscv.c
View File

@ -17,7 +17,9 @@ static bool _is_any(const char *str, ...) {
va_start (va, str);
while (true) {
cur = va_arg (va, char *);
if (!cur) break;
if (!cur) {
break;
}
if (!strcmp (str, cur)) {
va_end (va);
return true;
@ -72,13 +74,18 @@ static int riscv_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int le
op->type = R_ANAL_OP_TYPE_ILL;
return -1;
}
if (!o || !o->name) return op->size;
if (!o || !o->name) {
return op->size;
}
for (; o < &riscv_opcodes[NUMOPCODES]; o++) {
// XXX ASAN segfault if ( !(o->match_func)(o, word) ) continue;
if ( no_alias && (o->pinfo & INSN_ALIAS) ) continue;
if ( isdigit ((int)(o->subset[0])) && atoi (o->subset) != xlen) continue;
else {
if (no_alias && (o->pinfo & INSN_ALIAS)) {
continue;
}
if (isdigit ((int)(o->subset[0])) && atoi (o->subset) != xlen) {
continue;
} else {
break;
}
}

23
libr/anal/p/anal_snes.c
View File

@ -13,8 +13,9 @@ static struct snes_asm_flags* snesflags = NULL;
static int snes_anop(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int len) {
memset (op, '\0', sizeof (RAnalOp));
op->size = snes_op_get_size(snesflags->M, snesflags->X, &snes_op[data[0]]);
if (op->size > len)
if (op->size > len) {
return op->size = 0;
}
op->nopcode = 1;
op->addr = addr;
op->type = R_ANAL_OP_TYPE_UNK;
@ -219,19 +220,29 @@ static int snes_anop(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int l
op->type = R_ANAL_OP_TYPE_RET;
break;
case 0xc2: // rep
if ( ((st8)data[1]) & 0x10 ) snesflags->X = 0;
if ( ((st8)data[1]) & 0x20 ) snesflags->M = 0;
if (((st8)data[1]) & 0x10) {
snesflags->X = 0;
}
if (((st8)data[1]) & 0x20) {
snesflags->M = 0;
}
break;
case 0xe2: // sep
if ( ((st8)data[1]) & 0x10 ) snesflags->X = 1;
if ( ((st8)data[1]) & 0x20 ) snesflags->M = 1;
if (((st8)data[1]) & 0x10) {
snesflags->X = 1;
}
if (((st8)data[1]) & 0x20) {
snesflags->M = 1;
}
break;
}
return op->size;
}
static int snes_anal_init (void* user) {
if (!snesflags) snesflags = malloc(sizeof( struct snes_asm_flags ));
if (!snesflags) {
snesflags = malloc (sizeof (struct snes_asm_flags));
}
memset(snesflags,0,sizeof (struct snes_asm_flags));
return 0;
}

23
libr/anal/p/anal_sparc_cs.c
View File

@ -105,8 +105,9 @@ static int analop(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len) {
}
mode = CS_MODE_LITTLE_ENDIAN;
if (!strcmp (a->cpu, "v9"))
if (!strcmp (a->cpu, "v9")) {
mode |= CS_MODE_V9;
}
if (mode != omode) {
cs_close (&handle);
handle = 0;
@ -211,17 +212,21 @@ static int analop(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len) {
switch (INSOP(0).type) {
case SPARC_OP_REG:
op->type = R_ANAL_OP_TYPE_CJMP;
if (INSCC != SPARC_CC_ICC_N) // never
op->jump = INSOP(1).imm;
if (INSCC != SPARC_CC_ICC_A) // always
op->fail = addr+4;
if (INSCC != SPARC_CC_ICC_N) { // never
op->jump = INSOP (1).imm;
}
if (INSCC != SPARC_CC_ICC_A) { // always
op->fail = addr + 4;
}
break;
case SPARC_OP_IMM:
op->type = R_ANAL_OP_TYPE_CJMP;
if (INSCC != SPARC_CC_ICC_N) // never
op->jump = INSOP(0).imm;
if (INSCC != SPARC_CC_ICC_A) // always
op->fail = addr+4;
if (INSCC != SPARC_CC_ICC_N) { // never
op->jump = INSOP (0).imm;
}
if (INSCC != SPARC_CC_ICC_A) { // always
op->fail = addr + 4;
}
break;
default:
// MEM?

5
libr/anal/p/anal_sparc_gnu.c
View File

@ -304,8 +304,9 @@ static void anal_call(RAnalOp *op, const ut32 insn, const ut64 addr) {
static void anal_jmpl(RAnal const * const anal, RAnalOp *op, const ut32 insn, const ut64 addr) {
st64 disp = 0;
if (X_LDST_I(insn))
disp = get_immed_sgnext(insn, 12);
if (X_LDST_I (insn)) {
disp = get_immed_sgnext (insn, 12);
}
if (X_RD(insn) == GPR_O7) {
op->type = R_ANAL_OP_TYPE_UCALL;

9
libr/anal/p/anal_tms320.c
View File

@ -38,20 +38,23 @@ int tms320_c55x_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf, int len)
if (match(str, "B ")) {
op->type = R_ANAL_OP_TYPE_JMP;
if (match(str, "B AC"))
if (match (str, "B AC")) {
op->type = R_ANAL_OP_TYPE_UJMP;
}
} else if (match(str, "BCC ") || match(str, "BCCU ")) {
op->type = R_ANAL_OP_TYPE_CJMP;
} else if (match(str, "CALL ")) {
op->type = R_ANAL_OP_TYPE_CALL;
if (match(str, "CALL AC"))
if (match (str, "CALL AC")) {
op->type = R_ANAL_OP_TYPE_UCALL;
}
} else if (match(str, "CALLCC ")) {
op->type = R_ANAL_OP_TYPE_CCALL;
} else if (match(str, "RET")) {
op->type = R_ANAL_OP_TYPE_RET;
if (match(str, "RETCC"))
if (match (str, "RETCC")) {
op->type = R_ANAL_OP_TYPE_CRET;
}
} else if (match(str, "MOV ")) {
op->type = R_ANAL_OP_TYPE_MOV;
} else if (match(str, "PSHBOTH ")) {

6
libr/anal/p/anal_tms320_c55x_plus.c
View File

@ -12,12 +12,14 @@ int tms320_c55x_plus_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf, int
ut16 *ins = (ut16*)buf;
ut32 ins_len;
if (!buf || len <= 0)
if (!buf || len <= 0) {
return 0;
}
ins_len = get_ins_len(buf[0]);
if (ins_len == 0)
if (ins_len == 0) {
return 0;
}
memset (op, 0, sizeof (RAnalOp));
op->type = R_ANAL_OP_TYPE_UNK;

40
libr/anal/p/anal_v810.c
View File

@ -17,17 +17,33 @@ enum {
};
static void update_flags(RAnalOp *op, int flags) {
if (flags & V810_FLAG_CY) r_strbuf_append(&op->esil, ",$c31,cy,=");
if (flags & V810_FLAG_OV) r_strbuf_append(&op->esil, ",$o,ov,=");
if (flags & V810_FLAG_S) r_strbuf_append(&op->esil, ",$s,s,=");
if (flags & V810_FLAG_Z) r_strbuf_append(&op->esil, ",$z,z,=");
if (flags & V810_FLAG_CY) {
r_strbuf_append (&op->esil, ",$c31,cy,=");
}
if (flags & V810_FLAG_OV) {
r_strbuf_append (&op->esil, ",$o,ov,=");
}
if (flags & V810_FLAG_S) {
r_strbuf_append (&op->esil, ",$s,s,=");
}
if (flags & V810_FLAG_Z) {
r_strbuf_append (&op->esil, ",$z,z,=");
}
}
static void clear_flags(RAnalOp *op, int flags) {
if (flags & V810_FLAG_CY) r_strbuf_append(&op->esil, ",0,cy,=");
if (flags & V810_FLAG_OV) r_strbuf_append(&op->esil, ",0,ov,=");
if (flags & V810_FLAG_S) r_strbuf_append(&op->esil, ",0,s,=");
if (flags & V810_FLAG_Z) r_strbuf_append(&op->esil, ",0,z,=");
if (flags & V810_FLAG_CY) {
r_strbuf_append (&op->esil, ",0,cy,=");
}
if (flags & V810_FLAG_OV) {
r_strbuf_append (&op->esil, ",0,ov,=");
}
if (flags & V810_FLAG_S) {
r_strbuf_append (&op->esil, ",0,s,=");
}
if (flags & V810_FLAG_Z) {
r_strbuf_append (&op->esil, ",0,z,=");
}
}
static int v810_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf, int len) {
@ -58,8 +74,9 @@ static int v810_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf, int len)
op->ptr = op->val = -1;
opcode = OPCODE(word1);
if (opcode>>3 == 0x4)
if (opcode >> 3 == 0x4) {
opcode &= 0x20;
}
switch (opcode) {
case V810_MOV:
@ -104,10 +121,11 @@ static int v810_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf, int len)
update_flags (op, V810_FLAG_OV | V810_FLAG_S | V810_FLAG_Z);
break;
case V810_JMP:
if (REG1(word1) == 31)
if (REG1 (word1) == 31) {
op->type = R_ANAL_OP_TYPE_RET;
else
} else {
op->type = R_ANAL_OP_TYPE_UJMP;
}
r_strbuf_appendf (&op->esil, "r%u,pc,=",
REG1(word1));
break;

32
libr/anal/p/anal_v850.c
View File

@ -12,17 +12,33 @@
#include <v850_disas.h>
static void update_flags(RAnalOp *op, int flags) {
if (flags & V850_FLAG_CY) r_strbuf_append (&op->esil, ",$c31,cy,=");
if (flags & V850_FLAG_OV) r_strbuf_append (&op->esil, ",$o,ov,=");
if (flags & V850_FLAG_S) r_strbuf_append (&op->esil, ",$s,s,=");
if (flags & V850_FLAG_Z) r_strbuf_append (&op->esil, ",$z,z,=");
if (flags & V850_FLAG_CY) {
r_strbuf_append (&op->esil, ",$c31,cy,=");
}
if (flags & V850_FLAG_OV) {
r_strbuf_append (&op->esil, ",$o,ov,=");
}
if (flags & V850_FLAG_S) {
r_strbuf_append (&op->esil, ",$s,s,=");
}
if (flags & V850_FLAG_Z) {
r_strbuf_append (&op->esil, ",$z,z,=");
}
}
static void clear_flags(RAnalOp *op, int flags) {
if (flags & V850_FLAG_CY) r_strbuf_append (&op->esil, ",0,cy,=");
if (flags & V850_FLAG_OV) r_strbuf_append (&op->esil, ",0,ov,=");
if (flags & V850_FLAG_S) r_strbuf_append (&op->esil, ",0,s,=");
if (flags & V850_FLAG_Z) r_strbuf_append (&op->esil, ",0,z,=");
if (flags & V850_FLAG_CY) {
r_strbuf_append (&op->esil, ",0,cy,=");
}
if (flags & V850_FLAG_OV) {
r_strbuf_append (&op->esil, ",0,ov,=");
}
if (flags & V850_FLAG_S) {
r_strbuf_append (&op->esil, ",0,s,=");
}
if (flags & V850_FLAG_Z) {
r_strbuf_append (&op->esil, ",0,z,=");
}
}
static int v850_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf, int len) {

4
libr/anal/p/anal_vax.c
View File

@ -13,7 +13,9 @@
static int vax_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf, int len) {
op->size = 1;
if (len<1) return -1;
if (len < 1) {
return -1;
}
op->type = R_ANAL_OP_TYPE_UNK;
switch (buf[0]) {
case 0xd0:

8
libr/anal/p/anal_x86_cs.c
View File

@ -2071,8 +2071,9 @@ static void anop(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len, csh
}
break;
case X86_OP_IMM:
if (INSOP(1).imm > 10)
op->ptr = INSOP(1).imm;
if (INSOP (1).imm > 10) {
op->ptr = INSOP (1).imm;
}
break;
default:
break;
@ -2746,8 +2747,9 @@ static int analop(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len) {
//#if X86_GRP_PRIVILEGE>0
if (insn) {
#if HAVE_CSGRP_PRIVILEGE
if (cs_insn_group (handle, insn, X86_GRP_PRIVILEGE))
if (cs_insn_group (handle, insn, X86_GRP_PRIVILEGE)) {
op->family = R_ANAL_OP_FAMILY_PRIV;
}
#endif
#if !USE_ITER_API
cs_free (insn, n);

30
libr/anal/p/anal_xap.c
View File

@ -129,8 +129,9 @@ static int xap_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *bytes, int len
// BSR
op->type = R_ANAL_OP_TYPE_CALL;
op->jump = label_off (&d);
if (op->jump&1)
op->jump+=3;
if (op->jump & 1) {
op->jump += 3;
}
op->fail = addr+2;
op->eob = true;
break;
@ -150,16 +151,18 @@ static int xap_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *bytes, int len
case 0: // BRA
op->type = R_ANAL_OP_TYPE_JMP;
op->jump = label_off (&d)+4;
if (op->jump&1)
op->jump+=3;
if (op->jump & 1) {
op->jump += 3;
}
op->eob = true;
break;
case 1:
// BLT
op->type = R_ANAL_OP_TYPE_CJMP;
op->jump = label_off (&d);
if (op->jump&1)
op->jump+=3;
if (op->jump & 1) {
op->jump += 3;
}
op->fail = addr + 2;
op->eob = true;
break;
@ -167,8 +170,9 @@ static int xap_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *bytes, int len
// BPL
op->type = R_ANAL_OP_TYPE_CJMP;
op->jump = label_off (&d);
if (op->jump&1)
op->jump+=3;
if (op->jump & 1) {
op->jump += 3;
}
op->fail = addr + 2;
op->eob = true;
break;
@ -176,8 +180,9 @@ static int xap_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *bytes, int len
// BMI
op->type = R_ANAL_OP_TYPE_CJMP;
op->jump = label_off (&d);
if (op->jump&1)
op->jump+=3;
if (op->jump & 1) {
op->jump += 3;
}
op->fail = addr + 2;
op->eob = true;
break;
@ -191,8 +196,9 @@ static int xap_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *bytes, int len
case 3: // BCS
op->type = R_ANAL_OP_TYPE_CJMP;
op->jump = label_off (&d);
if (op->jump&1)
op->jump+=3;
if (op->jump & 1) {
op->jump += 3;
}
op->fail = addr+2;
break;
}

3
libr/anal/p/anal_xcore_cs.c
View File

@ -56,8 +56,9 @@ static int analop(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len) {
cs_insn *insn;
int mode, n, ret;
mode = CS_MODE_BIG_ENDIAN;
if (!strcmp (a->cpu, "v9"))
if (!strcmp (a->cpu, "v9")) {
mode |= CS_MODE_V9;
}
if (mode != omode) {
if (handle) {
cs_close (&handle);

16
libr/anal/p/anal_xtensa.c
View File

@ -282,10 +282,11 @@ static void xtensa_imp_op (RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf)
op->type = R_ANAL_OP_TYPE_NULL;
break;
case 0xe:
if (((buf[0] >> 4) & 0xf) <= 1)
if (((buf[0] >> 4) & 0xf) <= 1) {
op->type = R_ANAL_OP_TYPE_RET;
else
} else {
xtensa_unk_op (anal, op, addr, buf);
}
break;
default:
xtensa_unk_op (anal, op, addr, buf);
@ -495,10 +496,11 @@ static void xtensa_lsci_op (RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf)
ut8 r = buf[1] >> 4;
op->family = R_ANAL_OP_FAMILY_FPU;
if ((r & 3) == 0) {
if (r & 4)
if (r & 4) {
xtensa_store_op (anal, op, addr, buf);
else
} else {
xtensa_load_op (anal, op, addr, buf);
}
} else {
xtensa_unk_op (anal, op, addr, buf);
}
@ -1904,14 +1906,16 @@ static void analop_esil (xtensa_isa isa, xtensa_opcode opcode, xtensa_format for
}
static int xtensa_op (RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf_original, int len_original) {
if (!op)
if (!op) {
return 1;
}
memset (op, 0, sizeof (RAnalOp));
r_strbuf_init (&op->esil);
op->size = xtensa_length (buf_original);
if (op->size > len_original)
if (op->size > len_original) {
return 1;
}
xtensa_op0_fns[(buf_original[0] & 0xf)] (anal, op, addr, buf_original);

7
libr/anal/reflines.c
View File

@ -193,7 +193,9 @@ R_API RList *r_anal_reflines_get(RAnal *anal, ut64 addr, const ut8 *buf, ut64 le
if (min < 0) {
min = 0;
}
while (free_levels[++min] == 1);
while (free_levels[++min] == 1) {
;
}
} else {
free_levels[el->r->level - 1] = 0;
if (min > el->r->level - 1) {
@ -321,8 +323,9 @@ R_API int r_anal_reflines_middle(RAnal *a, RList* /*<RAnalRefline>*/ list, ut64
RAnalRefline *ref;
RListIter *iter;
r_list_foreach (list, iter, ref) {
if ((ref->to > addr) && (ref->to < addr+len))
if ((ref->to > addr) && (ref->to < addr + len)) {
return true;
}
}
}
return false;

53
libr/anal/value.c
View File

@ -13,7 +13,9 @@ R_API RAnalValue *r_anal_value_new_from_string(const char *str) {
R_API RAnalValue *r_anal_value_copy(RAnalValue *ov) {
RAnalValue *v = R_NEW0 (RAnalValue);
if (!v) return NULL;
if (!v) {
return NULL;
}
memcpy (v, ov, sizeof (RAnalValue));
// reference to reg and regdelta should be kept
return v;
@ -34,13 +36,16 @@ R_API void r_anal_value_free(RAnalValue *value) {
// mul*value+regbase+regidx+delta
R_API ut64 r_anal_value_to_ut64(RAnal *anal, RAnalValue *val) {
ut64 num;
if (!val)
if (!val) {
return 0LL;
}
num = val->base + (val->delta*(val->mul?val->mul:1));
if (val->reg)
if (val->reg) {
num += r_reg_get_value (anal->reg, val->reg);
if (val->regdelta)
}
if (val->regdelta) {
num += r_reg_get_value (anal->reg, val->regdelta);
}
switch (val->memref) {
case 1:
case 2:
@ -60,10 +65,13 @@ R_API int r_anal_value_set_ut64(RAnal *anal, RAnalValue *val, ut64 num) {
ut64 addr = r_anal_value_to_ut64 (anal, val);
r_mem_set_num (data, val->memref, num);
anal->iob.write_at (anal->iob.io, addr, data, val->memref);
} else eprintf ("No IO binded to r_anal\n");
} else {
eprintf ("No IO binded to r_anal\n");
}
} else {
if (val->reg)
if (val->reg) {
r_reg_set_value (anal->reg, val->reg, num);
}
}
return false; //is this necessary
}
@ -73,9 +81,11 @@ R_API char *r_anal_value_to_string (RAnalValue *value) {
if (value) {
out = r_str_new ("");
if (!value->base && !value->reg) {
if (value->imm != -1LL)
if (value->imm != -1LL) {
out = r_str_appendf (out, "0x%"PFMT64x, value->imm);
else out = r_str_append (out, "-1");
} else {
out = r_str_append (out, "-1");
}
} else {
if (value->memref) {
switch (value->memref) {
@ -86,13 +96,26 @@ R_API char *r_anal_value_to_string (RAnalValue *value) {
}
out = r_str_append (out, "[");
}
if (value->mul) out = r_str_appendf (out, "%d*", value->mul);
if (value->reg) out = r_str_appendf (out, "%s", value->reg->name);
if (value->regdelta) out = r_str_appendf (out, "+%s", value->regdelta->name);
if (value->base!=0) out = r_str_appendf (out, "0x%"PFMT64x, value->base);
if (value->delta>0) out = r_str_appendf (out, "+0x%"PFMT64x, value->delta);
else if (value->delta<0) out = r_str_appendf (out, "-0x%"PFMT64x, -value->delta);
if (value->memref) out = r_str_append (out, "]");
if (value->mul) {
out = r_str_appendf (out, "%d*", value->mul);
}
if (value->reg) {
out = r_str_appendf (out, "%s", value->reg->name);
}
if (value->regdelta) {
out = r_str_appendf (out, "+%s", value->regdelta->name);
}
if (value->base != 0) {
out = r_str_appendf (out, "0x%" PFMT64x, value->base);
}
if (value->delta > 0) {
out = r_str_appendf (out, "+0x%" PFMT64x, value->delta);
} else if (value->delta < 0) {
out = r_str_appendf (out, "-0x%" PFMT64x, -value->delta);
}
if (value->memref) {
out = r_str_append (out, "]");
}
}
}
return out;

3
libr/anal/vtable.c
View File

@ -247,8 +247,9 @@ R_API void r_anal_list_vtables(RAnal *anal, int rad) {
bool isFirstMethod = true;
r_cons_printf ("{\"offset\":%"PFMT64d",\"methods\":[", table->saddr);
r_vector_foreach (&table->methods, curMethod) {
if(!isFirstMethod)
if (!isFirstMethod) {
r_cons_print (",");
}
RAnalFunction *fcn = r_anal_get_fcn_in (anal, curMethod->addr, 0);
const char* const name = fcn ? fcn->name : NULL;
r_cons_printf ("{\"offset\":%"PFMT64d",\"name\":\"%s\"}",

398
libr/asm/arch/arc/gnu/arc-dis.c
View File

@ -183,25 +183,28 @@ typedef enum
static const char *
core_reg_name (struct arcDisState * state, int val)
{
if (state->coreRegName)
return (*state->coreRegName)(state->_this, val);
return 0;
if (state->coreRegName) {
return (*state->coreRegName) (state->_this, val);
}
return 0;
}
static const char *
aux_reg_name (struct arcDisState * state, int val)
{
if (state->auxRegName)
return (*state->auxRegName)(state->_this, val);
return 0;
if (state->auxRegName) {
return (*state->auxRegName) (state->_this, val);
}
return 0;
}
static const char *
cond_code_name (struct arcDisState * state, int val)
{
if (state->condCodeName)
return (*state->condCodeName)(state->_this, val);
return 0;
if (state->condCodeName) {
return (*state->condCodeName) (state->_this, val);
}
return 0;
}
static const char *
@ -210,16 +213,18 @@ instruction_name (struct arcDisState * state,
int op2,
int * flags)
{
if (state->instName)
return (*state->instName)(state->_this, op1, op2, flags);
return 0;
if (state->instName) {
return (*state->instName) (state->_this, op1, op2, flags);
}
return 0;
}
static void
mwerror (struct arcDisState * state, const char * msg)
{
if (state->err != 0)
(*state->err)(state->_this, (msg));
if (state->err != 0) {
(*state->err) (state->_this, (msg));
}
}
static const char *
@ -258,42 +263,39 @@ arc_sprintf (struct arcDisState *state, char *buf, const char *format, ...)
regMap[0] = 0;
regMap[1] = 0;
while (1)
switch (*p++)
{
case 0:
goto DOCOMM; /* Return. */
default:
*bp++ = p[-1];
break;
case '%':
size = 0;
leading_zero = 0;
RETRY: ;
switch (*p++)
{
case '0':
case '1':
case '2':
case '3':
case '4':
case '5':
case '6':
case '7':
case '8':
case '9':
{
/* size. */
size = p[-1] - '0';
if (size == 0)
leading_zero = 1; /* e.g. %08x */
while (*p >= '0' && *p <= '9')
{
size = size * 10 + *p - '0';
p++;
}
goto RETRY;
}
while (1) {
switch (*p++) {
case 0:
goto DOCOMM; /* Return. */
default:
*bp++ = p[-1];
break;
case '%':
size = 0;
leading_zero = 0;
RETRY:;
switch (*p++) {
case '0':
case '1':
case '2':
case '3':
case '4':
case '5':
case '6':
case '7':
case '8':
case '9': {
/* size. */
size = p[-1] - '0';
if (size == 0) {
leading_zero = 1; /* e.g. %08x */
}
while (*p >= '0' && *p <= '9') {
size = size * 10 + *p - '0';
p++;
}
goto RETRY;
}
#define inc_bp() bp = bp + strlen (bp)
case 'h':
@ -307,13 +309,15 @@ arc_sprintf (struct arcDisState *state, char *buf, const char *format, ...)
{
int val = va_arg (ap, int);
if (size != 0)
if (leading_zero)
sprintf (bp, "%0*x", size, val);
else
sprintf (bp, "%*x", size, val);
else
sprintf (bp, "%x", val);
if (size != 0) {
if (leading_zero) {
sprintf (bp, "%0*x", size, val);
} else {
sprintf (bp, "%*x", size, val);
}
} else {
sprintf (bp, "%x", val);
}
inc_bp ();
}
break;
@ -321,10 +325,11 @@ arc_sprintf (struct arcDisState *state, char *buf, const char *format, ...)
{
int val = va_arg (ap, int);
if (size != 0)
sprintf (bp, "%*d", size, val);
else
sprintf (bp, "%d", val);
if (size != 0) {
sprintf (bp, "%*d", size, val);
} else {
sprintf (bp, "%d", val);
}
inc_bp ();
}
break;
@ -349,10 +354,11 @@ arc_sprintf (struct arcDisState *state, char *buf, const char *format, ...)
const char *ext;
ext = core_reg_name (state, val);
if (ext)
sprintf (bp, "%s", ext);
else
sprintf (bp, "r%d", val);
if (ext) {
sprintf (bp, "%s", ext);
} else {
sprintf (bp, "r%d", val);
}
}
break;
}
@ -378,10 +384,11 @@ arc_sprintf (struct arcDisState *state, char *buf, const char *format, ...)
const char *ext;
ext = aux_reg_name (state, val);
if (ext)
sprintf (bp, "%s", ext);
else
arc_sprintf (state, bp, "%h", val);
if (ext) {
sprintf (bp, "%s", ext);
} else {
arc_sprintf (state, bp, "%h", val);
}
}
break;
}
@ -398,7 +405,8 @@ arc_sprintf (struct arcDisState *state, char *buf, const char *format, ...)
fprintf (stderr, "?? format %c\n", p[-1]);
break;
}
}
}
}
DOCOMM: *bp = 0;
va_end (ap);
@ -426,20 +434,23 @@ write_instr_name_(struct arcDisState * state,
{
const char *cc = 0;
if (!condCodeIsPartOfName)
strcat (state->instrBuffer, ".");
if (cond < 16)
cc = condName[cond];
else
cc = cond_code_name (state, cond);
if (!cc)
cc = "???";
if (!condCodeIsPartOfName) {
strcat (state->instrBuffer, ".");
}
if (cond < 16) {
cc = condName[cond];
} else {
cc = cond_code_name (state, cond);
}
if (!cc) {
cc = "???";
}
strcat (state->instrBuffer, cc);
}
if (flag)
strcat (state->instrBuffer, ".f");
switch (state->nullifyMode)
{
if (flag) {
strcat (state->instrBuffer, ".f");
}
switch (state->nullifyMode) {
case BR_exec_always:
strcat (state->instrBuffer, ".d");
break;
@ -449,12 +460,15 @@ write_instr_name_(struct arcDisState * state,
case BR_exec_when_no_jump:
break;
}
if (signExtend)
strcat (state->instrBuffer, ".x");
if (addrWriteBack)
strcat (state->instrBuffer, ".a");
if (directMem)
strcat (state->instrBuffer, ".di");
if (signExtend) {
strcat (state->instrBuffer, ".x");
}
if (addrWriteBack) {
strcat (state->instrBuffer, ".a");
}
if (directMem) {
strcat (state->instrBuffer, ".di");
}
}
#define write_instr_name() \
@ -506,8 +520,9 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState * state)
state->ea_reg2 = no_reg;
state->_offset = 0;
if (! NEXT_WORD (0))
return 0;
if (!NEXT_WORD (0)) {
return 0;
}
state->_opcode = OPCODE (state->words[0]);
instrName = 0;
@ -651,16 +666,23 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState * state)
instrName = "???";
state->flow = invalid_instr;
}
if (flags & IGNORE_FIRST_OPD)
ignoreFirstOpd = 1;
break;
if (flags & IGNORE_FIRST_OPD) {
ignoreFirstOpd = 1;
}
break;
}
break;
case op_BC: instrName = "b";
case op_BLC: if (!instrName) instrName = "bl";
case op_LPC: if (!instrName) instrName = "lp";
case op_BLC:
if (!instrName) {
instrName = "bl";
}
case op_LPC:
if (!instrName) {
instrName = "lp";
}
case op_JC:
if (!instrName)
{
@ -706,9 +728,9 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState * state)
with ARC). This encoding says: xor -1, -1, -1. */
instrName = "nop";
decodingClass = CLASS_A4_OP3_SUBOPC3F;
}
else
instrName = "xor";
} else {
instrName = "xor";
}
break;
default:
@ -719,9 +741,10 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState * state)
instrName = "???";
state->flow=invalid_instr;
}
if (flags & IGNORE_FIRST_OPD)
ignoreFirstOpd = 1;
break;
if (flags & IGNORE_FIRST_OPD) {
ignoreFirstOpd = 1;
}
break;
}
fieldAisReg = fieldBisReg = fieldCisReg = 1; /* Assume regs for now. */
@ -735,8 +758,9 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState * state)
case CLASS_A4_ARITH:
CHECK_FIELD_A ();
CHECK_FIELD_B ();
if (!repeatsOp)
CHECK_FIELD_C ();
if (!repeatsOp) {
CHECK_FIELD_C ();
}
CHECK_FLAG_COND_NULLIFY ();
write_instr_name ();
@ -744,8 +768,9 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState * state)
{
WRITE_FORMAT_x (A);
WRITE_FORMAT_COMMA_x (B);
if (!repeatsOp)
WRITE_FORMAT_COMMA_x (C);
if (!repeatsOp) {
WRITE_FORMAT_COMMA_x (C);
}
WRITE_NOP_COMMENT ();
arc_sprintf (state, state->operandBuffer, formatString,
fieldA, fieldB, fieldC);
@ -753,8 +778,9 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState * state)
else
{
WRITE_FORMAT_x (B);
if (!repeatsOp)
WRITE_FORMAT_COMMA_x (C);
if (!repeatsOp) {
WRITE_FORMAT_COMMA_x (C);
}
arc_sprintf (state, state->operandBuffer, formatString,
fieldB, fieldC);
}
@ -831,8 +857,9 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState * state)
add_target (fieldB);
/* Screwy JLcc requires .jd mode to execute correctly
but we pretend it is .nd (no delay slot). */
if (is_linked && state->nullifyMode == BR_exec_when_jump)
state->nullifyMode = BR_exec_when_no_jump;
if (is_linked && state->nullifyMode == BR_exec_when_jump) {
state->nullifyMode = BR_exec_when_no_jump;
}
}
else
{
@ -852,31 +879,35 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState * state)
fieldAisReg = 0;
WRITE_FORMAT_COMMA_x (A);
}
if (IS_REG (B))
arc_sprintf (state, state->operandBuffer, formatString, fieldB, fieldA);
else
arc_sprintf (state, state->operandBuffer, formatString,
post_address (state, fieldB), fieldA);
break;
if (IS_REG (B)) {
arc_sprintf (state, state->operandBuffer, formatString, fieldB, fieldA);
} else {
arc_sprintf (state, state->operandBuffer, formatString,
post_address (state, fieldB), fieldA);
}
break;
case CLASS_A4_LD0:
/* LD instruction. B and C can be regs, or one (both?) can be limm. */
CHECK_FIELD_A ();
CHECK_FIELD_B ();
CHECK_FIELD_C ();
if (dbg)
printf ("5:b reg %d %d c reg %d %d \n",
fieldBisReg,fieldB,fieldCisReg,fieldC);
if (dbg) {
printf ("5:b reg %d %d c reg %d %d \n",
fieldBisReg, fieldB, fieldCisReg, fieldC);
}
state->_offset = 0;
state->_ea_present = 1;
if (fieldBisReg)
state->ea_reg1 = fieldB;
else
state->_offset += fieldB;
if (fieldCisReg)
state->ea_reg2 = fieldC;
else
state->_offset += fieldC;
if (fieldBisReg) {
state->ea_reg1 = fieldB;
} else {
state->_offset += fieldB;
}
if (fieldCisReg) {
state->ea_reg2 = fieldC;
} else {
state->_offset += fieldC;
}
state->_mem_load = 1;
directMem = BIT (state->words[0], 5);
@ -885,10 +916,11 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState * state)
write_instr_name ();
WRITE_FORMAT_x_COMMA_LB(A);
if (fieldBisReg || fieldB != 0)
WRITE_FORMAT_x_COMMA (B);
else
fieldB = fieldC;
if (fieldBisReg || fieldB != 0) {
WRITE_FORMAT_x_COMMA (B);
} else {
fieldB = fieldC;
}
WRITE_FORMAT_x_RB (C);
arc_sprintf (state, state->operandBuffer, formatString,
@ -901,18 +933,20 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState * state)
CHECK_FIELD_A ();
fieldC = FIELDD (state->words[0]);
if (dbg)
eprintf ("6:b reg %d %d c 0x%x \n",
fieldBisReg, fieldB, fieldC);
if (dbg) {
eprintf ("6:b reg %d %d c 0x%x \n",
fieldBisReg, fieldB, fieldC);
}
state->_ea_present = 1;
state->_offset = fieldC;
state->_mem_load = 1;
if (fieldBisReg)
state->ea_reg1 = fieldB;
/* Field B is either a shimm (same as fieldC) or limm (different!)
if (fieldBisReg) {
state->ea_reg1 = fieldB;
/* Field B is either a shimm (same as fieldC) or limm (different!)
Say ea is not present, so only one of us will do the name lookup. */
else
state->_offset += fieldB, state->_ea_present = 0;
} else {
state->_offset += fieldB, state->_ea_present = 0;
}
directMem = BIT (state->words[0],14);
addrWriteBack = BIT (state->words[0],12);
@ -932,9 +966,9 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState * state)
{
fieldCisReg = 0;
WRITE_FORMAT_COMMA_x_RB (C);
}
else
WRITE_FORMAT_RB ();
} else {
WRITE_FORMAT_RB ();
}
}
arc_sprintf (state, state->operandBuffer, formatString,
fieldA, fieldB, fieldC);
@ -947,17 +981,20 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState * state)
fieldA = FIELDD(state->words[0]); /* shimm */
/* [B,A offset] */
if (dbg) eprintf("7:b reg %d %x off %x\n",
fieldBisReg,fieldB,fieldA);
if (dbg) {
eprintf ("7:b reg %d %x off %x\n",
fieldBisReg, fieldB, fieldA);
}
state->_ea_present = 1;
state->_offset = fieldA;
if (fieldBisReg)
state->ea_reg1 = fieldB;
/* Field B is either a shimm (same as fieldA) or limm (different!)
if (fieldBisReg) {
state->ea_reg1 = fieldB;
/* Field B is either a shimm (same as fieldA) or limm (different!)
Say ea is not present, so only one of us will do the name lookup.
(for is_limm we do the name translation here). */
else
state->_offset += fieldB, state->_ea_present = 0;
} else {
state->_offset += fieldB, state->_ea_present = 0;
}
directMem = BIT (state->words[0], 26);
addrWriteBack = BIT (state->words[0], 24);
@ -977,9 +1014,9 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState * state)
{
fieldAisReg = 0;
WRITE_FORMAT_COMMA_x_RB(A);
}
else
WRITE_FORMAT_RB();
} else {
WRITE_FORMAT_RB ();
}
}
arc_sprintf (state, state->operandBuffer, formatString,
fieldC, fieldB, fieldA);
@ -1088,45 +1125,46 @@ ARCTangent_decodeInstr (bfd_vma address, disassemble_info *info)
(*info->memory_error_func) (status, address, info);
return -1;
}
if (info->endian == BFD_ENDIAN_LITTLE)
s.words[0] = bfd_getl32(buffer);
else
s.words[0] = bfd_getb32(buffer);
/* Always read second word in case of limm. */
/* We ignore the result since last insn may not have a limm. */
status = (*info->read_memory_func) (address + 4, buffer, 4, info);
if (info->endian == BFD_ENDIAN_LITTLE)
s.words[1] = bfd_getl32(buffer);
else
s.words[1] = bfd_getb32(buffer);
if (info->endian == BFD_ENDIAN_LITTLE) {
s.words[0] = bfd_getl32 (buffer);
} else {
s.words[0] = bfd_getb32 (buffer);
}
/* Always read second word in case of limm. */
/* We ignore the result since last insn may not have a limm. */
status = (*info->read_memory_func) (address + 4, buffer, 4, info);
if (info->endian == BFD_ENDIAN_LITTLE) {
s.words[1] = bfd_getl32 (buffer);
} else {
s.words[1] = bfd_getb32 (buffer);
}
s._this = &s;
s.coreRegName = _coreRegName;
s.auxRegName = _auxRegName;
s.condCodeName = _condCodeName;
s.instName = _instName;
s._this = &s;
s.coreRegName = _coreRegName;
s.auxRegName = _auxRegName;
s.condCodeName = _condCodeName;
s.instName = _instName;
/* Disassemble. */
dsmOneArcInst (address, (void *)&s);
/* Disassemble. */
dsmOneArcInst (address, (void *)&s);
/* Display the disassembly instruction. */
/*
/* Display the disassembly instruction. */
/*
(*func) (stream, "%08lx ", s.words[0]);
(*func) (stream, " ");
*/
(*func) (stream, "%s ", s.instrBuffer);
(*func) (stream, "%s ", s.instrBuffer);
if (__TRANSLATION_REQUIRED (s))
{
bfd_vma addr = s.addresses[s.operandBuffer[1] - '0'];
if (__TRANSLATION_REQUIRED (s)) {
bfd_vma addr = s.addresses[s.operandBuffer[1] - '0'];
(*info->print_address_func) ((bfd_vma) addr, info);
//(*func) (stream, "\n");
(*info->print_address_func) ((bfd_vma)addr, info);
//(*func) (stream, "\n");
} else {
(*func) (stream, "%s", s.operandBuffer);
}
else
(*func) (stream, "%s",s.operandBuffer);
return s.instructionLen;
return s.instructionLen;
}

68
libr/asm/arch/arc/gnu/arc-ext.c
View File

@ -329,10 +329,11 @@ arcExtMap_instName (int opcode, int insn, int *flags)
c = (insn & 0x00e0) >> 5;
i = (insn & 0x001f);
if (i)
minor = i;
else
minor = (c == 0x07) ? b : c;
if (i) {
minor = i;
} else {
minor = (c == 0x07) ? b : c;
}
}
/* 32-bit instructions. */
else
@ -370,15 +371,16 @@ arcExtMap_instName (int opcode, int insn, int *flags)
}
else
{
if (A != 0x3f)
minor = A;
else
minor = B;
if (A != 0x3f) {
minor = A;
} else {
minor = B;
}
}
}
}
else /* ARCTangent extension instructions. */
minor = insn;
} else { /* ARCTangent extension instructions. */
minor = insn;
}
temp = arc_extension_map.instructions[INST_HASH (opcode, minor)];
while (temp)
@ -399,9 +401,10 @@ arcExtMap_instName (int opcode, int insn, int *flags)
const char *
arcExtMap_coreRegName (int regnum)
{
if (regnum < FIRST_EXTENSION_CORE_REGISTER || regnum > LAST_EXTENSION_CORE_REGISTER)
return NULL;
return arc_extension_map.coreRegisters[regnum - FIRST_EXTENSION_CORE_REGISTER].name;
if (regnum < FIRST_EXTENSION_CORE_REGISTER || regnum > LAST_EXTENSION_CORE_REGISTER) {
return NULL;
}
return arc_extension_map.coreRegisters[regnum - FIRST_EXTENSION_CORE_REGISTER].name;
}
@ -409,9 +412,10 @@ arcExtMap_coreRegName (int regnum)
enum ExtReadWrite
arcExtMap_coreReadWrite (int regnum)
{
if (regnum < FIRST_EXTENSION_CORE_REGISTER || regnum > LAST_EXTENSION_CORE_REGISTER)
return REG_INVALID;
return arc_extension_map.coreRegisters[regnum - FIRST_EXTENSION_CORE_REGISTER].rw;
if (regnum < FIRST_EXTENSION_CORE_REGISTER || regnum > LAST_EXTENSION_CORE_REGISTER) {
return REG_INVALID;
}
return arc_extension_map.coreRegisters[regnum - FIRST_EXTENSION_CORE_REGISTER].rw;
}
@ -419,9 +423,10 @@ arcExtMap_coreReadWrite (int regnum)
const char *
arcExtMap_condCodeName (int code)
{
if (code < FIRST_EXTENSION_CONDITION_CODE || code > LAST_EXTENSION_CONDITION_CODE)
return NULL;
return arc_extension_map.condCodes[code - FIRST_EXTENSION_CONDITION_CODE];
if (code < FIRST_EXTENSION_CONDITION_CODE || code > LAST_EXTENSION_CONDITION_CODE) {
return NULL;
}
return arc_extension_map.condCodes[code - FIRST_EXTENSION_CONDITION_CODE];
}
@ -434,8 +439,9 @@ arcExtMap_auxRegName (long address)
for (r = arc_extension_map.auxRegisters; r; r = r->next)
{
if (r->address == address)
return (const char *)r->name;
if (r->address == address) {
return (const char *)r->name;
}
}
return NULL;
}
@ -491,21 +497,25 @@ void dump_ARC_extmap (void)
{
struct ExtInstruction *insn;
for (insn = arc_extension_map.instructions[i]; insn != NULL; insn = insn->next)
printf("INST: %d %d %x %s\n", insn->major, insn->minor, insn->flags, insn->name);
for (insn = arc_extension_map.instructions[i]; insn != NULL; insn = insn->next) {
printf ("INST: %d %d %x %s\n", insn->major, insn->minor, insn->flags, insn->name);
}
}
for (i = 0; i < NUM_EXT_CORE; i++)
{
struct ExtCoreRegister reg = arc_extension_map.coreRegisters[i];
if (reg.name)
printf("CORE: %s %d %s\n", reg.name, reg.number, ExtReadWrite_image(reg.rw));
if (reg.name) {
printf ("CORE: %s %d %s\n", reg.name, reg.number, ExtReadWrite_image (reg.rw));
}
}
for (i = 0; i < NUM_EXT_COND; i++)
if (arc_extension_map.condCodes[i])
printf("COND: %s\n", arc_extension_map.condCodes[i]);
for (i = 0; i < NUM_EXT_COND; i++) {
if (arc_extension_map.condCodes[i]) {
printf ("COND: %s\n", arc_extension_map.condCodes[i]);
}
}
}
/******************************************************************************/

870
libr/asm/arch/arc/gnu/arc-opc.c
View File

File diff suppressed because it is too large Load Diff

764
libr/asm/arch/arc/gnu/arcompact-dis.c
View File

File diff suppressed because it is too large Load Diff

485
libr/asm/arch/arm/aarch64/aarch64-dis.c
View File

@ -87,8 +87,9 @@ parse_aarch64_dis_options (const char *options)
{
const char *option_end;
if (!options)
return;
if (!options) {
return;
}
while (*options != '\0')
{
@ -101,8 +102,9 @@ parse_aarch64_dis_options (const char *options)
/* We know that *options is neither NUL or a comma. */
option_end = options + 1;
while (*option_end != ',' && *option_end != '\0')
option_end++;
while (*option_end != ',' && *option_end != '\0') {
option_end++;
}
parse_aarch64_dis_option (options, option_end - options);
@ -212,10 +214,11 @@ get_expected_qualifier (const aarch64_inst *inst, int i)
/* Should not be called if the qualifier is known. */
assert (inst->operands[i].qualifier == AARCH64_OPND_QLF_NIL);
if (aarch64_find_best_match (inst, inst->opcode->qualifiers_list,
i, qualifiers))
return qualifiers[i];
else
return AARCH64_OPND_QLF_NIL;
i, qualifiers)) {
return qualifiers[i];
} else {
return AARCH64_OPND_QLF_NIL;
}
}
/* Operand extractors. */
@ -284,10 +287,12 @@ aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info,
1000 D */
int pos = -1;
aarch64_insn value = extract_field (FLD_imm5, code, 0);
while (++pos <= 3 && (value & 0x1) == 0)
value >>= 1;
if (pos > 3)
return 0;
while (++pos <= 3 && (value & 0x1) == 0) {
value >>= 1;
}
if (pos > 3) {
return 0;
}
info->qualifier = get_sreg_qualifier_from_value (pos);
info->reglane.index = (unsigned) (value >> 1);
}
@ -368,8 +373,9 @@ aarch64_ext_ldst_reglist (const aarch64_operand *self ATTRIBUTE_UNUSED,
info->reglist.first_regno = extract_field (FLD_Rt, code, 0);
/* opcode */
value = extract_field (FLD_opcode, code, 0);
if (expected_num != data[value].num_elements || data[value].is_reserved)
return 0;
if (expected_num != data[value].num_elements || data[value].is_reserved) {
return 0;
}
info->reglist.num_regs = data[value].num_regs;
return 1;
@ -395,8 +401,9 @@ aarch64_ext_ldst_reglist_r (const aarch64_operand *self ATTRIBUTE_UNUSED,
assert (info->reglist.num_regs >= 1 && info->reglist.num_regs <= 4);
/* Except when it is LD1R. */
if (info->reglist.num_regs == 1 && value == (aarch64_insn) 1)
info->reglist.num_regs = 2;
if (info->reglist.num_regs == 1 && value == (aarch64_insn)1) {
info->reglist.num_regs = 2;
}
return 1;
}
@ -443,9 +450,10 @@ aarch64_ext_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED,
info->qualifier = AARCH64_OPND_QLF_S_D;
/* Index encoded in "Q". */
info->reglist.index = QSsize >> 3;
if (extract_field (FLD_S, code, 0))
/* UND */
return 0;
if (extract_field (FLD_S, code, 0)) {
/* UND */
return 0;
}
}
break;
default:
@ -476,13 +484,15 @@ aarch64_ext_advsimd_imm_shift (const aarch64_operand *self ATTRIBUTE_UNUSED,
enum aarch64_insn_class iclass = inst->opcode->iclass;
immh = extract_field (FLD_immh, code, 0);
if (immh == 0)
return 0;
if (immh == 0) {
return 0;
}
imm = extract_fields (code, 0, 2, FLD_immh, FLD_immb);
pos = 4;
/* Get highest set bit in immh. */
while (--pos >= 0 && (immh & 0x8) == 0)
immh <<= 1;
while (--pos >= 0 && (immh & 0x8) == 0) {
immh <<= 1;
}
assert ((iclass == asimdshf || iclass == asisdshf)
&& (info->type == AARCH64_OPND_IMM_VLSR
@ -503,27 +513,28 @@ aarch64_ext_advsimd_imm_shift (const aarch64_operand *self ATTRIBUTE_UNUSED,
1xxx 1 2D */
info->qualifier =
get_vreg_qualifier_from_value ((pos << 1) | (int) Q);
}
else
info->qualifier = get_sreg_qualifier_from_value (pos);
} else {
info->qualifier = get_sreg_qualifier_from_value (pos);
}
if (info->type == AARCH64_OPND_IMM_VLSR)
/* immh <shift>
if (info->type == AARCH64_OPND_IMM_VLSR) {
/* immh <shift>
0000 SEE AdvSIMD modified immediate
0001 (16-UInt(immh:immb))
001x (32-UInt(immh:immb))
01xx (64-UInt(immh:immb))
1xxx (128-UInt(immh:immb)) */
info->imm.value = (16 << pos) - imm;
else
/* immh:immb
info->imm.value = (16 << pos) - imm;
} else {
/* immh:immb
immh <shift>
0000 SEE AdvSIMD modified immediate
0001 (UInt(immh:immb)-8)
001x (UInt(immh:immb)-16)
01xx (UInt(immh:immb)-32)
1xxx (UInt(immh:immb)-64) */
info->imm.value = imm - (8 << pos);
info->imm.value = imm - (8 << pos);
}
return 1;
}
@ -559,23 +570,28 @@ aarch64_ext_imm (const aarch64_operand *self, aarch64_opnd_info *info,
/* Maximum of two fields to extract. */
assert (self->fields[2] == FLD_NIL);
if (self->fields[1] == FLD_NIL)
imm = extract_field (self->fields[0], code, 0);
else
/* e.g. TBZ b5:b40. */
imm = extract_fields (code, 0, 2, self->fields[0], self->fields[1]);
if (self->fields[1] == FLD_NIL) {
imm = extract_field (self->fields[0], code, 0);
} else {
/* e.g. TBZ b5:b40. */
imm = extract_fields (code, 0, 2, self->fields[0], self->fields[1]);
}
if (info->type == AARCH64_OPND_FPIMM)
info->imm.is_fp = 1;
if (info->type == AARCH64_OPND_FPIMM) {
info->imm.is_fp = 1;
}
if (operand_need_sign_extension (self))
imm = sign_extend (imm, get_operand_fields_width (self) - 1);
if (operand_need_sign_extension (self)) {
imm = sign_extend (imm, get_operand_fields_width (self) - 1);
}
if (operand_need_shift_by_two (self))
imm <<= 2;
if (operand_need_shift_by_two (self)) {
imm <<= 2;
}
if (info->type == AARCH64_OPND_ADDR_ADRP)
imm <<= 12;
if (info->type == AARCH64_OPND_ADDR_ADRP) {
imm <<= 12;
}
info->imm.value = imm;
return 1;
@ -607,8 +623,9 @@ aarch64_ext_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED,
assert (info->idx == 1);
if (info->type == AARCH64_OPND_SIMD_FPIMM)
info->imm.is_fp = 1;
if (info->type == AARCH64_OPND_SIMD_FPIMM) {
info->imm.is_fp = 1;
}
/* a:b:c:d:e:f:g:h */
imm = extract_fields (code, 0, 2, FLD_abc, FLD_defgh);
@ -621,9 +638,11 @@ aarch64_ext_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED,
encoded in "a:b:c:d:e:f:g:h". */
int i;
unsigned abcdefgh = imm;
for (imm = 0ull, i = 0; i < 8; i++)
if (((abcdefgh >> i) & 0x1) != 0)
imm |= 0xffull << (8 * i);
for (imm = 0ull, i = 0; i < 8; i++) {
if (((abcdefgh >> i) & 0x1) != 0) {
imm |= 0xffull << (8 * i);
}
}
}
info->imm.value = imm;
@ -684,8 +703,9 @@ aarch64_ext_aimm (const aarch64_operand *self ATTRIBUTE_UNUSED,
info->shifter.kind = AARCH64_MOD_LSL;
/* shift */
value = extract_field (FLD_shift, code, 0);
if (value >= 2)
return 0;
if (value >= 2) {
return 0;
}
info->shifter.amount = value ? 12 : 0;
/* imm12 (unsigned) */
info->imm.value = extract_field (FLD_imm12, code, 0);
@ -716,8 +736,9 @@ aarch64_ext_limm (const aarch64_operand *self ATTRIBUTE_UNUSED,
R = (value >> 6) & 0x3f;
N = (value >> 12) & 0x1;
if (sf == 0 && N == 1)
return 0;
if (sf == 0 && N == 1) {
return 0;
}
/* The immediate value is S+1 bits to 1, left rotated by SIMDsize - R
(in other words, right rotated by R), then replicated. */
@ -739,17 +760,18 @@ aarch64_ext_limm (const aarch64_operand *self ATTRIBUTE_UNUSED,
R &= simd_size - 1;
}
/* NOTE: if S = simd_size - 1 we get 0xf..f which is rejected. */
if (S == simd_size - 1)
return 0;
/* S+1 consecutive bits to 1. */
/* NOTE: S can't be 63 due to detection above. */
imm = (1ull << (S + 1)) - 1;
/* Rotate to the left by simd_size - R. */
if (R != 0)
imm = ((imm << (simd_size - R)) & mask) | (imm >> R);
/* Replicate the value according to SIMD size. */
switch (simd_size)
{
if (S == simd_size - 1) {
return 0;
}
/* S+1 consecutive bits to 1. */
/* NOTE: S can't be 63 due to detection above. */
imm = (1ull << (S + 1)) - 1;
/* Rotate to the left by simd_size - R. */
if (R != 0) {
imm = ((imm << (simd_size - R)) & mask) | (imm >> R);
}
/* Replicate the value according to SIMD size. */
switch (simd_size) {
case 2: imm = (imm << 2) | imm;
case 4: imm = (imm << 4) | imm;
case 8: imm = (imm << 8) | imm;
@ -797,8 +819,9 @@ aarch64_ext_ft (const aarch64_operand *self ATTRIBUTE_UNUSED,
{
/* opc1:size */
value = extract_fields (code, 0, 2, FLD_opc1, FLD_ldst_size);
if (value > 0x4)
return 0;
if (value > 0x4) {
return 0;
}
info->qualifier = get_sreg_qualifier_from_value (value);
}
@ -836,8 +859,9 @@ aarch64_ext_addr_regoff (const aarch64_operand *self ATTRIBUTE_UNUSED,
aarch64_get_operand_modifier_from_value (value, TRUE /* extend_p */);
/* Fix-up the shifter kind; although the table-driven approach is
efficient, it is slightly inflexible, thus needing this fix-up. */
if (info->shifter.kind == AARCH64_MOD_UXTX)
info->shifter.kind = AARCH64_MOD_LSL;
if (info->shifter.kind == AARCH64_MOD_UXTX) {
info->shifter.kind = AARCH64_MOD_LSL;
}
/* S */
S = extract_field (FLD_S, code, 0);
if (S == 0)
@ -874,23 +898,21 @@ aarch64_ext_addr_simm (const aarch64_operand *self, aarch64_opnd_info *info,
/* simm (imm9 or imm7) */
imm = extract_field (self->fields[0], code, 0);
info->addr.offset.imm = sign_extend (imm, aarch64_fields[self->fields[0]].width - 1);
if (self->fields[0] == FLD_imm7)
/* scaled immediate in ld/st pair instructions. */
info->addr.offset.imm *= aarch64_get_qualifier_esize (info->qualifier);
if (self->fields[0] == FLD_imm7) {
/* scaled immediate in ld/st pair instructions. */
info->addr.offset.imm *= aarch64_get_qualifier_esize (info->qualifier);
}
/* qualifier */
if (inst->opcode->iclass == ldst_unscaled
|| inst->opcode->iclass == ldstnapair_offs
|| inst->opcode->iclass == ldstpair_off
|| inst->opcode->iclass == ldst_unpriv)
info->addr.writeback = 0;
else
{
/* pre/post- index */
info->addr.writeback = 1;
if (extract_field (self->fields[1], code, 0) == 1)
info->addr.preind = 1;
else
info->addr.postind = 1;
if (inst->opcode->iclass == ldst_unscaled || inst->opcode->iclass == ldstnapair_offs || inst->opcode->iclass == ldstpair_off || inst->opcode->iclass == ldst_unpriv) {
info->addr.writeback = 0;
} else {
/* pre/post- index */
info->addr.writeback = 1;
if (extract_field (self->fields[1], code, 0) == 1) {
info->addr.preind = 1;
} else {
info->addr.postind = 1;
}
}
return 1;
@ -929,18 +951,17 @@ aarch64_ext_simd_addr_post (const aarch64_operand *self ATTRIBUTE_UNUSED,
info->addr.offset.regno = extract_field (FLD_Rm, code, 0);
if (info->addr.offset.regno == 31)
{
if (inst->opcode->operands[0] == AARCH64_OPND_LVt_AL)
/* Special handling of loading single structure to all lane. */
info->addr.offset.imm = (is_ld1r ? 1
: inst->operands[0].reglist.num_regs)
* aarch64_get_qualifier_esize (inst->operands[0].qualifier);
else
info->addr.offset.imm = inst->operands[0].reglist.num_regs
* aarch64_get_qualifier_esize (inst->operands[0].qualifier)
* aarch64_get_qualifier_nelem (inst->operands[0].qualifier);
}
else
info->addr.offset.is_reg = 1;
if (inst->opcode->operands[0] == AARCH64_OPND_LVt_AL) {
/* Special handling of loading single structure to all lane. */
info->addr.offset.imm = (is_ld1r ? 1
: inst->operands[0].reglist.num_regs) *
aarch64_get_qualifier_esize (inst->operands[0].qualifier);
} else {
info->addr.offset.imm = inst->operands[0].reglist.num_regs * aarch64_get_qualifier_esize (inst->operands[0].qualifier) * aarch64_get_qualifier_nelem (inst->operands[0].qualifier);
}
} else {
info->addr.offset.is_reg = 1;
}
info->addr.writeback = 1;
return 1;
@ -981,9 +1002,11 @@ aarch64_ext_pstatefield (const aarch64_operand *self ATTRIBUTE_UNUSED,
int i;
/* op1:op2 */
info->pstatefield = extract_fields (code, 0, 2, FLD_op1, FLD_op2);
for (i = 0; aarch64_pstatefields[i].name != NULL; ++i)
if (aarch64_pstatefields[i].value == (aarch64_insn)info->pstatefield)
return 1;
for (i = 0; aarch64_pstatefields[i].name != NULL; ++i) {
if (aarch64_pstatefields[i].value == (aarch64_insn)info->pstatefield) {
return 1;
}
}
/* Reserved value in <pstatefield>. */
return 0;
}
@ -1012,18 +1035,18 @@ aarch64_ext_sysins_op (const aarch64_operand *self ATTRIBUTE_UNUSED,
default: assert (0); return 0;
}
for (i = 0; sysins_ops[i].template != NULL; ++i)
if (sysins_ops[i].value == value)
{
info->sysins_op = sysins_ops + i;
DEBUG_TRACE ("%s found value: %x, has_xt: %d, i: %d.",
info->sysins_op->template,
(unsigned)info->sysins_op->value,
info->sysins_op->has_xt, i);
return 1;
}
for (i = 0; sysins_ops[i].template != NULL; ++i) {
if (sysins_ops[i].value == value) {
info->sysins_op = sysins_ops + i;
DEBUG_TRACE ("%s found value: %x, has_xt: %d, i: %d.",
info->sysins_op->template,
(unsigned)info->sysins_op->value,
info->sysins_op->has_xt, i);
return 1;
}
}
return 0;
return 0;
}
/* Decode the memory barrier option operand for e.g. DMB <option>|#<imm>. */
@ -1077,10 +1100,9 @@ aarch64_ext_reg_extended (const aarch64_operand *self ATTRIBUTE_UNUSED,
/* Assume inst->operands[0].qualifier has been resolved. */
assert (inst->operands[0].qualifier != AARCH64_OPND_QLF_NIL);
info->qualifier = AARCH64_OPND_QLF_W;
if (inst->operands[0].qualifier == AARCH64_OPND_QLF_X
&& (info->shifter.kind == AARCH64_MOD_UXTX
|| info->shifter.kind == AARCH64_MOD_SXTX))
info->qualifier = AARCH64_OPND_QLF_X;
if (inst->operands[0].qualifier == AARCH64_OPND_QLF_X && (info->shifter.kind == AARCH64_MOD_UXTX || info->shifter.kind == AARCH64_MOD_SXTX)) {
info->qualifier = AARCH64_OPND_QLF_X;
}
return 1;
}
@ -1101,11 +1123,11 @@ aarch64_ext_reg_shifted (const aarch64_operand *self ATTRIBUTE_UNUSED,
value = extract_field (FLD_shift, code, 0);
info->shifter.kind =
aarch64_get_operand_modifier_from_value (value, FALSE /* extend_p */);
if (info->shifter.kind == AARCH64_MOD_ROR
&& inst->opcode->iclass != log_shift)
/* ROR is not available for the shifted register operand in arithmetic
if (info->shifter.kind == AARCH64_MOD_ROR && inst->opcode->iclass != log_shift) {
/* ROR is not available for the shifted register operand in arithmetic
instructions. */
return 0;
return 0;
}
/* imm6 */
info->shifter.amount = extract_field (FLD_imm6, code, 0);
@ -1146,11 +1168,13 @@ get_qualifier_from_partial_encoding (aarch64_insn value,
for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i)
{
aarch64_insn standard_value;
if (candidates[i] == AARCH64_OPND_QLF_NIL)
break;
if (candidates[i] == AARCH64_OPND_QLF_NIL) {
break;
}
standard_value = aarch64_get_qualifier_standard_value (candidates[i]);
if ((standard_value & mask) == (value & mask))
return candidates[i];
if ((standard_value & mask) == (value & mask)) {
return candidates[i];
}
}
return AARCH64_OPND_QLF_NIL;
}
@ -1165,9 +1189,11 @@ get_operand_possible_qualifiers (int idx,
enum aarch64_opnd_qualifier *qualifiers)
{
int i;
for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i)
if ((qualifiers[i] = list[i][idx]) == AARCH64_OPND_QLF_NIL)
break;
for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i) {
if ((qualifiers[i] = list[i][idx]) == AARCH64_OPND_QLF_NIL) {
break;
}
}
}
/* Decode the size Q field for e.g. SHADD.
@ -1185,13 +1211,11 @@ decode_sizeq (aarch64_inst *inst)
enum aarch64_field_kind fld_sz;
enum aarch64_opnd_qualifier candidates[AARCH64_MAX_QLF_SEQ_NUM];
if (inst->opcode->iclass == asisdlse
|| inst->opcode->iclass == asisdlsep
|| inst->opcode->iclass == asisdlso
|| inst->opcode->iclass == asisdlsop)
fld_sz = FLD_vldst_size;
else
fld_sz = FLD_size;
if (inst->opcode->iclass == asisdlse || inst->opcode->iclass == asisdlsep || inst->opcode->iclass == asisdlso || inst->opcode->iclass == asisdlsop) {
fld_sz = FLD_vldst_size;
} else {
fld_sz = FLD_size;
}
code = inst->value;
value = extract_fields (code, inst->opcode->mask, 2, fld_sz, FLD_Q);
@ -1230,8 +1254,9 @@ decode_sizeq (aarch64_inst *inst)
qualifier = get_qualifier_from_partial_encoding (value, candidates, mask);
if (qualifier == AARCH64_OPND_QLF_NIL)
return 0;
if (qualifier == AARCH64_OPND_QLF_NIL) {
return 0;
}
inst->operands[idx].qualifier = qualifier;
return 1;
@ -1279,8 +1304,9 @@ decode_asisd_fcvtxn (aarch64_inst *inst)
{
aarch64_field field = {0, 0};
gen_sub_field (FLD_size, 0, 1, &field);
if (!extract_field_2 (&field, inst->value, 0))
return 0;
if (!extract_field_2 (&field, inst->value, 0)) {
return 0;
}
inst->operands[0].qualifier = AARCH64_OPND_QLF_S_S;
return 1;
}
@ -1352,25 +1378,24 @@ do_special_decoding (aarch64_inst *inst)
idx = select_operand_for_sf_field_coding (inst->opcode);
value = extract_field (FLD_sf, inst->value, 0);
inst->operands[idx].qualifier = get_greg_qualifier_from_value (value);
if ((inst->opcode->flags & F_N)
&& extract_field (FLD_N, inst->value, 0) != value)
return 0;
if ((inst->opcode->flags & F_N) && extract_field (FLD_N, inst->value, 0) != value) {
return 0;
}
}
/* size:Q fields. */
if (inst->opcode->flags & F_SIZEQ)
return decode_sizeq (inst);
if (inst->opcode->flags & F_SIZEQ) {
return decode_sizeq (inst);
}
if (inst->opcode->flags & F_FPTYPE)
{
idx = select_operand_for_fptype_field_coding (inst->opcode);
value = extract_field (FLD_type, inst->value, 0);
switch (value)
{
case 0: inst->operands[idx].qualifier = AARCH64_OPND_QLF_S_S; break;
case 1: inst->operands[idx].qualifier = AARCH64_OPND_QLF_S_D; break;
case 3: inst->operands[idx].qualifier = AARCH64_OPND_QLF_S_H; break;
default: return 0;
}
if (inst->opcode->flags & F_FPTYPE) {
idx = select_operand_for_fptype_field_coding (inst->opcode);
value = extract_field (FLD_type, inst->value, 0);
switch (value) {
case 0: inst->operands[idx].qualifier = AARCH64_OPND_QLF_S_S; break;
case 1: inst->operands[idx].qualifier = AARCH64_OPND_QLF_S_D; break;
case 3: inst->operands[idx].qualifier = AARCH64_OPND_QLF_S_H; break;
default: return 0;
}
}
if (inst->opcode->flags & F_SSIZE)
@ -1384,14 +1409,12 @@ do_special_decoding (aarch64_inst *inst)
mask = extract_field (FLD_size, ~inst->opcode->mask, 0);
/* For most related instruciton, the 'size' field is fully available for
operand encoding. */
if (mask == 0x3)
inst->operands[idx].qualifier = get_sreg_qualifier_from_value (value);
else
{
get_operand_possible_qualifiers (idx, inst->opcode->qualifiers_list,
candidates);
inst->operands[idx].qualifier
= get_qualifier_from_partial_encoding (value, candidates, mask);
if (mask == 0x3) {
inst->operands[idx].qualifier = get_sreg_qualifier_from_value (value);
} else {
get_operand_possible_qualifiers (idx, inst->opcode->qualifiers_list,
candidates);
inst->operands[idx].qualifier = get_qualifier_from_partial_encoding (value, candidates, mask);
}
}
@ -1413,10 +1436,12 @@ do_special_decoding (aarch64_inst *inst)
1000 0 reserved
1000 1 2d */
val = extract_field (FLD_imm5, inst->value, 0);
while ((val & 0x1) == 0 && ++num <= 3)
val >>= 1;
if (num > 3)
return 0;
while ((val & 0x1) == 0 && ++num <= 3) {
val >>= 1;
}
if (num > 3) {
return 0;
}
Q = (unsigned) extract_field (FLD_Q, inst->value, inst->opcode->mask);
inst->operands[0].qualifier =
get_vreg_qualifier_from_value ((num << 1) | Q);
@ -1452,10 +1477,11 @@ do_special_decoding (aarch64_inst *inst)
}
/* Miscellaneous decoding; done as the last step. */
if (inst->opcode->flags & F_MISC)
return do_misc_decoding (inst);
if (inst->opcode->flags & F_MISC) {
return do_misc_decoding (inst);
}
return 1;
return 1;
}
/* Converters converting a real opcode instruction to its alias form. */
@ -1652,8 +1678,9 @@ convert_movewide_to_mov (aarch64_inst *inst)
{
uint64_t value = inst->operands[1].imm.value;
/* MOVZ/MOVN #0 have a shift amount other than LSL #0. */
if (value == 0 && inst->operands[1].shifter.amount != 0)
return 0;
if (value == 0 && inst->operands[1].shifter.amount != 0) {
return 0;
}
inst->operands[1].type = AARCH64_OPND_IMM_MOV;
inst->operands[1].shifter.kind = AARCH64_MOD_NONE;
value <<= inst->operands[1].shifter.amount;
@ -1664,8 +1691,9 @@ convert_movewide_to_mov (aarch64_inst *inst)
int is32 = inst->operands[0].qualifier == AARCH64_OPND_QLF_W;
value = ~value;
/* A MOVN has an immediate that could be encoded by MOVZ. */
if (aarch64_wide_constant_p (value, is32, NULL) == TRUE)
return 0;
if (aarch64_wide_constant_p (value, is32, NULL) == TRUE) {
return 0;
}
}
inst->operands[1].imm.value = value;
inst->operands[1].shifter.amount = 0;
@ -1696,10 +1724,9 @@ convert_movebitmask_to_mov (aarch64_inst *inst)
value = inst->operands[1].imm.value;
/* ORR has an immediate that could be generated by a MOVZ or MOVN
instruction. */
if (inst->operands[0].reg.regno != 0x1f
&& (aarch64_wide_constant_p (value, is32, NULL) == TRUE
|| aarch64_wide_constant_p (~value, is32, NULL) == TRUE))
return 0;
if (inst->operands[0].reg.regno != 0x1f && (aarch64_wide_constant_p (value, is32, NULL) == TRUE || aarch64_wide_constant_p (~value, is32, NULL) == TRUE)) {
return 0;
}
inst->operands[2].type = AARCH64_OPND_NIL;
return 1;
@ -1817,8 +1844,9 @@ determine_disassembling_preference (struct aarch64_inst *inst)
opcode = inst->opcode;
/* This opcode does not have an alias, so use itself. */
if (opcode_has_alias (opcode) == FALSE)
return;
if (opcode_has_alias (opcode) == FALSE) {
return;
}
alias = aarch64_find_alias_opcode (opcode);
assert (alias);
@ -1928,10 +1956,11 @@ aarch64_opcode_decode (const aarch64_opcode *opcode, const aarch64_insn code,
/* Assign operand codes and indexes. */
for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
{
if (opcode->operands[i] == AARCH64_OPND_NIL)
break;
inst->operands[i].type = opcode->operands[i];
inst->operands[i].idx = i;
if (opcode->operands[i] == AARCH64_OPND_NIL) {
break;
}
inst->operands[i].type = opcode->operands[i];
inst->operands[i].idx = i;
}
/* Call the opcode decoder indicated by flags. */
@ -1947,8 +1976,9 @@ aarch64_opcode_decode (const aarch64_opcode *opcode, const aarch64_insn code,
const aarch64_operand *opnd;
enum aarch64_opnd type;
type = opcode->operands[i];
if (type == AARCH64_OPND_NIL)
break;
if (type == AARCH64_OPND_NIL) {
break;
}
opnd = &aarch64_operands[type];
if (operand_has_extractor (opnd)
&& (! aarch64_extract_operand (opnd, &inst->operands[i], code, inst)))
@ -1966,8 +1996,9 @@ aarch64_opcode_decode (const aarch64_opcode *opcode, const aarch64_insn code,
instruction. Before the return, check if the instruction has any
alias and should be disassembled in the form of its alias instead.
If the answer is yes, *INST will be updated. */
if (!noaliases_p)
determine_disassembling_preference (inst);
if (!noaliases_p) {
determine_disassembling_preference (inst);
}
DEBUG_TRACE ("SUCCESS");
return 1;
}
@ -1996,8 +2027,9 @@ user_friendly_fixup (aarch64_inst *inst)
the register, which may be written and should be disassembled as Wn if
uimm is less than 32. Limited to a branch offset range of +/- 32KiB.
*/
if (inst->operands[1].imm.value < 32)
inst->operands[0].qualifier = AARCH64_OPND_QLF_W;
if (inst->operands[1].imm.value < 32) {
inst->operands[0].qualifier = AARCH64_OPND_QLF_W;
}
break;
default: break;
}
@ -2034,8 +2066,9 @@ disas_aarch64_insn (uint64_t pc ATTRIBUTE_UNUSED, uint32_t insn,
{
/* But only one opcode can be decoded successfully for, as the
decoding routine will check the constraint carefully. */
if (aarch64_opcode_decode (opcode, insn, inst, no_aliases) == 1)
return ERR_OK;
if (aarch64_opcode_decode (opcode, insn, inst, no_aliases) == 1) {
return ERR_OK;
}
opcode = aarch64_find_next_opcode (opcode);
}
@ -2057,24 +2090,26 @@ print_operands (bfd_vma pc, const aarch64_opcode *opcode,
operand.
The two operand code should be the same in all cases, apart from
when the operand can be optional. */
if (opcode->operands[i] == AARCH64_OPND_NIL
|| opnds[i].type == AARCH64_OPND_NIL)
break;
if (opcode->operands[i] == AARCH64_OPND_NIL || opnds[i].type == AARCH64_OPND_NIL) {
break;
}
/* Generate the operand string in STR. */
aarch64_print_operand (str, SIZE, pc, opcode, opnds, i, &pcrel_p,
&info->target);
/* Print the delimiter (taking account of omitted operand(s)). */
if (str[0] != '\0')
(*info->fprintf_func) (info->stream, "%s",
num_printed++ == 0 ? " " : ", ");
if (str[0] != '\0') {
(*info->fprintf_func) (info->stream, "%s",
num_printed++ == 0 ? " " : ", ");
}
/* Print the operand. */
if (pcrel_p)
(*info->print_address_func) (info->target, info);
else
(*info->fprintf_func) (info->stream, "%s", str);
if (pcrel_p) {
(*info->print_address_func) (info->target, info);
} else {
(*info->fprintf_func) (info->stream, "%s", str);
}
}
}
@ -2098,9 +2133,9 @@ print_mnemonic_name (const aarch64_inst *inst, struct disassemble_info *info)
strncpy (name, inst->opcode->name, len);
name [len] = '\0';
(*info->fprintf_func) (info->stream, "%s.%s", name, inst->cond->names[0]);
}
else
(*info->fprintf_func) (info->stream, "%s", inst->opcode->name);
} else {
(*info->fprintf_func) (info->stream, "%s", inst->opcode->name);
}
}
/* Print the instruction according to *INST. */
@ -2139,13 +2174,14 @@ print_insn_aarch64_word (bfd_vma pc,
info->target = 0;
info->target2 = 0;
if (info->flags & INSN_HAS_RELOC)
/* If the instruction has a reloc associated with it, then
if (info->flags & INSN_HAS_RELOC) {
/* If the instruction has a reloc associated with it, then
the offset field in the instruction will actually be the
addend for the reloc. (If we are using REL type relocs).
In such cases, we can ignore the pc when computing
addresses, since the addend is not currently pc-relative. */
pc = 0;
pc = 0;
}
ret = disas_aarch64_insn (pc, word, &inst);
@ -2185,8 +2221,9 @@ aarch64_symbol_is_valid (asymbol * sym,
{
const char * name;
if (!sym)
return FALSE;
if (!sym) {
return FALSE;
}
name = bfd_asymbol_name (sym);
@ -2292,21 +2329,24 @@ print_insn_aarch64 (bfd_vma pc,
bfd_vma addr;
int n;
if (pc <= last_mapping_addr)
last_mapping_sym = -1;
if (pc <= last_mapping_addr) {
last_mapping_sym = -1;
}
/* Start scanning at the start of the function, or wherever
we finished last time. */
n = info->symtab_pos + 1;
if (n < last_mapping_sym)
n = last_mapping_sym;
if (n < last_mapping_sym) {
n = last_mapping_sym;
}
/* Scan up to the location being disassembled. */
for (; n < info->symtab_size; n++)
{
addr = bfd_asymbol_value (info->symtab[n]);
if (addr > pc)
break;
if (addr > pc) {
break;
}
if ((!info->section
|| info->section == info->symtab[n]->section)
&& get_sym_code_type (info, n, &type))
@ -2319,8 +2359,9 @@ print_insn_aarch64 (bfd_vma pc,
if (!found)
{
n = info->symtab_pos;
if (n < last_mapping_sym)
n = last_mapping_sym;
if (n < last_mapping_sym) {
n = last_mapping_sym;
}
/* No mapping symbol found at this address. Look backwards
for a preceding one. */
@ -2350,16 +2391,18 @@ print_insn_aarch64 (bfd_vma pc,
addr = bfd_asymbol_value (info->symtab[n]);
if (addr > pc)
{
if (addr - pc < size)
size = addr - pc;
break;
if (addr - pc < size) {
size = addr - pc;
}
break;
}
}
/* If the next symbol is after three bytes, we need to
print only part of the data, so that we can use either
.byte or .short. */
if (size == 3)
size = (pc & 1) ? 1 : 2;
if (size == 3) {
size = (pc & 1) ? 1 : 2;
}
}
}

746
libr/asm/arch/arm/aarch64/aarch64-opc.c
View File

File diff suppressed because it is too large Load Diff

346
libr/asm/arch/arm/armass.c
View File

@ -47,8 +47,9 @@ enum {
};
static int strcmpnull(const char *a, const char *b) {
if (!a || !b)
if (!a || !b) {
return -1;
}
return strcmp (a, b);
}
@ -601,13 +602,17 @@ static char *getrange(char *s) {
p = s+1;
*p=0;
}
if (*s == '[' || *s == ']')
memmove (s, s+1, strlen (s+1)+1);
if (*s == '}')
if (*s == '[' || *s == ']') {
memmove (s, s + 1, strlen (s + 1) + 1);
}
if (*s == '}') {
*s = 0;
}
s++;
}
while (p && *p == ' ') p++;
while (p && *p == ' ') {
p++;
}
return p;
}
@ -656,8 +661,12 @@ static st32 getlistmask(char *input) {
}
otemp = temp;
while (*input != '\0') {
for (; *input == ' '; input++);
for (i = 0; input[i] != ',' && input[i] != '\0'; i++);
for (; *input == ' '; input++) {
;
}
for (i = 0; input[i] != ',' && input[i] != '\0'; i++) {
;
}
strncpy (temp, input, i);
temp[i] = 0;
@ -666,7 +675,9 @@ static st32 getlistmask(char *input) {
input++;
}
for (i = 0; temp[i] != '-' && temp[i] != '\0'; i++);
for (i = 0; temp[i] != '-' && temp[i] != '\0'; i++) {
;
}
if (i == strlen (temp)) {
tempres = getreg (temp);
if (tempres == -1 || tempres > 15) {
@ -966,7 +977,9 @@ void collect_list(char *input[]) {
int conc = 0;
int start, end = 0;
int arrsz;
for (arrsz = 1; input[arrsz] != NULL; arrsz++);
for (arrsz = 1; input[arrsz] != NULL; arrsz++) {
;
}
for (i = 0; input[i]; i++) {
if (conc) {
@ -1112,7 +1125,9 @@ static ut32 getshift(const char *str) {
// i|=1; // use reg
i |= (1 << 4); // bitshift
i |= shift << 4; // set shift mode
if (shift == 6) i |= (1 << 20);
if (shift == 6) {
i |= (1 << 20);
}
} else {
char *bracket = strchr (arg, ']');
if (bracket) {
@ -1120,7 +1135,9 @@ static ut32 getshift(const char *str) {
}
// ensure only the bottom 5 bits are used
i &= 0x1f;
if (!i) i = 32;
if (!i) {
i = 32;
}
i = (i * 8);
i |= shift; // lsl, ror, ...
i = i << 4;
@ -1133,8 +1150,9 @@ static ut32 getshift(const char *str) {
static void arm_opcode_parse(ArmOpcode *ao, const char *str) {
int i;
memset (ao, 0, sizeof (ArmOpcode));
if (strlen (str)+1>=sizeof (ao->op))
if (strlen (str) + 1 >= sizeof (ao->op)) {
return;
}
strncpy (ao->op, str, sizeof (ao->op)-1);
strcpy (ao->opstr, ao->op);
ao->a[0] = strchr (ao->op, ' ');
@ -1142,7 +1160,9 @@ static void arm_opcode_parse(ArmOpcode *ao, const char *str) {
if (ao->a[i]) {
*ao->a[i] = 0;
ao->a[i+1] = strchr (++ao->a[i], ',');
} else break;
} else {
break;
}
}
if (ao->a[i]) {
*ao->a[i] = 0;
@ -2790,9 +2810,10 @@ static int thumb_assemble(ArmOpcode *ao, ut64 off, const char *str) {
if (ldrsel == 0) {
ao->a[1][strlen (ao->a[1]) - 1] = '\0';
ao->a[2] = "0]";
} else
} else {
return -1;
}
}
}
// intentional fallthrough
case THUMB_REG_BRACKREG_CONSTBRACK: {
st32 num = getnummemend (ao->a[2]);
@ -6041,7 +6062,9 @@ static int findyz(int x, int *y, int *z) {
for (i = 0;i < 0xff; i++) {
for (j = 0;j < 0xf;j++) {
int v = i << j;
if (v > x) continue;
if (v > x) {
continue;
}
if (v == x) {
*y = i;
*z = 16 - (j / 2);
@ -6061,160 +6084,164 @@ static int arm_assemble(ArmOpcode *ao, ut64 off, const char *str) {
if (!strncmp (ao->op, ops[i].name, strlen (ops[i].name))) {
ao->o = ops[i].code;
arm_opcode_cond (ao, strlen(ops[i].name));
if (ao->a[0] || ops[i].type == TYPE_BKP)
switch (ops[i].type) {
case TYPE_MEM:
if (!strncmp (ops[i].name, "strex", 5)) {
rex = 1;
}
if (!strcmp (ops[i].name, "str") || !strcmp (ops[i].name, "ldr")) {
if (!ao->a[2]) {
ao->a[2] = "0";
if (ao->a[0] || ops[i].type == TYPE_BKP) {
switch (ops[i].type) {
case TYPE_MEM:
if (!strncmp (ops[i].name, "strex", 5)) {
rex = 1;
}
}
getrange (ao->a[0]);
getrange (ao->a[1]);
getrange (ao->a[2]);
if (ao->a[0] && ao->a[1]) {
char rn[8];
strncpy (rn, ao->a[1], 7);
int r0 = getreg (ao->a[0]);
int r1 = getreg (ao->a[1]);
if ( (r0 < 0 || r0 > 15) || (r1 > 15 || r1 < 0) ) {
return 0;
if (!strcmp (ops[i].name, "str") || !strcmp (ops[i].name, "ldr")) {
if (!ao->a[2]) {
ao->a[2] = "0";
}
}
ao->o |= r0 << 20;
if (!strcmp (ops[i].name, "strd")) {
r1 = getreg (ao->a[2]);
if (r1 == -1) {
getrange (ao->a[0]);
getrange (ao->a[1]);
getrange (ao->a[2]);
if (ao->a[0] && ao->a[1]) {
char rn[8];
strncpy (rn, ao->a[1], 7);
int r0 = getreg (ao->a[0]);
int r1 = getreg (ao->a[1]);
if ((r0 < 0 || r0 > 15) || (r1 > 15 || r1 < 0)) {
return 0;
}
ao->o |= r0 << 20;
if (!strcmp (ops[i].name, "strd")) {
r1 = getreg (ao->a[2]);
if (r1 == -1) {
break;
}
ao->o |= r1 << 8;
if (ao->a[3]) {
char *bracket = strchr (ao->a[3], ']');
if (bracket) {
*bracket = '\0';
}
int num = getnum (ao->a[3]);
ao->o |= (num & 0x0f) << 24;
ao->o |= ((num >> 4) & 0x0f) << 16;
}
break;
}
ao->o |= r1 << 8;
if (ao->a[3]) {
char *bracket = strchr (ao->a[3], ']');
if (bracket) {
*bracket = '\0';
}
int num = getnum (ao->a[3]);
ao->o |= (num & 0x0f) << 24;
ao->o |= ((num >> 4) & 0x0f) << 16;
}
break;
}
if (!strcmp (ops[i].name, "strh")) {
ao->o |= r1 << 8;
if (ao->a[2]) {
reg = getreg (ao->a[2]);
if (reg != -1) {
ao->o |= reg << 24;
if (!strcmp (ops[i].name, "strh")) {
ao->o |= r1 << 8;
if (ao->a[2]) {
reg = getreg (ao->a[2]);
if (reg != -1) {
ao->o |= reg << 24;
} else {
ao->o |= 1 << 14;
ao->o |= getnum (ao->a[2]) << 24;
}
} else {
ao->o |= 1 << 14;
ao->o |= getnum (ao->a[2]) << 24;
}
break;
}
if (rex) {
ao->o |= r1 << 24;
} else {
ao->o |= 1 << 14;
ao->o |= r1 << 8; // delta
}
break;
}
if (rex) {
ao->o |= r1 << 24;
} else {
ao->o |= r1 << 8; // delta
}
} else {
return 0;
}
ret = getreg (ao->a[2]);
if (ret != -1) {
if (rex) {
ao->o |= 1;
ao->o |= (ret & 0x0f) << 8;
} else {
ao->o |= (strstr (str,"],")) ? 6 : 7;
ao->o |= (ret & 0x0f) << 24;
}
if (ao->a[3]) {
shift = getshift (ao->a[3]);
low = shift & 0xFF;
high = shift & 0xFF00;
ao->o |= low << 24;
ao->o |= high << 8;
}
} else {
int num = getnum (ao->a[2]) & 0xfff;
if (err) {
break;
}
if (rex) {
ao->o |= 1;
} else {
ao->o |= (strstr (str, "],")) ? 4 : 5;
}
ao->o |= 1;
ao->o |= (num & 0xff) << 24;
ao->o |= ((num >> 8) & 0xf) << 16;
}
break;
case TYPE_IMM:
if (*ao->a[0] ++== '{') {
for (j = 0; j < 16; j++) {
if (ao->a[j] && *ao->a[j]) {
getrange (ao->a[j]); // XXX filter regname string
reg = getreg (ao->a[j]);
if (reg != -1) {
if (reg < 8)
ao->o |= 1 << (24 + reg);
else
ao->o |= 1 << (8 + reg);
}
}
}
} else ao->o |= getnum (ao->a[0]) << 24; // ???
break;
case TYPE_BRA:
if ((ret = getreg (ao->a[0])) == -1) {
// TODO: control if branch out of range
ret = (getnum (ao->a[0]) - (int)ao->off - 8) / 4;
if (ret >= 0x00800000 || ret < (int)0xff800000) {
eprintf("Branch into out of range\n");
return 0;
}
ao->o |= ((ret >> 16) & 0xff) << 8;
ao->o |= ((ret >> 8) & 0xff) << 16;
ao->o |= ((ret) & 0xff) << 24;
} else {
eprintf("This branch does not accept reg as arg\n");
return 0;
}
break;
case TYPE_BKP:
ao->o |= 0x70 << 24;
if (ao->a[0]) {
int n = getnum (ao->a[0]);
ao->o |= ((n & 0xf) << 24);
ao->o |= (((n >> 4) & 0xff) << 16);
}
break;
case TYPE_BRR:
if ((ret = getreg (ao->a[0])) == -1) {
ut32 dst = getnum (ao->a[0]);
dst -= (ao->off + 8);
if (dst & 0x2) {
ao->o = 0xfb;
ret = getreg (ao->a[2]);
if (ret != -1) {
if (rex) {
ao->o |= 1;
ao->o |= (ret & 0x0f) << 8;
} else {
ao->o |= (strstr (str, "],")) ? 6 : 7;
ao->o |= (ret & 0x0f) << 24;
}
if (ao->a[3]) {
shift = getshift (ao->a[3]);
low = shift & 0xFF;
high = shift & 0xFF00;
ao->o |= low << 24;
ao->o |= high << 8;
}
} else {
ao->o = 0xfa;
int num = getnum (ao->a[2]) & 0xfff;
if (err) {
break;
}
if (rex) {
ao->o |= 1;
} else {
ao->o |= (strstr (str, "],")) ? 4 : 5;
}
ao->o |= 1;
ao->o |= (num & 0xff) << 24;
ao->o |= ((num >> 8) & 0xf) << 16;
}
dst /= 4;
ao->o |= ((dst >> 16) & 0xff) << 8;
ao->o |= ((dst >> 8) & 0xff) << 16;
ao->o |= ((dst) & 0xff) << 24;
return 4;
} else ao->o |= (getreg (ao->a[0]) << 24);
break;
case TYPE_HLT:
{
break;
case TYPE_IMM:
if (*ao->a[0]++ == '{') {
for (j = 0; j < 16; j++) {
if (ao->a[j] && *ao->a[j]) {
getrange (ao->a[j]); // XXX filter regname string
reg = getreg (ao->a[j]);
if (reg != -1) {
if (reg < 8) {
ao->o |= 1 << (24 + reg);
} else {
ao->o |= 1 << (8 + reg);
}
}
}
}
} else {
ao->o |= getnum (ao->a[0]) << 24; // ???
}
break;
case TYPE_BRA:
if ((ret = getreg (ao->a[0])) == -1) {
// TODO: control if branch out of range
ret = (getnum (ao->a[0]) - (int)ao->off - 8) / 4;
if (ret >= 0x00800000 || ret < (int)0xff800000) {
eprintf ("Branch into out of range\n");
return 0;
}
ao->o |= ((ret >> 16) & 0xff) << 8;
ao->o |= ((ret >> 8) & 0xff) << 16;
ao->o |= ((ret)&0xff) << 24;
} else {
eprintf ("This branch does not accept reg as arg\n");
return 0;
}
break;
case TYPE_BKP:
ao->o |= 0x70 << 24;
if (ao->a[0]) {
int n = getnum (ao->a[0]);
ao->o |= ((n & 0xf) << 24);
ao->o |= (((n >> 4) & 0xff) << 16);
}
break;
case TYPE_BRR:
if ((ret = getreg (ao->a[0])) == -1) {
ut32 dst = getnum (ao->a[0]);
dst -= (ao->off + 8);
if (dst & 0x2) {
ao->o = 0xfb;
} else {
ao->o = 0xfa;
}
dst /= 4;
ao->o |= ((dst >> 16) & 0xff) << 8;
ao->o |= ((dst >> 8) & 0xff) << 16;
ao->o |= ((dst)&0xff) << 24;
return 4;
} else {
ao->o |= (getreg (ao->a[0]) << 24);
}
break;
case TYPE_HLT: {
ut32 o = 0, n = getnum (ao->a[0]);
o |= ((n >> 12) & 0xf) << 8;
o |= ((n >> 8) & 0xf) << 20;
@ -6274,9 +6301,10 @@ static int arm_assemble(ArmOpcode *ao, ut64 off, const char *str) {
return 0;
}
}
if (0xff == ((ao->o >> 16) & 0xff))
if (0xff == ((ao->o >> 16) & 0xff)) {
return 0;
}
}
break;
case TYPE_MOV:
if (!strcmpnull (ao->op, "movs")) {
@ -6382,8 +6410,9 @@ static int arm_assemble(ArmOpcode *ao, ut64 off, const char *str) {
} else {
ao->o |= (a << 8);
ao->o |= (b << 24);
if (ao->a[2])
if (ao->a[2]) {
ao->o |= getshift (ao->a[2]);
}
}
if (ao->a[2]) {
int n = getnum (ao->a[2]);
@ -6504,6 +6533,7 @@ static int arm_assemble(ArmOpcode *ao, ut64 off, const char *str) {
break;
}
}
return 1;
}
}

3457
libr/asm/arch/arm/gnu/arm-dis.c
View File

File diff suppressed because it is too large Load Diff

182
libr/asm/arch/arm/gnu/floatformat.c
View File

@ -182,10 +182,11 @@ floatformat_i387_ext_is_valid (const struct floatformat *fmt, const void *from)
int_bit = get_field (ufrom, fmt->byteorder, fmt->totalsize,
fmt->man_start, 1);
if ((exponent == 0) != (int_bit == 0))
return 0;
else
return 1;
if ((exponent == 0) != (int_bit == 0)) {
return 0;
} else {
return 1;
}
}
const struct floatformat floatformat_i387_ext =
@ -297,21 +298,24 @@ floatformat_ibm_long_double_is_valid (const struct floatformat *fmt,
bot_exp = get_field (ufrom + 8, hfmt->byteorder, hfmt->totalsize,
hfmt->exp_start, hfmt->exp_len);
if ((unsigned long) top_exp == hfmt->exp_nan)
top_nan = mant_bits_set (hfmt, ufrom);
if ((unsigned long)top_exp == hfmt->exp_nan) {
top_nan = mant_bits_set (hfmt, ufrom);
}
/* A NaN is valid with any low part. */
if (top_nan)
return 1;
if (top_nan) {
return 1;
}
/* An infinity, zero or denormal requires low part 0 (positive or
negative). */
if ((unsigned long) top_exp == hfmt->exp_nan || top_exp == 0)
{
if (bot_exp != 0)
return 0;
if (bot_exp != 0) {
return 0;
}
return !mant_bits_set (hfmt, ufrom + 8);
return !mant_bits_set (hfmt, ufrom + 8);
}
/* The top part is now a finite normal value. The long double value
@ -320,42 +324,46 @@ floatformat_ibm_long_double_is_valid (const struct floatformat *fmt,
the bottom part must be <= 0.5ulp of the top part in absolute
value, and if it is < 0.5ulp then the long double is definitely
valid. */
if (bot_exp < top_exp - 53)
return 1;
if (bot_exp > top_exp - 53 && bot_exp != 0)
return 0;
if (bot_exp == 0)
{
/* The bottom part is 0 or denormal. Determine which, and if
if (bot_exp < top_exp - 53) {
return 1;
}
if (bot_exp > top_exp - 53 && bot_exp != 0) {
return 0;
}
if (bot_exp == 0) {
/* The bottom part is 0 or denormal. Determine which, and if
denormal the first two set bits. */
int first_bit = -1, second_bit = -1, cur_bit;
for (cur_bit = 0; (unsigned int) cur_bit < hfmt->man_len; cur_bit++)
if (get_field (ufrom + 8, hfmt->byteorder, hfmt->totalsize,
hfmt->man_start + cur_bit, 1))
{
if (first_bit == -1)
first_bit = cur_bit;
else
{
second_bit = cur_bit;
break;
}
}
/* Bottom part 0 is OK. */
if (first_bit == -1)
return 1;
/* The real exponent of the bottom part is -first_bit. */
if (-first_bit < top_exp - 53)
return 1;
if (-first_bit > top_exp - 53)
return 0;
/* The bottom part is at least 0.5ulp of the top part. For this
int first_bit = -1, second_bit = -1, cur_bit;
for (cur_bit = 0; (unsigned int)cur_bit < hfmt->man_len; cur_bit++) {
if (get_field (ufrom + 8, hfmt->byteorder, hfmt->totalsize,
hfmt->man_start + cur_bit, 1)) {
if (first_bit == -1) {
first_bit = cur_bit;
} else {
second_bit = cur_bit;
break;
}
}
}
/* Bottom part 0 is OK. */
if (first_bit == -1) {
return 1;
}
/* The real exponent of the bottom part is -first_bit. */
if (-first_bit < top_exp - 53) {
return 1;
}
if (-first_bit > top_exp - 53) {
return 0;
}
/* The bottom part is at least 0.5ulp of the top part. For this
to be OK, the bottom part must be exactly 0.5ulp (i.e. no
more bits set) and the top part must have last bit 0. */
if (second_bit != -1)
return 0;
return !get_field (ufrom, hfmt->byteorder, hfmt->totalsize,
hfmt->man_start + hfmt->man_len - 1, 1);
if (second_bit != -1) {
return 0;
}
return !get_field (ufrom, hfmt->byteorder, hfmt->totalsize,
hfmt->man_start + hfmt->man_len - 1, 1);
}
else
{
@ -363,8 +371,9 @@ floatformat_ibm_long_double_is_valid (const struct floatformat *fmt,
to be OK, it must be exactly 0.5ulp (i.e. no explicit bits
set) and the top part must have last bit 0. */
if (get_field (ufrom, hfmt->byteorder, hfmt->totalsize,
hfmt->man_start + hfmt->man_len - 1, 1))
return 0;
hfmt->man_start + hfmt->man_len - 1, 1)) {
return 0;
}
return !mant_bits_set (hfmt, ufrom + 8);
}
}
@ -407,8 +416,9 @@ mant_bits_set (const struct floatformat *fmt, const unsigned char *ufrom)
mant_bits = min (mant_bits_left, 32);
if (get_field (ufrom, fmt->byteorder, fmt->totalsize,
mant_off, mant_bits) != 0)
return 1;
mant_off, mant_bits) != 0) {
return 1;
}
mant_off += mant_bits;
mant_bits_left -= mant_bits;
@ -431,10 +441,11 @@ get_field (const unsigned char *data, enum floatformat_byteorders order,
start = total_len - (start + len);
/* Start at the least significant part of the field. */
if (order == floatformat_little)
cur_byte = start / FLOATFORMAT_CHAR_BIT;
else
cur_byte = (total_len - start - 1) / FLOATFORMAT_CHAR_BIT;
if (order == floatformat_little) {
cur_byte = start / FLOATFORMAT_CHAR_BIT;
} else {
cur_byte = (total_len - start - 1) / FLOATFORMAT_CHAR_BIT;
}
lo_bit = start % FLOATFORMAT_CHAR_BIT;
hi_bit = min (lo_bit + len, FLOATFORMAT_CHAR_BIT);
@ -492,13 +503,15 @@ floatformat_to_double (const struct floatformat *fmt,
conjunction with the GNU/C99 extension for hexadecimal
floating point constants and will issue a warning when
compiling with -pedantic. */
if (nan)
dto = NAN;
else
dto = INFINITY;
if (nan) {
dto = NAN;
} else {
dto = INFINITY;
}
if (get_field (ufrom, fmt->byteorder, fmt->totalsize, fmt->sign_start, 1))
dto = -dto;
if (get_field (ufrom, fmt->byteorder, fmt->totalsize, fmt->sign_start, 1)) {
dto = -dto;
}
*to = dto;
@ -513,20 +526,20 @@ floatformat_to_double (const struct floatformat *fmt,
who cares. */
/* For denorms use minimum exponent. */
if (exponent == 0)
exponent = 1 - fmt->exp_bias;
else
{
exponent -= fmt->exp_bias;
if (exponent == 0) {
exponent = 1 - fmt->exp_bias;
} else {
exponent -= fmt->exp_bias;
/* If this format uses a hidden bit, explicitly add it in now.
/* If this format uses a hidden bit, explicitly add it in now.
Otherwise, increment the exponent by one to account for the
integer bit. */
if (fmt->intbit == floatformat_intbit_no)
dto = ldexp (1.0, exponent);
else
exponent++;
if (fmt->intbit == floatformat_intbit_no) {
dto = ldexp (1.0, exponent);
} else {
exponent++;
}
}
while (mant_bits_left > 0)
@ -543,9 +556,10 @@ floatformat_to_double (const struct floatformat *fmt,
}
/* Negate it if negative. */
if (get_field (ufrom, fmt->byteorder, fmt->totalsize, fmt->sign_start, 1))
dto = -dto;
*to = dto;
if (get_field (ufrom, fmt->byteorder, fmt->totalsize, fmt->sign_start, 1)) {
dto = -dto;
}
*to = dto;
}
static void put_field (unsigned char *, enum floatformat_byteorders,
@ -569,10 +583,11 @@ put_field (unsigned char *data, enum floatformat_byteorders order,
start = total_len - (start + len);
/* Start at the least significant part of the field. */
if (order == floatformat_little)
cur_byte = start / FLOATFORMAT_CHAR_BIT;
else
cur_byte = (total_len - start - 1) / FLOATFORMAT_CHAR_BIT;
if (order == floatformat_little) {
cur_byte = start / FLOATFORMAT_CHAR_BIT;
} else {
cur_byte = (total_len - start - 1) / FLOATFORMAT_CHAR_BIT;
}
lo_bit = start % FLOATFORMAT_CHAR_BIT;
hi_bit = min (lo_bit + len, FLOATFORMAT_CHAR_BIT);
@ -653,16 +668,15 @@ floatformat_from_double (const struct floatformat *fmt,
#else
mant = frexp (dfrom, &exponent);
#endif
if (exponent + fmt->exp_bias - 1 > 0)
put_field (uto, fmt->byteorder, fmt->totalsize, fmt->exp_start,
fmt->exp_len, exponent + fmt->exp_bias - 1);
else
{
/* Handle a denormalized number. FIXME: What should we do for
if (exponent + fmt->exp_bias - 1 > 0) {
put_field (uto, fmt->byteorder, fmt->totalsize, fmt->exp_start,
fmt->exp_len, exponent + fmt->exp_bias - 1);
} else {
/* Handle a denormalized number. FIXME: What should we do for
non-IEEE formats? */
put_field (uto, fmt->byteorder, fmt->totalsize, fmt->exp_start,
fmt->exp_len, 0);
mant = ldexp (mant, exponent + fmt->exp_bias - 1);
put_field (uto, fmt->byteorder, fmt->totalsize, fmt->exp_start,
fmt->exp_len, 0);
mant = ldexp (mant, exponent + fmt->exp_bias - 1);
}
mant_bits_left = fmt->man_len;

16
libr/asm/arch/arm/winedbg/be_arm.c
View File

@ -323,8 +323,11 @@ static ut32 arm_disasm_blocktrans(struct winedbg_arm_insn *arminsn, ut32 inst) {
get_cond (inst), tbl_regs[get_nibble (inst, 4)], writeback ? "!" : "");
for (i=0;i<=15;i++) {
if ((inst>>i) & 1) {
if (i == last) arminsn->str_asm = r_str_appendf (arminsn->str_asm, "%s", tbl_regs[i]);
else arminsn->str_asm = r_str_appendf (arminsn->str_asm, "%s, ", tbl_regs[i]);
if (i == last) {
arminsn->str_asm = r_str_appendf (arminsn->str_asm, "%s", tbl_regs[i]);
} else {
arminsn->str_asm = r_str_appendf (arminsn->str_asm, "%s, ", tbl_regs[i]);
}
}
}
arminsn->str_asm = r_str_appendf (arminsn->str_asm, "}%s", psr ? "^" : "");
@ -378,12 +381,13 @@ static ut32 arm_disasm_coprocdatatrans(struct winedbg_arm_insn *arminsn, ut32 in
}
arminsn->str_asm = r_str_appendf (arminsn->str_asm, "%s%s%s", load ? "ldc" : "stc", translen ? "l" : "", get_cond (inst));
if (indexing)
if (indexing) {
arminsn->str_asm = r_str_appendf (arminsn->str_asm, " %u, cr%u, [%s, #%d]%s", CPnum, CRd, tbl_regs[get_nibble (inst, 4)],
offset, writeback?"!":"");
else
offset, writeback ? "!" : "");
} else {
arminsn->str_asm = r_str_appendf (arminsn->str_asm, " %u, cr%u, [%s], #%d", CPnum, CRd, tbl_regs[get_nibble (inst, 4)],
offset);
offset);
}
return 0;
}

71
libr/asm/arch/cr16/cr16_disas.c
View File

@ -423,8 +423,9 @@ static inline int cr16_decode_i_r(const ut8 *instr, struct cr16_cmd *cmd)
in = r_read_le16 (instr);
if (in == 0x0200)
if (in == 0x0200) {
return -1;
}
if (((in >> 9) != CR16_TBIT_I_R) && ((in >> 9) != CR16_TBIT_R_R)) {
if (cr16_print_4biti_opcode(cmd, in)) {
@ -528,8 +529,9 @@ static inline int cr16_decode_ld_st(const ut8 *instr, struct cr16_cmd *cmd)
ret = -1;
}
if (ret != -1)
if (ret != -1) {
return ret;
}
ret = 2;
@ -584,8 +586,9 @@ static inline int cr16_decode_ld_st(const ut8 *instr, struct cr16_cmd *cmd)
ret = -1;
}
if (ret != -1)
if (ret != -1) {
return ret;
}
ret = 2;
switch (c >> 14) {
@ -765,11 +768,13 @@ static int cr16_decode_bcond_br(const ut8 *instr, struct cr16_cmd *cmd)
c = r_read_le16 (instr);
if (c & 0x1)
if (c & 0x1) {
return -1;
}
if (!(c >> 14) && cr16_get_opcode_low(c) != 0xA)
if (!(c >> 14) && cr16_get_opcode_low (c) != 0xA) {
return -1;
}
if (((c >> 5) & 0xF) == 0xE) {
snprintf(cmd->instr, CR16_INSTR_MAXLEN - 1, "br");
@ -816,8 +821,9 @@ static int cr16_decode_bcond_br(const ut8 *instr, struct cr16_cmd *cmd)
} else {
snprintf(cmd->instr, CR16_INSTR_MAXLEN - 1, "b%s",
cr16_conds[cr16_get_cond(c)]);
if (c & 0x1)
if (c & 0x1) {
return -1;
}
if ((c >> 8) == CR16_BCOND_2) {
disp = r_read_at_le16 (instr, 2);
@ -856,12 +862,13 @@ static int cr16_decode_bcond01i(const ut8 *instr, struct cr16_cmd *cmd)
c = r_read_le16 (instr);
if (!(c & 1))
if (!(c & 1)) {
return -1;
}
if (c >> 14)
if (c >> 14) {
return -1;
}
switch ((c >> 6) & 0x3) {
case 0x0:
@ -976,8 +983,9 @@ int cr16_decode_loadm_storm(const ut8 *instr, struct cr16_cmd *cmd)
c = r_read_le16 (instr);
if ((c & 0x1F) != 4)
if ((c & 0x1F) != 4) {
return -1;
}
snprintf(cmd->instr, CR16_INSTR_MAXLEN - 1, "%s",
instrs_4bit[c >> 7]);
@ -995,8 +1003,9 @@ int cr16_decode_movz(const ut8 *instr, struct cr16_cmd *cmd)
ut16 c;
c = r_read_le16 (instr);
if (c & 1)
if (c & 1) {
return -1;
}
switch (c >> 9) {
case CR16_MOVXB:
@ -1026,8 +1035,9 @@ int cr16_decode_movd(const ut8 *instr, struct cr16_cmd *cmd)
c = r_read_le16 (instr);
imm = r_read_at_le16 (instr, 2);
if (c & 1)
if (c & 1) {
return -1;
}
snprintf(cmd->instr, CR16_INSTR_MAXLEN - 1, "movd");
@ -1060,8 +1070,9 @@ int cr16_decode_muls(const ut8 *instr, struct cr16_cmd *cmd)
cr16_regs_names[cr16_get_dstreg(c)]);
break;
case CR16_MULUW:
if (c & 0x000C)
if (c & 0x000C) {
return -1;
}
snprintf(cmd->instr, CR16_INSTR_MAXLEN - 1, "muluw");
snprintf(cmd->operands, CR16_INSTR_MAXLEN - 1, "%s,(%s,%s)",
@ -1081,8 +1092,9 @@ int cr16_decode_scond(const ut8 *instr, struct cr16_cmd *cmd)
c = r_read_le16 (instr);
if (c & 1)
if (c & 1) {
return -1;
}
snprintf(cmd->instr, CR16_INSTR_MAXLEN - 1, "s%s",
cr16_conds[cr16_get_dstreg(c)]);
@ -1196,8 +1208,9 @@ int cr16_decode_command(const ut8 *instr, struct cr16_cmd *cmd)
ret = -1;
}
if (ret != -1)
if (ret != -1) {
return ret;
}
switch ((in >> 13)) {
case 0x2:
@ -1206,8 +1219,9 @@ int cr16_decode_command(const ut8 *instr, struct cr16_cmd *cmd)
break;
}
if (ret != -1)
if (ret != -1) {
return ret;
}
switch (in >> 9) {
case CR16_LPR:
@ -1216,8 +1230,9 @@ int cr16_decode_command(const ut8 *instr, struct cr16_cmd *cmd)
break;
case CR16_TBIT_R_R:
ret = cr16_decode_r_r(instr, cmd);
if (ret == -1)
ret = cr16_decode_bal(instr, cmd);
if (ret == -1) {
ret = cr16_decode_bal (instr, cmd);
}
break;
case CR16_TBIT_I_R:
ret = cr16_decode_i_r(instr, cmd);
@ -1229,8 +1244,9 @@ int cr16_decode_command(const ut8 *instr, struct cr16_cmd *cmd)
case CR16_JAL:
case 0x0B:
ret = cr16_decode_jmp(instr, cmd);
if (ret == -1)
ret = cr16_decode_bcond_br(instr, cmd);
if (ret == -1) {
ret = cr16_decode_bcond_br (instr, cmd);
}
break;
case CR16_MOVXB:
case CR16_MOVZB:
@ -1243,8 +1259,9 @@ int cr16_decode_command(const ut8 *instr, struct cr16_cmd *cmd)
break;
}
if (ret != -1)
if (ret != -1) {
return ret;
}
switch (in >> 7) {
case CR16_PUSH:
@ -1259,8 +1276,9 @@ int cr16_decode_command(const ut8 *instr, struct cr16_cmd *cmd)
break;
}
if (ret != -1)
if (ret != -1) {
return ret;
}
switch (in >> 10) {
case CR16_MOVD:
@ -1268,13 +1286,15 @@ int cr16_decode_command(const ut8 *instr, struct cr16_cmd *cmd)
break;
}
if (ret != -1)
if (ret != -1) {
return ret;
}
ret = cr16_decode_misc(instr, cmd);
if (ret != -1)
if (ret != -1) {
return ret;
}
switch (cr16_get_opcode_hi(in)) {
case 0x2:
@ -1285,7 +1305,8 @@ int cr16_decode_command(const ut8 *instr, struct cr16_cmd *cmd)
break;
}
if (ret != -1)
if (ret != -1) {
return ret;
}
return ret;
}

1117
libr/asm/arch/cris/gnu/cris-dis.c
View File

File diff suppressed because it is too large Load Diff

16
libr/asm/arch/ebc/ebc_disas.c
View File

@ -141,9 +141,12 @@ static int decode_jmp(const ut8 *bytes, ebc_command_t *cmd) {
ret = 10;
snprintf(cmd->operands, EBC_OPERANDS_MAXLEN, "0x%lx", immed);
} else {
if ((bytes[1] & 0x7) != 0)
snprintf(op1, sizeof (op1), "%sr%u ",
TEST_BIT(bytes[1], 3) ? "@" : "", bytes[1] & 0x7);
if ((bytes[1] & 0x7) != 0) {
{
snprintf (op1, sizeof (op1), "%sr%u ",
TEST_BIT (bytes[1], 3) ? "@" : "", bytes[1] & 0x7);
}
}
if (TEST_BIT (bytes[0], 7)) {
if (TEST_BIT(bytes[1], 3)) {
decode_index32(bytes + 2, &idx32);
@ -978,7 +981,10 @@ static decode decodes[EBC_COMMAND_NUM] = {
};
int ebc_decode_command(const ut8 *instr, ebc_command_t *cmd) {
if ((instr[0] & EBC_OPCODE_MASK) > 0x39)
return -1;
if ((instr[0] & EBC_OPCODE_MASK) > 0x39) {
{
return -1;
}
}
return decodes[instr[0] & EBC_OPCODE_MASK](instr, cmd);
}

7
libr/asm/arch/h8300/h8300_disas.c
View File

@ -833,8 +833,11 @@ int h8300_decode_command(const ut8 *instr, struct h8300_cmd *cmd)
break;
}
if (ret)
return ret;
if (ret) {
{
return ret;
}
}
switch (instr[0]) {
case H8300_ANDC:

359
libr/asm/arch/hppa/gnu/hppa-dis.c
View File

@ -190,10 +190,11 @@ static void
fput_fp_reg_r (unsigned reg, disassemble_info *info)
{
/* Special case floating point exception registers. */
if (reg < 4)
(*info->fprintf_func) (info->stream, "fpe%d", reg * 2 + 1);
else
(*info->fprintf_func) (info->stream, "%sR", fp_reg_names[reg]);
if (reg < 4) {
(*info->fprintf_func) (info->stream, "fpe%d", reg * 2 + 1);
} else {
(*info->fprintf_func) (info->stream, "%sR", fp_reg_names[reg]);
}
}
static void
@ -207,10 +208,11 @@ fput_creg (unsigned reg, disassemble_info *info)
static void
fput_const (unsigned num, disassemble_info *info)
{
if ((int) num < 0)
(*info->fprintf_func) (info->stream, "-%x", - (int) num);
else
(*info->fprintf_func) (info->stream, "%x", num);
if ((int)num < 0) {
(*info->fprintf_func) (info->stream, "-%x", -(int)num);
} else {
(*info->fprintf_func) (info->stream, "%x", num);
}
}
/* Routines to extract various sized constants out of hppa
@ -386,8 +388,9 @@ print_insn_hppa (bfd_vma memaddr, disassemble_info *info)
#endif
(*info->fprintf_func) (info->stream, "%s", opcode->name);
if (!strchr ("cfCY?-+nHNZFIuv{", opcode->args[0]))
(*info->fprintf_func) (info->stream, " ");
if (!strchr ("cfCY?-+nHNZFIuv{", opcode->args[0])) {
(*info->fprintf_func) (info->stream, " ");
}
for (s = opcode->args; *s != '\0'; ++s)
{
switch (*s)
@ -414,19 +417,21 @@ print_insn_hppa (bfd_vma memaddr, disassemble_info *info)
fput_fp_reg (GET_FIELD (insn, 27, 31), info);
break;
case 'T':
if (GET_FIELD (insn, 25, 25))
fput_fp_reg_r (GET_FIELD (insn, 27, 31), info);
else
fput_fp_reg (GET_FIELD (insn, 27, 31), info);
break;
if (GET_FIELD (insn, 25, 25)) {
fput_fp_reg_r (GET_FIELD (insn, 27, 31), info);
} else {
fput_fp_reg (GET_FIELD (insn, 27, 31), info);
}
break;
case 'a':
if (GET_FIELD (insn, 25, 25))
fput_fp_reg_r (GET_FIELD (insn, 6, 10), info);
else
fput_fp_reg (GET_FIELD (insn, 6, 10), info);
break;
if (GET_FIELD (insn, 25, 25)) {
fput_fp_reg_r (GET_FIELD (insn, 6, 10), info);
} else {
fput_fp_reg (GET_FIELD (insn, 6, 10), info);
}
break;
/* 'fA' will not generate a space before the register
/* 'fA' will not generate a space before the register
name. Normally that is fine. Except that it
causes problems with xmpyu which has no FP format
completer. */
@ -435,31 +440,35 @@ print_insn_hppa (bfd_vma memaddr, disassemble_info *info)
/* FALLTHRU */
case 'A':
if (GET_FIELD (insn, 24, 24))
fput_fp_reg_r (GET_FIELD (insn, 6, 10), info);
else
fput_fp_reg (GET_FIELD (insn, 6, 10), info);
break;
if (GET_FIELD (insn, 24, 24)) {
fput_fp_reg_r (GET_FIELD (insn, 6, 10), info);
} else {
fput_fp_reg (GET_FIELD (insn, 6, 10), info);
}
break;
case 'b':
if (GET_FIELD (insn, 25, 25))
fput_fp_reg_r (GET_FIELD (insn, 11, 15), info);
else
fput_fp_reg (GET_FIELD (insn, 11, 15), info);
break;
if (GET_FIELD (insn, 25, 25)) {
fput_fp_reg_r (GET_FIELD (insn, 11, 15), info);
} else {
fput_fp_reg (GET_FIELD (insn, 11, 15), info);
}
break;
case 'B':
if (GET_FIELD (insn, 19, 19))
fput_fp_reg_r (GET_FIELD (insn, 11, 15), info);
else
fput_fp_reg (GET_FIELD (insn, 11, 15), info);
break;
if (GET_FIELD (insn, 19, 19)) {
fput_fp_reg_r (GET_FIELD (insn, 11, 15), info);
} else {
fput_fp_reg (GET_FIELD (insn, 11, 15), info);
}
break;
case 'C':
{
int reg = GET_FIELD (insn, 21, 22);
reg |= GET_FIELD (insn, 16, 18) << 2;
if (GET_FIELD (insn, 23, 23) != 0)
fput_fp_reg_r (reg, info);
else
fput_fp_reg (reg, info);
if (GET_FIELD (insn, 23, 23) != 0) {
fput_fp_reg_r (reg, info);
} else {
fput_fp_reg (reg, info);
}
break;
}
case 'i':
@ -512,11 +521,12 @@ print_insn_hppa (bfd_vma memaddr, disassemble_info *info)
/* FALLTHRU */
case 'e':
if (GET_FIELD (insn, 30, 30))
fput_fp_reg_r (GET_FIELD (insn, 11, 15), info);
else
fput_fp_reg (GET_FIELD (insn, 11, 15), info);
break;
if (GET_FIELD (insn, 30, 30)) {
fput_fp_reg_r (GET_FIELD (insn, 11, 15), info);
} else {
fput_fp_reg (GET_FIELD (insn, 11, 15), info);
}
break;
case 'x':
fput_fp_reg (GET_FIELD (insn, 11, 15), info);
break;
@ -530,8 +540,9 @@ print_insn_hppa (bfd_vma memaddr, disassemble_info *info)
{
int space = GET_FIELD (insn, 16, 17);
/* Zero means implicit addressing, not use of sr0. */
if (space != 0)
(*info->fprintf_func) (info->stream, "sr%d", space);
if (space != 0) {
(*info->fprintf_func) (info->stream, "sr%d", space);
}
}
break;
@ -623,23 +634,27 @@ print_insn_hppa (bfd_vma memaddr, disassemble_info *info)
(*info->fprintf_func) (info->stream, ",w ");
break;
case 'r':
if (GET_FIELD (insn, 23, 26) == 5)
(*info->fprintf_func) (info->stream, ",r");
break;
if (GET_FIELD (insn, 23, 26) == 5) {
(*info->fprintf_func) (info->stream, ",r");
}
break;
case 'Z':
if (GET_FIELD (insn, 26, 26))
(*info->fprintf_func) (info->stream, ",m ");
else
(*info->fprintf_func) (info->stream, " ");
break;
if (GET_FIELD (insn, 26, 26)) {
(*info->fprintf_func) (info->stream, ",m ");
} else {
(*info->fprintf_func) (info->stream, " ");
}
break;
case 'i':
if (GET_FIELD (insn, 25, 25))
(*info->fprintf_func) (info->stream, ",i");
break;
if (GET_FIELD (insn, 25, 25)) {
(*info->fprintf_func) (info->stream, ",i");
}
break;
case 'z':
if (!GET_FIELD (insn, 21, 21))
(*info->fprintf_func) (info->stream, ",z");
break;
if (!GET_FIELD (insn, 21, 21)) {
(*info->fprintf_func) (info->stream, ",z");
}
break;
case 'a':
(*info->fprintf_func)
(info->stream, "%s",
@ -656,38 +671,42 @@ print_insn_hppa (bfd_vma memaddr, disassemble_info *info)
add_compl_names[GET_FIELD (insn, 20, 21)]);
break;
case 'v':
if (GET_FIELD (insn, 20, 20))
(*info->fprintf_func) (info->stream, ",tsv");
break;
if (GET_FIELD (insn, 20, 20)) {
(*info->fprintf_func) (info->stream, ",tsv");
}
break;
case 't':
(*info->fprintf_func) (info->stream, ",tc");
if (GET_FIELD (insn, 20, 20))
(*info->fprintf_func) (info->stream, ",tsv");
if (GET_FIELD (insn, 20, 20)) {
(*info->fprintf_func) (info->stream, ",tsv");
}
break;
case 'B':
(*info->fprintf_func) (info->stream, ",db");
if (GET_FIELD (insn, 20, 20))
(*info->fprintf_func) (info->stream, ",tsv");
if (GET_FIELD (insn, 20, 20)) {
(*info->fprintf_func) (info->stream, ",tsv");
}
break;
case 'b':
(*info->fprintf_func) (info->stream, ",b");
if (GET_FIELD (insn, 20, 20))
(*info->fprintf_func) (info->stream, ",tsv");
if (GET_FIELD (insn, 20, 20)) {
(*info->fprintf_func) (info->stream, ",tsv");
}
break;
case 'T':
if (GET_FIELD (insn, 25, 25))
(*info->fprintf_func) (info->stream, ",tc");
break;
if (GET_FIELD (insn, 25, 25)) {
(*info->fprintf_func) (info->stream, ",tc");
}
break;
case 'S':
/* EXTRD/W has a following condition. */
if (*(s + 1) == '?')
(*info->fprintf_func)
(info->stream, "%s",
signed_unsigned_names[GET_FIELD (insn, 21, 21)]);
else
(*info->fprintf_func)
(info->stream, "%s ",
signed_unsigned_names[GET_FIELD (insn, 21, 21)]);
if (*(s + 1) == '?') {
(*info->fprintf_func) (info->stream, "%s",
signed_unsigned_names[GET_FIELD (insn, 21, 21)]);
} else {
(*info->fprintf_func) (info->stream, "%s ",
signed_unsigned_names[GET_FIELD (insn, 21, 21)]);
}
break;
case 'h':
(*info->fprintf_func)
@ -713,12 +732,13 @@ print_insn_hppa (bfd_vma memaddr, disassemble_info *info)
m = GET_FIELD (insn, 28, 28);
a = GET_FIELD (insn, 29, 29);
if (m && !a)
fputs_filtered (",ma ", info);
else if (m && a)
fputs_filtered (",mb ", info);
else
fputs_filtered (" ", info);
if (m && !a) {
fputs_filtered (",ma ", info);
} else if (m && a) {
fputs_filtered (",mb ", info);
} else {
fputs_filtered (" ", info);
}
break;
}
@ -728,13 +748,14 @@ print_insn_hppa (bfd_vma memaddr, disassemble_info *info)
if (opc == 0x16 || opc == 0x1e)
{
if (GET_FIELD (insn, 29, 29) == 0)
fputs_filtered (",ma ", info);
else
fputs_filtered (",mb ", info);
}
else
fputs_filtered (" ", info);
if (GET_FIELD (insn, 29, 29) == 0) {
fputs_filtered (",ma ", info);
} else {
fputs_filtered (",mb ", info);
}
} else {
fputs_filtered (" ", info);
}
break;
}
@ -744,22 +765,24 @@ print_insn_hppa (bfd_vma memaddr, disassemble_info *info)
if (opc == 0x13 || opc == 0x1b)
{
if (GET_FIELD (insn, 18, 18) == 1)
fputs_filtered (",mb ", info);
else
fputs_filtered (",ma ", info);
if (GET_FIELD (insn, 18, 18) == 1) {
fputs_filtered (",mb ", info);
} else {
fputs_filtered (",ma ", info);
}
}
else if (opc == 0x17 || opc == 0x1f)
{
if (GET_FIELD (insn, 31, 31) == 1)
fputs_filtered (",ma ", info);
else
fputs_filtered (",mb ", info);
if (GET_FIELD (insn, 31, 31) == 1) {
fputs_filtered (",ma ", info);
} else {
fputs_filtered (",mb ", info);
}
} else {
fputs_filtered (" ", info);
}
else
fputs_filtered (" ", info);
break;
break;
}
}
break;
@ -869,8 +892,9 @@ print_insn_hppa (bfd_vma memaddr, disassemble_info *info)
/* If the next character in args is 'n', it will handle
putting out the space. */
if (s[1] != 'n')
(*info->fprintf_func) (info->stream, " ");
if (s[1] != 'n') {
(*info->fprintf_func) (info->stream, " ");
}
break;
case 'X':
(*info->fprintf_func)
@ -884,8 +908,9 @@ print_insn_hppa (bfd_vma memaddr, disassemble_info *info)
/* If the next character in args is 'n', it will handle
putting out the space. */
if (s[1] != 'n')
(*info->fprintf_func) (info->stream, " ");
if (s[1] != 'n') {
(*info->fprintf_func) (info->stream, " ");
}
break;
}
break;
@ -923,19 +948,21 @@ print_insn_hppa (bfd_vma memaddr, disassemble_info *info)
fput_const (extract_16 (insn), info);
break;
case 'n':
if (insn & 0x2)
(*info->fprintf_func) (info->stream, ",n ");
else
(*info->fprintf_func) (info->stream, " ");
break;
if (insn & 0x2) {
(*info->fprintf_func) (info->stream, ",n ");
} else {
(*info->fprintf_func) (info->stream, " ");
}
break;
case 'N':
if ((insn & 0x20) && s[1])
(*info->fprintf_func) (info->stream, ",n ");
else if (insn & 0x20)
(*info->fprintf_func) (info->stream, ",n");
else if (s[1])
(*info->fprintf_func) (info->stream, " ");
break;
if ((insn & 0x20) && s[1]) {
(*info->fprintf_func) (info->stream, ",n ");
} else if (insn & 0x20) {
(*info->fprintf_func) (info->stream, ",n");
} else if (s[1]) {
(*info->fprintf_func) (info->stream, " ");
}
break;
case 'w':
(*info->print_address_func)
(memaddr + 8 + extract_12 (insn), info);
@ -1060,13 +1087,12 @@ print_insn_hppa (bfd_vma memaddr, disassemble_info *info)
case 'F':
/* If no destination completer and not before a completer
for fcmp, need a space here. */
if (s[1] == 'G' || s[1] == '?')
fputs_filtered
(float_format_names[GET_FIELD (insn, 19, 20)], info);
else
(*info->fprintf_func)
(info->stream, "%s ",
float_format_names[GET_FIELD (insn, 19, 20)]);
if (s[1] == 'G' || s[1] == '?') {
fputs_filtered (float_format_names[GET_FIELD (insn, 19, 20)], info);
} else {
(*info->fprintf_func) (info->stream, "%s ",
float_format_names[GET_FIELD (insn, 19, 20)]);
}
break;
case 'G':
(*info->fprintf_func)
@ -1074,23 +1100,23 @@ print_insn_hppa (bfd_vma memaddr, disassemble_info *info)
float_format_names[GET_FIELD (insn, 17, 18)]);
break;
case 'H':
if (GET_FIELD (insn, 26, 26) == 1)
(*info->fprintf_func) (info->stream, "%s ",
float_format_names[0]);
else
(*info->fprintf_func) (info->stream, "%s ",
float_format_names[1]);
break;
if (GET_FIELD (insn, 26, 26) == 1) {
(*info->fprintf_func) (info->stream, "%s ",
float_format_names[0]);
} else {
(*info->fprintf_func) (info->stream, "%s ",
float_format_names[1]);
}
break;
case 'I':
/* If no destination completer and not before a completer
for fcmp, need a space here. */
if (s[1] == '?')
fputs_filtered
(float_format_names[GET_FIELD (insn, 20, 20)], info);
else
(*info->fprintf_func)
(info->stream, "%s ",
float_format_names[GET_FIELD (insn, 20, 20)]);
if (s[1] == '?') {
fputs_filtered (float_format_names[GET_FIELD (insn, 20, 20)], info);
} else {
(*info->fprintf_func) (info->stream, "%s ",
float_format_names[GET_FIELD (insn, 20, 20)]);
}
break;
case 'J':
@ -1103,10 +1129,11 @@ print_insn_hppa (bfd_vma memaddr, disassemble_info *info)
int imm10 = GET_FIELD (insn, 18, 27);
int disp;
if (sign)
disp = (UT64_MAX << 10) | imm10;
else
disp = imm10;
if (sign) {
disp = (UT64_MAX << 10) | imm10;
} else {
disp = imm10;
}
disp <<= 3;
fput_const (disp, info);
@ -1119,10 +1146,11 @@ print_insn_hppa (bfd_vma memaddr, disassemble_info *info)
int imm11 = GET_FIELD (insn, 18, 28);
int disp;
if (sign)
disp = (UT64_MAX << 11) | imm11;
else
disp = imm11;
if (sign) {
disp = (UT64_MAX << 11) | imm11;
} else {
disp = imm11;
}
disp <<= 2;
fput_const (disp, info);
@ -1165,24 +1193,28 @@ print_insn_hppa (bfd_vma memaddr, disassemble_info *info)
fputs_filtered (",UND ", info);
break;
}
if ((sub & 3) == 3)
t = ",t";
if ((sub & 3) == 1)
source = sub & 4 ? fcnv_ufixed_names : fcnv_fixed_names;
if (sub & 2)
dest = sub & 4 ? fcnv_ufixed_names : fcnv_fixed_names;
if ((sub & 3) == 3) {
t = ",t";
}
if ((sub & 3) == 1) {
source = sub & 4 ? fcnv_ufixed_names : fcnv_fixed_names;
}
if (sub & 2) {
dest = sub & 4 ? fcnv_ufixed_names : fcnv_fixed_names;
}
(*info->fprintf_func) (info->stream, "%s%s%s ",
t, source[sf], dest[df]);
break;
(*info->fprintf_func) (info->stream, "%s%s%s ",
t, source[sf], dest[df]);
break;
}
case 'm':
{
int y = GET_FIELD (insn, 16, 18);
if (y != 1)
fput_const ((y ^ 1) - 1, info);
if (y != 1) {
fput_const ((y ^ 1) - 1, info);
}
}
break;
@ -1192,8 +1224,9 @@ print_insn_hppa (bfd_vma memaddr, disassemble_info *info)
cbit = GET_FIELD (insn, 16, 18);
if (cbit > 0)
(*info->fprintf_func) (info->stream, ",%d", cbit - 1);
if (cbit > 0) {
(*info->fprintf_func) (info->stream, ",%d", cbit - 1);
}
break;
}

74
libr/asm/arch/lanai/gnu/lanai-dis.c
View File

@ -84,9 +84,9 @@ is_delayed_branch (insn)
for (i = 0; i < NUMOPCODES; ++i)
{
CONST struct lanai_opcode *opcode = &lanai_opcodes[i];
if ((opcode->match & insn) == opcode->match
&& (opcode->lose & insn) == 0)
return (opcode->flags & F_BR);
if ((opcode->match & insn) == opcode->match && (opcode->lose & insn) == 0) {
return (opcode->flags & F_BR);
}
}
return 0;
}
@ -212,8 +212,9 @@ print_insn_lanai (memaddr, info)
break;
case '5': /* Op2 (for RRR) */
(*info->fprintf_func) (stream, "%s", op_names[X_OP2(insn)]);
if(insn&L3_RRR_F)
(*info->fprintf_func) (stream, ".f");
if (insn & L3_RRR_F) {
(*info->fprintf_func) (stream, ".f");
}
break;
case '6': /* Op2 (for RRM) */
(*info->fprintf_func) (stream, "%s", op_names[X_OP2(insn)]);
@ -237,14 +238,18 @@ print_insn_lanai (memaddr, info)
break;
case 'o':
imm = SEX (X_C16(insn), 16);
if (X_RS1 (insn) == 0) goto print_address;
if (X_RS1 (insn) == 0) {
goto print_address;
}
goto print_immediate;
case 's':
imm = SEX (X_C16(insn), 16);
goto print_immediate;
case 'i':
imm = SEX (X_C10(insn), 10);
if (X_RS1 (insn) == 0) goto print_address;
if (X_RS1 (insn) == 0) {
goto print_address;
}
goto print_immediate;
case 'I':
imm = X_C21(insn);
@ -372,14 +377,15 @@ print_insn_lanai (memaddr, info)
if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR))
{
/* FIXME -- check is_annulled flag */
if (opcode->flags & F_UNBR)
info->insn_type = dis_branch;
else if (opcode->flags & F_CONDBR)
info->insn_type = dis_condbranch;
else if (opcode->flags & F_JSR)
info->insn_type = dis_jsr;
else if (opcode->flags & F_BR)
info->branch_delay_insns = 1;
if (opcode->flags & F_UNBR) {
info->insn_type = dis_branch;
} else if (opcode->flags & F_CONDBR) {
info->insn_type = dis_condbranch;
} else if (opcode->flags & F_JSR) {
info->insn_type = dis_jsr;
} else if (opcode->flags & F_BR) {
info->branch_delay_insns = 1;
}
}
return sizeof (buffer);
@ -429,8 +435,9 @@ compare_opcodes (a, b)
int x0 = (match0 & x) != 0;
int x1 = (match1 & x) != 0;
if (x0 != x1)
return x1 - x0;
if (x0 != x1) {
return x1 - x0;
}
}
for (i = 0; i < 32; ++i)
@ -439,8 +446,9 @@ compare_opcodes (a, b)
int x0 = (lose0 & x) != 0;
int x1 = (lose1 & x) != 0;
if (x0 != x1)
return x1 - x0;
if (x0 != x1) {
return x1 - x0;
}
}
/* They are functionally equal. So as long as the opcode table is
@ -449,9 +457,10 @@ compare_opcodes (a, b)
/* Our first aesthetic ground is that aliases defer to real insns. */
{
int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS);
if (alias_diff != 0)
/* Put the one that isn't an alias first. */
return alias_diff;
if (alias_diff != 0) {
/* Put the one that isn't an alias first. */
return alias_diff;
}
}
/* Except for aliases, two "identical" instructions had
@ -474,9 +483,10 @@ compare_opcodes (a, b)
/* Fewer arguments are preferred. */
{
int length_diff = strlen (op0->args) - strlen (op1->args);
if (length_diff != 0)
/* Put the one with fewer arguments first. */
return length_diff;
if (length_diff != 0) {
/* Put the one with fewer arguments first. */
return length_diff;
}
}
/* Put 1+i before i+1. */
@ -489,12 +499,14 @@ compare_opcodes (a, b)
/* There is a plus in both operands. Note that a plus
sign cannot be the first character in args,
so the following [-1]'s are valid. */
if (p0[-1] == 'i' && p1[1] == 'i')
/* op0 is i+1 and op1 is 1+i, so op1 goes first. */
return 1;
if (p0[1] == 'i' && p1[-1] == 'i')
/* op0 is 1+i and op1 is i+1, so op0 goes first. */
return -1;
if (p0[-1] == 'i' && p1[1] == 'i') {
/* op0 is i+1 and op1 is 1+i, so op1 goes first. */
return 1;
}
if (p0[1] == 'i' && p1[-1] == 'i') {
/* op0 is 1+i and op1 is i+1, so op0 goes first. */
return -1;
}
}
}

556
libr/asm/arch/mips/gnu/mips-dis.c
View File

@ -457,10 +457,11 @@ choose_abi_by_name (const char *name, unsigned int namelen)
const struct mips_abi_choice *c;
unsigned int i;
for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && !c; i++)
if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
&& strlen (mips_abi_choices[i].name) == namelen)
c = &mips_abi_choices[i];
for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && !c; i++) {
if (strncmp (mips_abi_choices[i].name, name, namelen) == 0 && strlen (mips_abi_choices[i].name) == namelen) {
c = &mips_abi_choices[i];
}
}
return c;
}
@ -471,10 +472,11 @@ choose_arch_by_name (const char *name, unsigned int namelen)
const struct mips_arch_choice *c = NULL;
unsigned int i;
for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && !c; i++)
if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
&& strlen (mips_arch_choices[i].name) == namelen)
c = &mips_arch_choices[i];
for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && !c; i++) {
if (strncmp (mips_arch_choices[i].name, name, namelen) == 0 && strlen (mips_arch_choices[i].name) == namelen) {
c = &mips_arch_choices[i];
}
}
return c;
}
@ -489,10 +491,9 @@ choose_arch_by_number (unsigned long mach)
/* We optimize this because even if the user specifies no
flags, this will be done for every instruction! */
if (hint_bfd_mach == mach
&& hint_arch_choice != NULL
&& hint_arch_choice->bfd_mach == hint_bfd_mach)
return hint_arch_choice;
if (hint_bfd_mach == mach && hint_arch_choice != NULL && hint_arch_choice->bfd_mach == hint_bfd_mach) {
return hint_arch_choice;
}
for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && !c; i++)
{
@ -513,12 +514,14 @@ static int
is_newabi (Elf_Internal_Ehdr *header)
{
/* There are no old-style ABIs which use 64-bit ELF. */
if (header->e_ident[EI_CLASS] == ELFCLASS64)
return 1;
if (header->e_ident[EI_CLASS] == ELFCLASS64) {
return 1;
}
/* If a 32-bit ELF file, n32 is a new-style ABI. */
if ((header->e_flags & EF_MIPS_ABI2) != 0)
return 1;
if ((header->e_flags & EF_MIPS_ABI2) != 0) {
return 1;
}
return 0;
}
@ -546,8 +549,9 @@ set_default_mips_dis_options (struct disassemble_info *info)
Elf_Internal_Ehdr *header;
header = elf_elfheader (info->section->owner);
if (is_newabi (header))
mips_gpr_names = mips_gpr_names_newabi;
if (is_newabi (header)) {
mips_gpr_names = mips_gpr_names_newabi;
}
}
/* Set ISA, architecture, and cp0 register names as best we can. */
@ -586,16 +590,21 @@ parse_mips_dis_option (const char *option, unsigned int len)
} */
/* Look for the = that delimits the end of the option name. */
for (i = 0; i < len; i++)
if (option[i] == '=')
break;
for (i = 0; i < len; i++) {
if (option[i] == '=') {
break;
}
}
if (i == 0) /* Invalid option: no name before '='. */
return;
if (i == len) /* Invalid option: no '='. */
return;
if (i == (len - 1)) /* Invalid option: no value after '='. */
return;
if (i == 0) { /* Invalid option: no name before '='. */
return;
}
if (i == len) { /* Invalid option: no '='. */
return;
}
if (i == (len - 1)) { /* Invalid option: no value after '='. */
return;
}
optionlen = i;
val = option + (optionlen + 1);
@ -605,8 +614,9 @@ parse_mips_dis_option (const char *option, unsigned int len)
&& strlen ("gpr-names") == optionlen)
{
chosen_abi = choose_abi_by_name (val, vallen);
if (chosen_abi != NULL)
mips_gpr_names = chosen_abi->gpr_names;
if (chosen_abi != NULL) {
mips_gpr_names = chosen_abi->gpr_names;
}
return;
}
@ -614,8 +624,9 @@ parse_mips_dis_option (const char *option, unsigned int len)
&& strlen ("fpr-names") == optionlen)
{
chosen_abi = choose_abi_by_name (val, vallen);
if (chosen_abi != NULL)
mips_fpr_names = chosen_abi->fpr_names;
if (chosen_abi != NULL) {
mips_fpr_names = chosen_abi->fpr_names;
}
return;
}
@ -636,8 +647,9 @@ parse_mips_dis_option (const char *option, unsigned int len)
&& strlen ("hwr-names") == optionlen)
{
chosen_arch = choose_arch_by_name (val, vallen);
if (chosen_arch != NULL)
mips_hwr_names = chosen_arch->hwr_names;
if (chosen_arch != NULL) {
mips_hwr_names = chosen_arch->hwr_names;
}
return;
}
@ -673,8 +685,9 @@ parse_mips_dis_options (const char *options)
{
const char *option_end;
if (!options)
return;
if (!options) {
return;
}
while (*options != '\0')
{
@ -687,8 +700,9 @@ parse_mips_dis_options (const char *options)
/* We know that *options is neither NUL or a comma. */
option_end = options + 1;
while (*option_end != ',' && *option_end != '\0')
option_end++;
while (*option_end != ',' && *option_end != '\0') {
option_end++;
}
parse_mips_dis_option (options, option_end - options);
@ -706,9 +720,11 @@ lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names,
{
unsigned int i;
for (i = 0; i < len; i++)
if (names[i].cp0reg == cp0reg && names[i].sel == sel)
return &names[i];
for (i = 0; i < len; i++) {
if (names[i].cp0reg == cp0reg && names[i].sel == sel) {
return &names[i];
}
}
return NULL;
}
@ -802,10 +818,11 @@ print_insn_args (const char *d,
printed. */
n = lookup_mips_cp0sel_name(mips_cp0sel_names,
mips_cp0sel_names_len, cp0reg, sel);
if (n != NULL)
(*info->fprintf_func) (info->stream, "%s", n->name);
else
(*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
if (n != NULL) {
(*info->fprintf_func) (info->stream, "%s", n->name);
} else {
(*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
}
break;
}
@ -845,10 +862,11 @@ print_insn_args (const char *d,
printed. */
n = lookup_mips_cp0sel_name(mips_cp0sel_names,
mips_cp0sel_names_len, cp0reg, sel);
if (n != NULL)
(*info->fprintf_func) (info->stream, "%s", n->name);
else
(*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
if (n != NULL) {
(*info->fprintf_func) (info->stream, "%s", n->name);
} else {
(*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
}
break;
}
@ -903,15 +921,17 @@ print_insn_args (const char *d,
case '0': /* dsp 6-bit signed immediate in bit 20 */
delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT);
if (delta & 0x20) /* test sign bit */
delta |= ~OP_MASK_DSPSFT;
if (delta & 0x20) { /* test sign bit */
delta |= ~OP_MASK_DSPSFT;
}
(*info->fprintf_func) (info->stream, "%d", delta);
break;
case ':': /* dsp 7-bit signed immediate in bit 19 */
delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7);
if (delta & 0x40) /* test sign bit */
delta |= ~OP_MASK_DSPSFT_7;
if (delta & 0x40) { /* test sign bit */
delta |= ~OP_MASK_DSPSFT_7;
}
(*info->fprintf_func) (info->stream, "%d", delta);
break;
@ -922,8 +942,9 @@ print_insn_args (const char *d,
case '@': /* dsp 10-bit signed immediate in bit 16 */
delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
if (delta & 0x200) /* test sign bit */
delta |= ~OP_MASK_IMM10;
if (delta & 0x200) { /* test sign bit */
delta |= ~OP_MASK_IMM10;
}
(*info->fprintf_func) (info->stream, "%d", delta);
break;
@ -976,8 +997,9 @@ print_insn_args (const char *d,
case 'j': /* Same as i, but sign-extended. */
case 'o':
delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
if (delta & 0x8000)
delta |= ~0xffff;
if (delta & 0x8000) {
delta |= ~0xffff;
}
(*info->fprintf_func) (info->stream, "%d",
delta);
break;
@ -1007,8 +1029,9 @@ print_insn_args (const char *d,
case 'p':
/* Sign extend the displacement. */
delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
if (delta & 0x8000)
delta |= ~0xffff;
if (delta & 0x8000) {
delta |= ~0xffff;
}
info->target = (delta << 2) + pc + INSNLEN;
(*info->print_address_func) (info->target, info);
break;
@ -1022,22 +1045,22 @@ print_insn_args (const char *d,
{
/* First check for both rd and rt being equal. */
unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
(*info->fprintf_func) (info->stream, "%s",
mips_gpr_names[reg]);
else
{
/* If one is zero use the other. */
if (reg == 0)
(*info->fprintf_func) (info->stream, "%s",
mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
(*info->fprintf_func) (info->stream, "%s",
mips_gpr_names[reg]);
else /* Bogus, result depends on processor. */
(*info->fprintf_func) (info->stream, "%s or %s",
mips_gpr_names[reg],
mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
if (reg == ((l >> OP_SH_RT) & OP_MASK_RT)) {
(*info->fprintf_func) (info->stream, "%s",
mips_gpr_names[reg]);
} else {
/* If one is zero use the other. */
if (reg == 0) {
(*info->fprintf_func) (info->stream, "%s",
mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
} else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0) {
(*info->fprintf_func) (info->stream, "%s",
mips_gpr_names[reg]);
} else { /* Bogus, result depends on processor. */
(*info->fprintf_func) (info->stream, "%s or %s",
mips_gpr_names[reg],
mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
}
}
}
break;
@ -1117,12 +1140,13 @@ print_insn_args (const char *d,
'S' format. Therefore, we only need to worry about cp0,
cp2, and cp3. */
op = (l >> OP_SH_OP) & OP_MASK_OP;
if (op == OP_OP_COP0)
(*info->fprintf_func) (info->stream, "%s",
mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
else
(*info->fprintf_func) (info->stream, "$%ld",
(l >> OP_SH_RD) & OP_MASK_RD);
if (op == OP_OP_COP0) {
(*info->fprintf_func) (info->stream, "%s",
mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
} else {
(*info->fprintf_func) (info->stream, "$%ld",
(l >> OP_SH_RD) & OP_MASK_RD);
}
break;
case 'K':
@ -1176,9 +1200,11 @@ print_insn_args (const char *d,
int fmt;
vsel &= 0x0f;
for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
if ((vsel & 1) == 0)
break;
for (fmt = 0; fmt < 3; fmt++, vsel >>= 1) {
if ((vsel & 1) == 0) {
break;
}
}
(*info->fprintf_func) (info->stream, "$v%ld[%d]",
(l >> OP_SH_FT) & OP_MASK_FT,
vsel >> 1);
@ -1244,13 +1270,12 @@ print_insn_mips (bfd_vma memaddr,
{
for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
{
if (op->pinfo == INSN_MACRO
|| (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
continue;
if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
{
mips_hash[i] = op;
break;
if (op->pinfo == INSN_MACRO || (no_aliases && (op->pinfo2 & INSN2_ALIAS))) {
continue;
}
if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP)) {
mips_hash[i] = op;
break;
}
}
}
@ -1279,39 +1304,39 @@ print_insn_mips (bfd_vma memaddr,
const char *d;
/* We always allow to disassemble the jalx instruction. */
if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
&& strcmp (op->name, "jalx"))
continue;
if (!OPCODE_IS_MEMBER (op, mips_isa, mips_processor) && strcmp (op->name, "jalx")) {
continue;
}
/* Figure out instruction type and branch delay information. */
if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
{
if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
info->insn_type = dis_jsr;
else
info->insn_type = dis_branch;
info->branch_delay_insns = 1;
if ((info->insn_type & INSN_WRITE_GPR_31) != 0) {
info->insn_type = dis_jsr;
} else {
info->insn_type = dis_branch;
}
info->branch_delay_insns = 1;
}
else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
| INSN_COND_BRANCH_LIKELY)) != 0)
{
if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
info->insn_type = dis_condjsr;
else
info->insn_type = dis_condbranch;
info->branch_delay_insns = 1;
if ((info->insn_type & INSN_WRITE_GPR_31) != 0) {
info->insn_type = dis_condjsr;
} else {
info->insn_type = dis_condbranch;
}
info->branch_delay_insns = 1;
} else if ((op->pinfo & (INSN_STORE_MEMORY | INSN_LOAD_MEMORY_DELAY)) != 0) {
info->insn_type = dis_dref;
}
else if ((op->pinfo & (INSN_STORE_MEMORY
| INSN_LOAD_MEMORY_DELAY)) != 0)
info->insn_type = dis_dref;
(*info->fprintf_func) (info->stream, "%s", op->name);
(*info->fprintf_func) (info->stream, "%s", op->name);
d = op->args;
if (d != NULL && *d != '\0')
{
(*info->fprintf_func) (info->stream, " ");
print_insn_args (d, word, memaddr, info, op);
d = op->args;
if (d != NULL && *d != '\0') {
(*info->fprintf_func) (info->stream, " ");
print_insn_args (d, word, memaddr, info, op);
}
return INSNLEN;
@ -1581,79 +1606,76 @@ print_mips16_insn_arg (char type,
if (! use_extend)
{
if (signedp && immed >= (1 << (nbits - 1)))
immed -= 1 << nbits;
immed <<= shift;
if ((type == '<' || type == '>' || type == '[' || type == ']')
&& immed == 0)
immed = 8;
if (signedp && immed >= (1 << (nbits - 1))) {
immed -= 1 << nbits;
}
immed <<= shift;
if ((type == '<' || type == '>' || type == '[' || type == ']') && immed == 0) {
immed = 8;
}
}
else
{
if (extbits == 16)
immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
else if (extbits == 15)
immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
else
immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
immed &= (1 << extbits) - 1;
if (! extu && immed >= (1 << (extbits - 1)))
immed -= 1 << extbits;
if (extbits == 16) {
immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
} else if (extbits == 15) {
immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
} else {
immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
}
immed &= (1 << extbits) - 1;
if (!extu && immed >= (1 << (extbits - 1))) {
immed -= 1 << extbits;
}
}
if (! pcrel)
(*info->fprintf_func) (info->stream, "%d", immed);
else
{
bfd_vma baseaddr;
if (!pcrel) {
(*info->fprintf_func) (info->stream, "%d", immed);
} else {
bfd_vma baseaddr;
if (branch)
{
immed *= 2;
baseaddr = memaddr + 2;
}
else if (use_extend)
baseaddr = memaddr - 2;
else
{
int status;
bfd_byte buffer[2];
if (branch) {
immed *= 2;
baseaddr = memaddr + 2;
} else if (use_extend) {
baseaddr = memaddr - 2;
} else {
int status;
bfd_byte buffer[2];
baseaddr = memaddr;
baseaddr = memaddr;
/* If this instruction is in the delay slot of a jr
/* If this instruction is in the delay slot of a jr
instruction, the base address is the address of the
jr instruction. If it is in the delay slot of jalr
instruction, the base address is the address of the
jalr instruction. This test is unreliable: we have
no way of knowing whether the previous word is
instruction or data. */
status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
info);
if (status == 0
&& (((info->endian == BFD_ENDIAN_BIG
? bfd_getb16 (buffer)
: bfd_getl16 (buffer))
& 0xf800) == 0x1800))
baseaddr = memaddr - 4;
else
{
status = (*info->read_memory_func) (memaddr - 2, buffer,
2, info);
if (status == 0
&& (((info->endian == BFD_ENDIAN_BIG
? bfd_getb16 (buffer)
: bfd_getl16 (buffer))
& 0xf81f) == 0xe800))
baseaddr = memaddr - 2;
status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
info);
if (status == 0 && (((info->endian == BFD_ENDIAN_BIG
? bfd_getb16 (buffer)
: bfd_getl16 (buffer)) &
0xf800) == 0x1800)) {
baseaddr = memaddr - 4;
} else {
status = (*info->read_memory_func) (memaddr - 2, buffer,
2, info);
if (status == 0 && (((info->endian == BFD_ENDIAN_BIG
? bfd_getb16 (buffer)
: bfd_getl16 (buffer)) &
0xf81f) == 0xe800)) {
baseaddr = memaddr - 2;
}
}
}
}
info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
if (pcrel && branch
&& info->flavour == bfd_target_unknown_flavour)
/* For gdb disassembler, maintain odd address. */
info->target |= 1;
(*info->print_address_func) (info->target, info);
info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
if (pcrel && branch && info->flavour == bfd_target_unknown_flavour) {
/* For gdb disassembler, maintain odd address. */
info->target |= 1;
}
(*info->print_address_func) (info->target, info);
}
}
break;
@ -1662,12 +1684,14 @@ print_mips16_insn_arg (char type,
{
int jalx = l & 0x400;
if (! use_extend)
extend = 0;
if (!use_extend) {
extend = 0;
}
l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
if (!jalx && info->flavour == bfd_target_unknown_flavour)
/* For gdb disassembler, maintain odd address. */
l |= 1;
if (!jalx && info->flavour == bfd_target_unknown_flavour) {
/* For gdb disassembler, maintain odd address. */
l |= 1;
}
}
info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
(*info->print_address_func) (info->target, info);
@ -1689,9 +1713,10 @@ print_mips16_insn_arg (char type,
if (amask > 0 && amask < 5)
{
(*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
if (amask > 1)
(*info->fprintf_func) (info->stream, "-%s",
mips_gpr_names[amask + 3]);
if (amask > 1) {
(*info->fprintf_func) (info->stream, "-%s",
mips_gpr_names[amask + 3]);
}
need_comma = 1;
}
@ -1707,9 +1732,10 @@ print_mips16_insn_arg (char type,
(*info->fprintf_func) (info->stream, "%s%s",
need_comma ? ", " : "",
mips_gpr_names[16]);
if (smask > 1)
(*info->fprintf_func) (info->stream, "-%s",
mips_gpr_names[smask + 15]);
if (smask > 1) {
(*info->fprintf_func) (info->stream, "-%s",
mips_gpr_names[smask + 15]);
}
need_comma = 1;
}
@ -1725,8 +1751,9 @@ print_mips16_insn_arg (char type,
{
(*info->fprintf_func) (info->stream, "%s$f0",
need_comma ? ", " : "");
if (amask == 6)
(*info->fprintf_func) (info->stream, "-$f1");
if (amask == 6) {
(*info->fprintf_func) (info->stream, "-$f1");
}
}
}
break;
@ -1742,8 +1769,9 @@ print_mips16_insn_arg (char type,
int i, j;
l = l & 0x7f;
if (use_extend)
l |= extend << 16;
if (use_extend) {
l |= extend << 16;
}
amask = (l >> 16) & 0xf;
if (amask == MIPS16_ALL_ARGS)
@ -1764,31 +1792,37 @@ print_mips16_insn_arg (char type,
if (args > 0) {
(*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
if (args > 1)
(*info->fprintf_func) (info->stream, "-%s",
mips_gpr_names[4 + args - 1]);
need_comma = 1;
if (args > 1) {
(*info->fprintf_func) (info->stream, "-%s",
mips_gpr_names[4 + args - 1]);
}
need_comma = 1;
}
framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8;
if (framesz == 0 && !use_extend)
framesz = 128;
if (framesz == 0 && !use_extend) {
framesz = 128;
}
(*info->fprintf_func) (info->stream, "%s%d",
need_comma ? ", " : "",
framesz);
if (l & 0x40) /* $ra */
(*info->fprintf_func) (info->stream, ", %s", mips_gpr_names[31]);
if (l & 0x40) { /* $ra */
(*info->fprintf_func) (info->stream, ", %s", mips_gpr_names[31]);
}
nsreg = (l >> 24) & 0x7;
smask = 0;
if (l & 0x20) /* $s0 */
smask |= 1 << 0;
if (l & 0x10) /* $s1 */
smask |= 1 << 1;
if (nsreg > 0) /* $s2-$s8 */
smask |= ((1 << nsreg) - 1) << 2;
if (l & 0x20) { /* $s0 */
smask |= 1 << 0;
}
if (l & 0x10) { /* $s1 */
smask |= 1 << 1;
}
if (nsreg > 0) { /* $s2-$s8 */
smask |= ((1 << nsreg) - 1) << 2;
}
/* Find first set static reg bit. */
for (i = 0; i < 9; i++)
@ -1798,22 +1832,25 @@ print_mips16_insn_arg (char type,
(*info->fprintf_func) (info->stream, ", %s",
mips_gpr_names[i == 8 ? 30 : (16 + i)]);
/* Skip over string of set bits. */
for (j = i; smask & (2 << j); j++)
continue;
if (j > i)
(*info->fprintf_func) (info->stream, "-%s",
mips_gpr_names[j == 8 ? 30 : (16 + j)]);
i = j + 1;
for (j = i; smask & (2 << j); j++) {
continue;
}
if (j > i) {
(*info->fprintf_func) (info->stream, "-%s",
mips_gpr_names[j == 8 ? 30 : (16 + j)]);
}
i = j + 1;
}
}
/* Statics $ax - $a3. */
if (statics == 1)
(*info->fprintf_func) (info->stream, ", %s", mips_gpr_names[7]);
else if (statics > 0)
(*info->fprintf_func) (info->stream, ", %s-%s",
mips_gpr_names[7 - statics + 1],
mips_gpr_names[7]);
if (statics == 1) {
(*info->fprintf_func) (info->stream, ", %s", mips_gpr_names[7]);
} else if (statics > 0) {
(*info->fprintf_func) (info->stream, ", %s-%s",
mips_gpr_names[7 - statics + 1],
mips_gpr_names[7]);
}
}
break;
@ -1858,10 +1895,11 @@ print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
length = 2;
if (info->endian == BFD_ENDIAN_BIG)
insn = bfd_getb16 (buffer);
else
insn = bfd_getl16 (buffer);
if (info->endian == BFD_ENDIAN_BIG) {
insn = bfd_getb16 (buffer);
} else {
insn = bfd_getl16 (buffer);
}
/* Plugin the extend opcode specially. */
use_extend = FALSE;
@ -1881,18 +1919,18 @@ print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
return -1;
}
if (info->endian == BFD_ENDIAN_BIG)
insn = bfd_getb16 (buffer);
else
insn = bfd_getl16 (buffer);
if (info->endian == BFD_ENDIAN_BIG) {
insn = bfd_getb16 (buffer);
} else {
insn = bfd_getl16 (buffer);
}
/* Check for an extend opcode followed by an extend opcode. */
if ((insn & 0xf800) == 0xf000)
{
(*info->fprintf_func) (info->stream, "extend 0x%x",
(unsigned int) extend);
info->insn_type = dis_noninsn;
return length;
/* Check for an extend opcode followed by an extend opcode. */
if ((insn & 0xf800) == 0xf000) {
(*info->fprintf_func) (info->stream, "extend 0x%x",
(unsigned int)extend);
info->insn_type = dis_noninsn;
return length;
}
length += 2;
@ -1928,17 +1966,19 @@ print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
if (status == 0)
{
use_extend = TRUE;
if (info->endian == BFD_ENDIAN_BIG)
extend = bfd_getb16 (buffer);
else
extend = bfd_getl16 (buffer);
if (info->endian == BFD_ENDIAN_BIG) {
extend = bfd_getb16 (buffer);
} else {
extend = bfd_getl16 (buffer);
}
length += 2;
}
}
(*info->fprintf_func) (info->stream, "%s", op->name);
if (op->args[0] != '\0')
(*info->fprintf_func) (info->stream, " ");
if (op->args[0] != '\0') {
(*info->fprintf_func) (info->stream, " ");
}
for (s = op->args; *s != '\0'; s++)
{
@ -1967,20 +2007,22 @@ print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
{
info->branch_delay_insns = 1;
if (info->insn_type != dis_jsr)
info->insn_type = dis_branch;
if (info->insn_type != dis_jsr) {
info->insn_type = dis_branch;
}
}
return length;
}
}
if (use_extend)
(*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
(*info->fprintf_func) (info->stream, "0x%x", insn);
info->insn_type = dis_noninsn;
if (use_extend) {
(*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
}
(*info->fprintf_func) (info->stream, "0x%x", insn);
info->insn_type = dis_noninsn;
return length;
return length;
}
/* In an environment where we do not know the symbol type of the
@ -2003,17 +2045,15 @@ _print_insn_mips (bfd_vma memaddr,
#if 1
/* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
/* Only a few tools will work this way. */
if (memaddr & 0x01)
return print_insn_mips16 (memaddr, info);
if (memaddr & 0x01) {
return print_insn_mips16 (memaddr, info);
}
#endif
#if SYMTAB_AVAILABLE
if (info->mach == bfd_mach_mips16
|| (info->flavour == bfd_target_elf_flavour
&& info->symbols != NULL
&& ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other
== STO_MIPS16)))
return print_insn_mips16 (memaddr, info);
if (info->mach == bfd_mach_mips16 || (info->flavour == bfd_target_elf_flavour && info->symbols != NULL && ((*(elf_symbol_type **)info->symbols)->internal_elf_sym.st_other == STO_MIPS16))) {
return print_insn_mips16 (memaddr, info);
}
#endif
status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
@ -2021,10 +2061,11 @@ _print_insn_mips (bfd_vma memaddr,
{
unsigned long insn;
if (endianness == BFD_ENDIAN_BIG)
insn = (unsigned long) bfd_getb32 (buffer);
else
insn = (unsigned long) bfd_getl32 (buffer);
if (endianness == BFD_ENDIAN_BIG) {
insn = (unsigned long)bfd_getb32 (buffer);
} else {
insn = (unsigned long)bfd_getl32 (buffer);
}
return print_insn_mips (memaddr, insn, info);
}
@ -2085,16 +2126,19 @@ with the -M switch (multiple options should be separated by commas):\n"));
fprintf (stream, _("\n\
For the options above, the following values are supported for \"ABI\":\n\
"));
for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++)
fprintf (stream, " %s", mips_abi_choices[i].name);
for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++) {
fprintf (stream, " %s", mips_abi_choices[i].name);
}
fprintf (stream, _("\n"));
fprintf (stream, _("\n\
For the options above, The following values are supported for \"ARCH\":\n\
"));
for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++)
if (*mips_arch_choices[i].name != '\0')
fprintf (stream, " %s", mips_arch_choices[i].name);
for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++) {
if (*mips_arch_choices[i].name != '\0') {
fprintf (stream, " %s", mips_arch_choices[i].name);
}
}
fprintf (stream, _("\n"));
fprintf (stream, _("\n"));

125
libr/asm/arch/mips/mipsasm.c
View File

@ -158,72 +158,79 @@ R_IPI int mips_assemble(const char *str, ut64 pc, ut8 *out) {
*out = 0;
*w0=*w1=*w2=*w3=0;
sscanf (s, "%31s", w0);
if (*w0)
for (i=0; ops[i].name; i++) {
if (!strcmp (ops[i].name, w0)) {
switch (ops[i].args) {
case 3: sscanf (s, "%31s %31s %31s %31s", w0, w1, w2, w3); break;
case -3: sscanf (s, "%31s %31s %31s %31s", w0, w1, w2, w3); break;
case 2: sscanf (s, "%31s %31s %31s", w0, w1, w2); break;
case -2:sscanf (s, "%31s %31s %31s", w0, w1, w2); break;
case 1: sscanf (s, "%31s %31s", w0, w1); break;
case -1: sscanf (s, "%31s %31s", w0, w1); break;
case 0: sscanf (s, "%31s", w0); break;
}
if (hasp) {
char tmp[32];
strcpy (tmp, w2);
strcpy (w2, w3);
strcpy (w3, tmp);
}
switch (ops[i].type) {
case 'R'://reg order diff per instruction 'group' - ordered to number of likelyhood to call (add > mfhi)
if (*w0) {
for (i = 0; ops[i].name; i++) {
if (!strcmp (ops[i].name, w0)) {
switch (ops[i].args) {
case 3: return mips_r (out, 0, getreg (w2), getreg (w3), getreg (w1), 0, ops[i].n); break;
case -3:
if(ops[i].n > -1) {
return mips_r (out, 0, 0, getreg (w2), getreg (w1), getreg (w3), ops[i].n); break;
}
else {
return mips_r (out, 0, getreg (w3), getreg (w2), getreg (w1), 0, (-1 * ops[i].n) ); break;
}
case 2: return mips_r (out, 0, getreg (w1), getreg (w2), 0, 0, ops[i].n); break;
case 1: return mips_r (out, 0, getreg (w1), 0, 0, 0, ops[i].n);
case -2: return mips_r (out, 0, getreg (w2), 0, getreg (w1), 0, ops[i].n); break;
case -1: return mips_r (out, 0, 0, 0, getreg (w1), 0, ops[i].n);
case 0: return mips_r (out, 0, 0, 0, 0, 0, ops[i].n);
case 3: sscanf (s, "%31s %31s %31s %31s", w0, w1, w2, w3); break;
case -3: sscanf (s, "%31s %31s %31s %31s", w0, w1, w2, w3); break;
case 2: sscanf (s, "%31s %31s %31s", w0, w1, w2); break;
case -2: sscanf (s, "%31s %31s %31s", w0, w1, w2); break;
case 1: sscanf (s, "%31s %31s", w0, w1); break;
case -1: sscanf (s, "%31s %31s", w0, w1); break;
case 0: sscanf (s, "%31s", w0); break;
}
break;
case 'I':
case 'B':
is_branch = ops[i].type == 'B';
switch (ops[i].args) {
case 2: return mips_i (out, ops[i].n, 0, getreg (w1), getreg (w2), is_branch); break;
case 3: return mips_i (out, ops[i].n, getreg (w2), getreg (w1), getreg (w3), is_branch); break;
case -2:
if (ops[i].n > 0) {
return mips_i (out, ops[i].n, getreg (w1), 0, getreg (w2), is_branch); break;
} else {
return mips_i (out, (-1 * ops[i].n), getreg (w1), ops[i].x, getreg (w2), is_branch); break;
if (hasp) {
char tmp[32];
strcpy (tmp, w2);
strcpy (w2, w3);
strcpy (w3, tmp);
}
switch (ops[i].type) {
case 'R': //reg order diff per instruction 'group' - ordered to number of likelyhood to call (add > mfhi)
switch (ops[i].args) {
case 3: return mips_r (out, 0, getreg (w2), getreg (w3), getreg (w1), 0, ops[i].n); break;
case -3:
if (ops[i].n > -1) {
return mips_r (out, 0, 0, getreg (w2), getreg (w1), getreg (w3), ops[i].n);
break;
} else {
return mips_r (out, 0, getreg (w3), getreg (w2), getreg (w1), 0, (-1 * ops[i].n));
break;
}
case 2: return mips_r (out, 0, getreg (w1), getreg (w2), 0, 0, ops[i].n); break;
case 1: return mips_r (out, 0, getreg (w1), 0, 0, 0, ops[i].n);
case -2: return mips_r (out, 0, getreg (w2), 0, getreg (w1), 0, ops[i].n); break;
case -1: return mips_r (out, 0, 0, 0, getreg (w1), 0, ops[i].n);
case 0: return mips_r (out, 0, 0, 0, 0, 0, ops[i].n);
}
break;
case 'I':
case 'B':
is_branch = ops[i].type == 'B';
switch (ops[i].args) {
case 2: return mips_i (out, ops[i].n, 0, getreg (w1), getreg (w2), is_branch); break;
case 3: return mips_i (out, ops[i].n, getreg (w2), getreg (w1), getreg (w3), is_branch); break;
case -2:
if (ops[i].n > 0) {
return mips_i (out, ops[i].n, getreg (w1), 0, getreg (w2), is_branch);
break;
} else {
return mips_i (out, (-1 * ops[i].n), getreg (w1), ops[i].x, getreg (w2), is_branch);
break;
}
case -1: if (ops[i].n > 0) {
return mips_i (out, ops[i].n, 0, 0, getreg (w1), is_branch); break;
} else {
return mips_i (out, (-1 * ops[i].n), 0, ops[i].x, getreg (w1), is_branch); break;
case -1:
if (ops[i].n > 0) {
return mips_i (out, ops[i].n, 0, 0, getreg (w1), is_branch);
break;
} else {
return mips_i (out, (-1 * ops[i].n), 0, ops[i].x, getreg (w1), is_branch);
break;
}
}
break;
case 'J':
switch (ops[i].args) {
case 1: return mips_j (out, ops[i].n, getreg (w1)); break;
}
break;
case 'N': // nop
memset (out, 0, 4);
return 4;
}
break;
case 'J':
switch (ops[i].args) {
case 1: return mips_j (out, ops[i].n, getreg (w1)); break;
}
break;
case 'N': // nop
memset (out, 0, 4);
return 4;
return -1;
}
return -1;
}
}
free (s);

7
libr/asm/arch/msp430/msp430_disas.c
View File

@ -77,8 +77,11 @@ static void remove_first_operand(struct msp430_cmd *cmd)
static void remove_second_operand(struct msp430_cmd *cmd)
{
if (strchr(cmd->operands, ','))
*strchr(cmd->operands, ',') = '\0';
if (strchr (cmd->operands, ',')) {
{
*strchr (cmd->operands, ',') = '\0';
}
}
}
/* TODO: This is ugly as hell */

185
libr/asm/arch/nios/gnu/nios2-dis.c
View File

@ -59,41 +59,39 @@ nios2_init_opcode_hash (void)
unsigned int i;
register const struct nios2_opcode *op;
for (i = 0; i <= OP_MASK_OP; ++i)
nios2_hash[0] = NULL;
for (i = 0; i <= OP_MASK_OP; i++)
for (op = nios2_opcodes; op < &nios2_opcodes[NUMOPCODES]; op++)
{
nios2_opcode_hash *new_hash;
nios2_opcode_hash **bucket = NULL;
for (i = 0; i <= OP_MASK_OP; ++i) {
nios2_hash[0] = NULL;
}
for (i = 0; i <= OP_MASK_OP; i++) {
for (op = nios2_opcodes; op < &nios2_opcodes[NUMOPCODES]; op++) {
nios2_opcode_hash *new_hash;
nios2_opcode_hash **bucket = NULL;
if ((op->pinfo & NIOS2_INSN_MACRO) == NIOS2_INSN_MACRO)
{
if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP)
&& (op->pinfo & (NIOS2_INSN_MACRO_MOV | NIOS2_INSN_MACRO_MOVI)
& 0x7fffffff))
bucket = &(nios2_ps_hash[i]);
}
else if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
bucket = &(nios2_hash[i]);
if ((op->pinfo & NIOS2_INSN_MACRO) == NIOS2_INSN_MACRO) {
if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP) && (op->pinfo & (NIOS2_INSN_MACRO_MOV | NIOS2_INSN_MACRO_MOVI) & 0x7fffffff)) {
bucket = &(nios2_ps_hash[i]);
}
} else if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP)) {
bucket = &(nios2_hash[i]);
}
if (bucket)
{
new_hash =
(nios2_opcode_hash *) malloc (sizeof (nios2_opcode_hash));
if (!new_hash)
{
fprintf (stderr,
"error allocating memory...broken disassembler\n");
abort ();
}
new_hash->opcode = op;
new_hash->next = NULL;
while (*bucket)
bucket = &((*bucket)->next);
*bucket = new_hash;
if (bucket) {
new_hash =
(nios2_opcode_hash *)malloc (sizeof (nios2_opcode_hash));
if (!new_hash) {
fprintf (stderr,
"error allocating memory...broken disassembler\n");
abort ();
}
new_hash->opcode = op;
new_hash->next = NULL;
while (*bucket) {
bucket = &((*bucket)->next);
}
*bucket = new_hash;
}
}
}
}
nios2_hash_init = 1;
#ifdef DEBUG_HASHTABLE
for (i = 0; i <= OP_MASK_OP; ++i)
@ -130,20 +128,25 @@ nios2_find_opcode_hash (unsigned long opcode)
nios2_opcode_hash *entry;
/* Build a hash table to shorten the search time. */
if (!nios2_hash_init)
nios2_init_opcode_hash ();
if (!nios2_hash_init) {
nios2_init_opcode_hash ();
}
/* First look in the pseudo-op hashtable. */
for (entry = nios2_ps_hash[(opcode >> OP_SH_OP) & OP_MASK_OP];
entry; entry = entry->next)
if (entry->opcode->match == (opcode & entry->opcode->mask))
return entry->opcode;
entry; entry = entry->next) {
if (entry->opcode->match == (opcode & entry->opcode->mask)) {
return entry->opcode;
}
}
/* Otherwise look in the main hashtable. */
for (entry = nios2_hash[(opcode >> OP_SH_OP) & OP_MASK_OP];
entry; entry = entry->next)
if (entry->opcode->match == (opcode & entry->opcode->mask))
return entry->opcode;
entry; entry = entry->next) {
if (entry->opcode->match == (opcode & entry->opcode->mask)) {
return entry->opcode;
}
}
return NULL;
}
@ -161,12 +164,12 @@ nios2_coprocessor_regs (void)
if (!cached)
{
int i;
for (i = NUMREGNAMES; i < nios2_num_regs; i++)
if (!strcmp (nios2_regs[i].name, "c0"))
{
cached = nios2_regs + i;
break;
}
for (i = NUMREGNAMES; i < nios2_num_regs; i++) {
if (!strcmp (nios2_regs[i].name, "c0")) {
cached = nios2_regs + i;
break;
}
}
assert (cached);
}
return cached;
@ -181,12 +184,12 @@ nios2_control_regs (void)
if (!cached)
{
int i;
for (i = NUMREGNAMES; i < nios2_num_regs; i++)
if (!strcmp (nios2_regs[i].name, "status"))
{
cached = nios2_regs + i;
break;
}
for (i = NUMREGNAMES; i < nios2_num_regs; i++) {
if (!strcmp (nios2_regs[i].name, "status")) {
cached = nios2_regs + i;
break;
}
}
assert (cached);
}
return cached;
@ -213,44 +216,47 @@ nios2_print_insn_arg (const char *argptr,
case 'd':
i = GET_INSN_FIELD (RRD, opcode);
if (GET_INSN_FIELD (OP, opcode) == OP_MATCH_CUSTOM
&& GET_INSN_FIELD (CUSTOM_C, opcode) == 0)
reg_base = nios2_coprocessor_regs ();
else
reg_base = nios2_regs;
if (GET_INSN_FIELD (OP, opcode) == OP_MATCH_CUSTOM && GET_INSN_FIELD (CUSTOM_C, opcode) == 0) {
reg_base = nios2_coprocessor_regs ();
} else {
reg_base = nios2_regs;
}
if (i < NUMREGNAMES)
(*info->fprintf_func) (info->stream, "%s", reg_base[i].name);
else
(*info->fprintf_func) (info->stream, "unknown");
if (i < NUMREGNAMES) {
(*info->fprintf_func) (info->stream, "%s", reg_base[i].name);
} else {
(*info->fprintf_func) (info->stream, "unknown");
}
break;
case 's':
i = GET_INSN_FIELD (RRS, opcode);
if (GET_INSN_FIELD (OP, opcode) == OP_MATCH_CUSTOM
&& GET_INSN_FIELD (CUSTOM_A, opcode) == 0)
reg_base = nios2_coprocessor_regs ();
else
reg_base = nios2_regs;
if (GET_INSN_FIELD (OP, opcode) == OP_MATCH_CUSTOM && GET_INSN_FIELD (CUSTOM_A, opcode) == 0) {
reg_base = nios2_coprocessor_regs ();
} else {
reg_base = nios2_regs;
}
if (i < NUMREGNAMES)
(*info->fprintf_func) (info->stream, "%s", reg_base[i].name);
else
(*info->fprintf_func) (info->stream, "unknown");
if (i < NUMREGNAMES) {
(*info->fprintf_func) (info->stream, "%s", reg_base[i].name);
} else {
(*info->fprintf_func) (info->stream, "unknown");
}
break;
case 't':
i = GET_INSN_FIELD (RRT, opcode);
if (GET_INSN_FIELD (OP, opcode) == OP_MATCH_CUSTOM
&& GET_INSN_FIELD (CUSTOM_B, opcode) == 0)
reg_base = nios2_coprocessor_regs ();
else
reg_base = nios2_regs;
if (GET_INSN_FIELD (OP, opcode) == OP_MATCH_CUSTOM && GET_INSN_FIELD (CUSTOM_B, opcode) == 0) {
reg_base = nios2_coprocessor_regs ();
} else {
reg_base = nios2_regs;
}
if (i < NUMREGNAMES)
(*info->fprintf_func) (info->stream, "%s", reg_base[i].name);
else
(*info->fprintf_func) (info->stream, "unknown");
if (i < NUMREGNAMES) {
(*info->fprintf_func) (info->stream, "%s", reg_base[i].name);
} else {
(*info->fprintf_func) (info->stream, "unknown");
}
break;
case 'i':
/* 16-bit signed immediate. */
@ -344,12 +350,12 @@ nios2_disassemble (bfd_vma address, unsigned long opcode,
{
(*info->fprintf_func) (info->stream, "nop");
is_nop = TRUE;
}
else
(*info->fprintf_func) (info->stream, "%s", op->name);
}
else
(*info->fprintf_func) (info->stream, "%s", op->name);
} else {
(*info->fprintf_func) (info->stream, "%s", op->name);
}
} else {
(*info->fprintf_func) (info->stream, "%s", op->name);
}
if (!is_nop)
{
@ -395,10 +401,11 @@ print_insn_nios2 (bfd_vma address, disassemble_info *info,
if (status == 0)
{
unsigned long insn;
if (endianness == BFD_ENDIAN_BIG)
insn = (unsigned long) bfd_getb32 (buffer);
else
insn = (unsigned long) bfd_getl32 (buffer);
if (endianness == BFD_ENDIAN_BIG) {
insn = (unsigned long)bfd_getb32 (buffer);
} else {
insn = (unsigned long)bfd_getl32 (buffer);
}
status = nios2_disassemble (address, insn, info);
}
else

4
libr/asm/arch/pic/pic_pic18.c
View File

@ -121,7 +121,9 @@ int pic_pic18_disassemble(RAsmOp *op, char *opbuf, const ut8 *b, int blen) {
const char *buf_asm = "invalid";
strcpy (opbuf, buf_asm);
for (i = 0;ops[i].opmin != (ops[i].opmin & instr) || ops[i].opmax != (ops[i].opmax | instr); i++);
for (i = 0; ops[i].opmin != (ops[i].opmin & instr) || ops[i].opmax != (ops[i].opmax | instr); i++) {
;
}
if (ops[i].opmin == 0 && ops[i].opmax == 0xffff) {
strcpy (opbuf, ops[i].name);
op->size = 2;

374
libr/asm/arch/ppc/gnu/ppc-dis.c
View File

@ -76,83 +76,67 @@ powerpc_init_dialect (struct disassemble_info *info)
ppc_cpu_t dialect = PPC_OPCODE_PPC;
struct dis_private *priv = calloc (sizeof (*priv), 1);
if (priv == NULL)
return FALSE;
if (priv == NULL) {
return FALSE;
}
if (BFD_DEFAULT_TARGET_SIZE == 64)
dialect |= PPC_OPCODE_64;
if (BFD_DEFAULT_TARGET_SIZE == 64) {
dialect |= PPC_OPCODE_64;
}
if (info->disassembler_options
&& strstr (info->disassembler_options, "ppcps") != NULL)
dialect |= PPC_OPCODE_PPCPS;
else if (info->disassembler_options
&& strstr (info->disassembler_options, "booke") != NULL)
dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_BOOKE64;
else if ((info->mach == bfd_mach_ppc_e500mc)
|| (info->disassembler_options
&& strstr (info->disassembler_options, "e500mc") != NULL))
dialect |= (PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI | PPC_OPCODE_E500MC);
else if ((info->mach == bfd_mach_ppc_e500)
|| (info->disassembler_options
&& strstr (info->disassembler_options, "e500") != NULL))
dialect |= (PPC_OPCODE_BOOKE
| PPC_OPCODE_SPE | PPC_OPCODE_ISEL
| PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI | PPC_OPCODE_E500MC);
else if (info->disassembler_options
&& strstr (info->disassembler_options, "efs") != NULL)
dialect |= PPC_OPCODE_EFS;
else if (info->disassembler_options
&& strstr (info->disassembler_options, "e300") != NULL)
dialect |= PPC_OPCODE_E300 | PPC_OPCODE_CLASSIC | PPC_OPCODE_COMMON;
else if (info->disassembler_options
&& (strstr (info->disassembler_options, "440") != NULL
|| strstr (info->disassembler_options, "464") != NULL))
dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_32
| PPC_OPCODE_440 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI;
else
dialect |= (PPC_OPCODE_403 | PPC_OPCODE_601 | PPC_OPCODE_CLASSIC
| PPC_OPCODE_COMMON | PPC_OPCODE_ALTIVEC);
if (info->disassembler_options && strstr (info->disassembler_options, "ppcps") != NULL) {
dialect |= PPC_OPCODE_PPCPS;
} else if (info->disassembler_options && strstr (info->disassembler_options, "booke") != NULL) {
dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_BOOKE64;
} else if ((info->mach == bfd_mach_ppc_e500mc) || (info->disassembler_options && strstr (info->disassembler_options, "e500mc") != NULL)) {
dialect |= (PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI | PPC_OPCODE_E500MC);
} else if ((info->mach == bfd_mach_ppc_e500) || (info->disassembler_options && strstr (info->disassembler_options, "e500") != NULL)) {
dialect |= (PPC_OPCODE_BOOKE | PPC_OPCODE_SPE | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI | PPC_OPCODE_E500MC);
} else if (info->disassembler_options && strstr (info->disassembler_options, "efs") != NULL) {
dialect |= PPC_OPCODE_EFS;
} else if (info->disassembler_options && strstr (info->disassembler_options, "e300") != NULL) {
dialect |= PPC_OPCODE_E300 | PPC_OPCODE_CLASSIC | PPC_OPCODE_COMMON;
} else if (info->disassembler_options && (strstr (info->disassembler_options, "440") != NULL || strstr (info->disassembler_options, "464") != NULL)) {
dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_32 | PPC_OPCODE_440 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI;
} else {
dialect |= (PPC_OPCODE_403 | PPC_OPCODE_601 | PPC_OPCODE_CLASSIC | PPC_OPCODE_COMMON | PPC_OPCODE_ALTIVEC);
}
if (info->disassembler_options
&& strstr (info->disassembler_options, "power4") != NULL)
dialect |= PPC_OPCODE_POWER4;
if (info->disassembler_options && strstr (info->disassembler_options, "power4") != NULL) {
dialect |= PPC_OPCODE_POWER4;
}
if (info->disassembler_options
&& strstr (info->disassembler_options, "power5") != NULL)
dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5;
if (info->disassembler_options && strstr (info->disassembler_options, "power5") != NULL) {
dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5;
}
if (info->disassembler_options
&& strstr (info->disassembler_options, "cell") != NULL)
dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC;
if (info->disassembler_options && strstr (info->disassembler_options, "cell") != NULL) {
dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC;
}
if (info->disassembler_options
&& strstr (info->disassembler_options, "power6") != NULL)
dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
| PPC_OPCODE_ALTIVEC;
if (info->disassembler_options && strstr (info->disassembler_options, "power6") != NULL) {
dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC;
}
if (info->disassembler_options
&& strstr (info->disassembler_options, "power7") != NULL)
dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
| PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX;
if (info->disassembler_options && strstr (info->disassembler_options, "power7") != NULL) {
dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX;
}
if (info->disassembler_options
&& strstr (info->disassembler_options, "vsx") != NULL)
dialect |= PPC_OPCODE_VSX;
if (info->disassembler_options && strstr (info->disassembler_options, "vsx") != NULL) {
dialect |= PPC_OPCODE_VSX;
}
if (info->disassembler_options
&& strstr (info->disassembler_options, "any") != NULL)
dialect |= PPC_OPCODE_ANY;
if (info->disassembler_options && strstr (info->disassembler_options, "any") != NULL) {
dialect |= PPC_OPCODE_ANY;
}
if (info->disassembler_options)
{
if (strstr (info->disassembler_options, "32") != NULL)
dialect &= ~PPC_OPCODE_64;
else if (strstr (info->disassembler_options, "64") != NULL)
dialect |= PPC_OPCODE_64;
if (strstr (info->disassembler_options, "32") != NULL) {
dialect &= ~PPC_OPCODE_64;
} else if (strstr (info->disassembler_options, "64") != NULL) {
dialect |= PPC_OPCODE_64;
}
}
info->private_data = priv;
@ -166,9 +150,10 @@ powerpc_init_dialect (struct disassemble_info *info)
int
print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
{
if (info->private_data == NULL && !powerpc_init_dialect (info))
return -1;
return print_insn_powerpc (memaddr, info, 1, POWERPC_DIALECT(info));
if (info->private_data == NULL && !powerpc_init_dialect (info)) {
return -1;
}
return print_insn_powerpc (memaddr, info, 1, POWERPC_DIALECT (info));
}
/* Print a little endian PowerPC instruction. */
@ -176,9 +161,10 @@ print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
int
print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
{
if (info->private_data == NULL && !powerpc_init_dialect (info))
return -1;
return print_insn_powerpc (memaddr, info, 0, POWERPC_DIALECT(info));
if (info->private_data == NULL && !powerpc_init_dialect (info)) {
return -1;
}
return print_insn_powerpc (memaddr, info, 0, POWERPC_DIALECT (info));
}
/* Print a POWER (RS/6000) instruction. */
@ -198,22 +184,20 @@ operand_value_powerpc (const struct powerpc_operand *operand,
long value;
int invalid;
/* Extract the value from the instruction. */
if (operand->extract)
value = (*operand->extract) (insn, dialect, &invalid);
else
{
value = (insn >> operand->shift) & operand->bitm;
if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
{
/* BITM is always some number of zeros followed by some
if (operand->extract) {
value = (*operand->extract) (insn, dialect, &invalid);
} else {
value = (insn >> operand->shift) & operand->bitm;
if ((operand->flags & PPC_OPERAND_SIGNED) != 0) {
/* BITM is always some number of zeros followed by some
number of ones, followed by some numer of zeros. */
unsigned long top = operand->bitm;
/* top & -top gives the rightmost 1 bit, so this
unsigned long top = operand->bitm;
/* top & -top gives the rightmost 1 bit, so this
fills in any trailing zeros. */
top |= (top & -top) - 1;
top &= ~(top >> 1);
value = (value ^ top) - top;
}
top |= (top & -top) - 1;
top &= ~(top >> 1);
value = (value ^ top) - top;
}
}
return value;
@ -230,10 +214,9 @@ skip_optional_operands (const unsigned char *opindex,
for (; *opindex != 0; opindex++)
{
operand = &powerpc_operands[*opindex];
if ((operand->flags & PPC_OPERAND_NEXT) != 0
|| ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
&& operand_value_powerpc (operand, insn, dialect) != 0))
return 0;
if ((operand->flags & PPC_OPERAND_NEXT) != 0 || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0 && operand_value_powerpc (operand, insn, dialect) != 0)) {
return 0;
}
}
return 1;
@ -261,17 +244,18 @@ print_insn_powerpc (bfd_vma memaddr,
return -1;
}
if (bigendian)
insn = __bfd_getb32 (buffer);
else
insn = __bfd_getl32 (buffer);
if (bigendian) {
insn = __bfd_getb32 (buffer);
} else {
insn = __bfd_getl32 (buffer);
}
/* Get the major opcode of the instruction. */
op = PPC_OP (insn);
/* Get the major opcode of the instruction. */
op = PPC_OP (insn);
/* Find the first match in the opcode table. We could speed this up
/* Find the first match in the opcode table. We could speed this up
a bit by doing a binary search on the major opcode. */
opcode_end = powerpc_opcodes + powerpc_num_opcodes;
opcode_end = powerpc_opcodes + powerpc_num_opcodes;
again:
for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++)
{
@ -284,14 +268,16 @@ print_insn_powerpc (bfd_vma memaddr,
int skip_optional;
table_op = PPC_OP (opcode->opcode);
if (op < table_op)
break;
if (op > table_op)
continue;
if (op < table_op) {
break;
}
if (op > table_op) {
continue;
}
if ((insn & opcode->mask) != opcode->opcode
|| (opcode->flags & dialect) == 0)
continue;
if ((insn & opcode->mask) != opcode->opcode || (opcode->flags & dialect) == 0) {
continue;
}
/* Make two passes over the operands. First see if any of them
have extraction functions, and, if they do, make sure the
@ -300,107 +286,105 @@ print_insn_powerpc (bfd_vma memaddr,
for (opindex = opcode->operands; *opindex != 0; opindex++)
{
operand = powerpc_operands + *opindex;
if (operand->extract)
(*operand->extract) (insn, dialect, &invalid);
if (operand->extract) {
(*operand->extract) (insn, dialect, &invalid);
}
}
if (invalid) {
continue;
}
if (invalid)
continue;
/* The instruction is valid. */
if (opcode->operands[0] != 0)
(*info->fprintf_func) (info->stream, "%s ", opcode->name);
else
(*info->fprintf_func) (info->stream, "%s", opcode->name);
/* The instruction is valid. */
if (opcode->operands[0] != 0) {
(*info->fprintf_func) (info->stream, "%s ", opcode->name);
} else {
(*info->fprintf_func) (info->stream, "%s", opcode->name);
}
/* Now extract and print the operands. */
need_comma = 0;
need_paren = 0;
skip_optional = -1;
for (opindex = opcode->operands; *opindex != 0; opindex++)
{
long value;
/* Now extract and print the operands. */
need_comma = 0;
need_paren = 0;
skip_optional = -1;
for (opindex = opcode->operands; *opindex != 0; opindex++) {
long value;
operand = powerpc_operands + *opindex;
operand = powerpc_operands + *opindex;
/* Operands that are marked FAKE are simply ignored. We
/* Operands that are marked FAKE are simply ignored. We
already made sure that the extract function considered
the instruction to be valid. */
if ((operand->flags & PPC_OPERAND_FAKE) != 0)
continue;
/* If all of the optional operands have the value zero,
then don't print any of them. */
if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
{
if (skip_optional < 0)
skip_optional = skip_optional_operands (opindex, insn,
dialect);
if (skip_optional)
continue;
}
value = operand_value_powerpc (operand, insn, dialect);
if (need_comma)
{
(*info->fprintf_func) (info->stream, ", ");
need_comma = 0;
}
/* Print the operand as directed by the flags. */
if ((operand->flags & PPC_OPERAND_GPR) != 0
|| ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
(*info->fprintf_func) (info->stream, "r%ld", value);
else if ((operand->flags & PPC_OPERAND_FPR) != 0)
(*info->fprintf_func) (info->stream, "f%ld", value);
else if ((operand->flags & PPC_OPERAND_VR) != 0)
(*info->fprintf_func) (info->stream, "v%ld", value);
else if ((operand->flags & PPC_OPERAND_VSR) != 0)
(*info->fprintf_func) (info->stream, "vs%ld", value);
else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
(*info->print_address_func) (memaddr + value, info);
else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
(*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
else if ((operand->flags & PPC_OPERAND_CR) == 0
|| (dialect & PPC_OPCODE_PPC) == 0)
(*info->fprintf_func) (info->stream, "%ld", value);
else if ((operand->flags & PPC_OPERAND_FSL) != 0)
(*info->fprintf_func) (info->stream, "fsl%ld", value);
else if ((operand->flags & PPC_OPERAND_FCR) != 0)
(*info->fprintf_func) (info->stream, "fcr%ld", value);
else if ((operand->flags & PPC_OPERAND_UDI) != 0)
(*info->fprintf_func) (info->stream, "%ld", value);
else
{
if (operand->bitm == 7)
(*info->fprintf_func) (info->stream, "cr%ld", value);
else
{
static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
int cr;
int cc;
cr = value >> 2;
if (cr != 0)
(*info->fprintf_func) (info->stream, "4*cr%d+", cr);
cc = value & 3;
(*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
if ((operand->flags & PPC_OPERAND_FAKE) != 0) {
continue;
}
}
if (need_paren)
{
(*info->fprintf_func) (info->stream, ")");
need_paren = 0;
}
/* If all of the optional operands have the value zero,
then don't print any of them. */
if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0) {
if (skip_optional < 0) {
skip_optional = skip_optional_operands (opindex, insn,
dialect);
}
if (skip_optional) {
continue;
}
}
if ((operand->flags & PPC_OPERAND_PARENS) == 0)
need_comma = 1;
else
{
(*info->fprintf_func) (info->stream, "(");
need_paren = 1;
}
value = operand_value_powerpc (operand, insn, dialect);
if (need_comma) {
(*info->fprintf_func) (info->stream, ", ");
need_comma = 0;
}
/* Print the operand as directed by the flags. */
if ((operand->flags & PPC_OPERAND_GPR) != 0 || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0)) {
(*info->fprintf_func) (info->stream, "r%ld", value);
} else if ((operand->flags & PPC_OPERAND_FPR) != 0) {
(*info->fprintf_func) (info->stream, "f%ld", value);
} else if ((operand->flags & PPC_OPERAND_VR) != 0) {
(*info->fprintf_func) (info->stream, "v%ld", value);
} else if ((operand->flags & PPC_OPERAND_VSR) != 0) {
(*info->fprintf_func) (info->stream, "vs%ld", value);
} else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0) {
(*info->print_address_func) (memaddr + value, info);
} else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0) {
(*info->print_address_func) ((bfd_vma)value & 0xffffffff, info);
} else if ((operand->flags & PPC_OPERAND_CR) == 0 || (dialect & PPC_OPCODE_PPC) == 0) {
(*info->fprintf_func) (info->stream, "%ld", value);
} else if ((operand->flags & PPC_OPERAND_FSL) != 0) {
(*info->fprintf_func) (info->stream, "fsl%ld", value);
} else if ((operand->flags & PPC_OPERAND_FCR) != 0) {
(*info->fprintf_func) (info->stream, "fcr%ld", value);
} else if ((operand->flags & PPC_OPERAND_UDI) != 0) {
(*info->fprintf_func) (info->stream, "%ld", value);
} else {
if (operand->bitm == 7) {
(*info->fprintf_func) (info->stream, "cr%ld", value);
} else {
static const char *cbnames[4] = {"lt", "gt", "eq", "so"};
int cr;
int cc;
cr = value >> 2;
if (cr != 0) {
(*info->fprintf_func) (info->stream, "4*cr%d+", cr);
}
cc = value & 3;
(*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
}
}
if (need_paren) {
(*info->fprintf_func) (info->stream, ")");
need_paren = 0;
}
if ((operand->flags & PPC_OPERAND_PARENS) == 0) {
need_comma = 1;
} else {
(*info->fprintf_func) (info->stream, "(");
need_paren = 1;
}
}
/* We have found and printed an instruction; return. */

271
libr/asm/arch/ppc/gnu/ppc-opc.c
View File

@ -657,9 +657,10 @@ extract_bat (unsigned long insn,
ppc_cpu_t dialect ATTRIBUTE_UNUSED,
int *invalid)
{
if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
*invalid = 1;
return 0;
if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) {
*invalid = 1;
}
return 0;
}
/* The BB field in an XL form instruction when it must be the same as
@ -682,9 +683,10 @@ extract_bba (unsigned long insn,
ppc_cpu_t dialect ATTRIBUTE_UNUSED,
int *invalid)
{
if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
*invalid = 1;
return 0;
if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f)) {
*invalid = 1;
}
return 0;
}
/* The BD field in a B form instruction when the - modifier is used.
@ -712,15 +714,17 @@ insert_bdm (unsigned long insn,
{
if ((dialect & PPC_OPCODE_POWER4) == 0)
{
if ((value & 0x8000) != 0)
insn |= 1 << 21;
if ((value & 0x8000) != 0) {
insn |= 1 << 21;
}
}
else
{
if ((insn & (0x14 << 21)) == (0x04 << 21))
insn |= 0x02 << 21;
else if ((insn & (0x14 << 21)) == (0x10 << 21))
insn |= 0x08 << 21;
if ((insn & (0x14 << 21)) == (0x04 << 21)) {
insn |= 0x02 << 21;
} else if ((insn & (0x14 << 21)) == (0x10 << 21)) {
insn |= 0x08 << 21;
}
}
return insn | (value & 0xfffc);
}
@ -732,14 +736,15 @@ extract_bdm (unsigned long insn,
{
if ((dialect & PPC_OPCODE_POWER4) == 0)
{
if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
*invalid = 1;
if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0)) {
*invalid = 1;
}
}
else
{
if ((insn & (0x17 << 21)) != (0x06 << 21)
&& (insn & (0x1d << 21)) != (0x18 << 21))
*invalid = 1;
if ((insn & (0x17 << 21)) != (0x06 << 21) && (insn & (0x1d << 21)) != (0x18 << 21)) {
*invalid = 1;
}
}
return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
@ -757,15 +762,17 @@ insert_bdp (unsigned long insn,
{
if ((dialect & PPC_OPCODE_POWER4) == 0)
{
if ((value & 0x8000) == 0)
insn |= 1 << 21;
if ((value & 0x8000) == 0) {
insn |= 1 << 21;
}
}
else
{
if ((insn & (0x14 << 21)) == (0x04 << 21))
insn |= 0x03 << 21;
else if ((insn & (0x14 << 21)) == (0x10 << 21))
insn |= 0x09 << 21;
if ((insn & (0x14 << 21)) == (0x04 << 21)) {
insn |= 0x03 << 21;
} else if ((insn & (0x14 << 21)) == (0x10 << 21)) {
insn |= 0x09 << 21;
}
}
return insn | (value & 0xfffc);
}
@ -777,14 +784,15 @@ extract_bdp (unsigned long insn,
{
if ((dialect & PPC_OPCODE_POWER4) == 0)
{
if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
*invalid = 1;
if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0)) {
*invalid = 1;
}
}
else
{
if ((insn & (0x17 << 21)) != (0x07 << 21)
&& (insn & (0x1d << 21)) != (0x19 << 21))
*invalid = 1;
if ((insn & (0x17 << 21)) != (0x07 << 21) && (insn & (0x1d << 21)) != (0x19 << 21)) {
*invalid = 1;
}
}
return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
@ -823,10 +831,9 @@ valid_bo (long value, ppc_cpu_t dialect, int extract)
break;
}
/* When disassembling with -Many, accept power4 encodings too. */
if (valid
|| (dialect & PPC_OPCODE_ANY) == 0
|| !extract)
return valid;
if (valid || (dialect & PPC_OPCODE_ANY) == 0 || !extract) {
return valid;
}
}
/* Certain encodings have bits that are required to be zero.
@ -841,12 +848,13 @@ valid_bo (long value, ppc_cpu_t dialect, int extract)
1a01t
1z1zz
*/
if ((value & 0x14) == 0)
return (value & 0x1) == 0;
else if ((value & 0x14) == 0x14)
return value == 0x14;
else
return 1;
if ((value & 0x14) == 0) {
return (value & 0x1) == 0;
} else if ((value & 0x14) == 0x14) {
return value == 0x14;
} else {
return 1;
}
}
/* The BO field in a B form instruction. Warn about attempts to set
@ -858,9 +866,10 @@ insert_bo (unsigned long insn,
ppc_cpu_t dialect,
const char **errmsg)
{
if (!valid_bo (value, dialect, 0))
*errmsg = _("invalid conditional option");
return insn | ((value & 0x1f) << 21);
if (!valid_bo (value, dialect, 0)) {
*errmsg = _ ("invalid conditional option");
}
return insn | ((value & 0x1f) << 21);
}
static long
@ -871,8 +880,9 @@ extract_bo (unsigned long insn,
long value;
value = (insn >> 21) & 0x1f;
if (!valid_bo (value, dialect, 1))
*invalid = 1;
if (!valid_bo (value, dialect, 1)) {
*invalid = 1;
}
return value;
}
@ -886,12 +896,13 @@ insert_boe (unsigned long insn,
ppc_cpu_t dialect,
const char **errmsg)
{
if (!valid_bo (value, dialect, 0))
*errmsg = _("invalid conditional option");
else if ((value & 1) != 0)
*errmsg = _("attempt to set y bit when using + or - modifier");
if (!valid_bo (value, dialect, 0)) {
*errmsg = _ ("invalid conditional option");
} else if ((value & 1) != 0) {
*errmsg = _ ("attempt to set y bit when using + or - modifier");
}
return insn | ((value & 0x1f) << 21);
return insn | ((value & 0x1f) << 21);
}
static long
@ -902,8 +913,9 @@ extract_boe (unsigned long insn,
long value;
value = (insn >> 21) & 0x1f;
if (!valid_bo (value, dialect, 1))
*invalid = 1;
if (!valid_bo (value, dialect, 1)) {
*invalid = 1;
}
return value & 0x1e;
}
@ -924,31 +936,27 @@ insert_fxm (unsigned long insn,
*errmsg = _("invalid mask field");
value = 0;
}
}
}
/* If the optional field on mfcr is missing that means we want to use
the old form of the instruction that moves the whole cr. In that
case we'll have VALUE zero. There doesn't seem to be a way to
distinguish this from the case where someone writes mfcr %r3,0. */
else if (value == 0)
;
else if (value == 0) {
;
/* If only one bit of the FXM field is set, we can use the new form
/* If only one bit of the FXM field is set, we can use the new form
of the instruction, which is faster. Unlike the Power4 branch hint
encoding, this is not backward compatible. Do not generate the
new form unless -mpower4 has been given, or -many and the two
operand form of mfcr was used. */
else if ((value & -value) == value
&& ((dialect & PPC_OPCODE_POWER4) != 0
|| ((dialect & PPC_OPCODE_ANY) != 0
&& (insn & (0x3ff << 1)) == 19 << 1)))
insn |= 1 << 20;
} else if ((value & -value) == value && ((dialect & PPC_OPCODE_POWER4) != 0 || ((dialect & PPC_OPCODE_ANY) != 0 && (insn & (0x3ff << 1)) == 19 << 1))) {
insn |= 1 << 20;
/* Any other value on mfcr is an error. */
else if ((insn & (0x3ff << 1)) == 19 << 1)
{
*errmsg = _("ignoring invalid mfcr mask");
value = 0;
/* Any other value on mfcr is an error. */
} else if ((insn & (0x3ff << 1)) == 19 << 1) {
*errmsg = _ ("ignoring invalid mfcr mask");
value = 0;
}
return insn | ((value & 0xff) << 12);
@ -965,15 +973,17 @@ extract_fxm (unsigned long insn,
if ((insn & (1 << 20)) != 0)
{
/* Exactly one bit of MASK should be set. */
if (mask == 0 || (mask & -mask) != mask)
*invalid = 1;
if (mask == 0 || (mask & -mask) != mask) {
*invalid = 1;
}
}
/* Check that non-power4 form of mfcr has a zero MASK. */
else if ((insn & (0x3ff << 1)) == 19 << 1)
{
if (mask != 0)
*invalid = 1;
if (mask != 0) {
*invalid = 1;
}
}
return mask;
@ -1003,10 +1013,11 @@ insert_mbe (unsigned long insn,
mb = 0;
me = 32;
if ((uval & 1) != 0)
last = 1;
else
last = 0;
if ((uval & 1) != 0) {
last = 1;
} else {
last = 0;
}
count = 0;
/* mb: location of last 0->1 transition */
@ -1028,13 +1039,15 @@ insert_mbe (unsigned long insn,
last = 0;
}
}
if (me == 0)
me = 32;
if (me == 0) {
me = 32;
}
if (count != 2 && (count != 0 || ! last))
*errmsg = _("illegal bitmask");
if (count != 2 && (count != 0 || !last)) {
*errmsg = _ ("illegal bitmask");
}
return insn | (mb << 6) | ((me - 1) << 1);
return insn | (mb << 6) | ((me - 1) << 1);
}
static long
@ -1053,16 +1066,17 @@ extract_mbe (unsigned long insn,
if (mb < me + 1)
{
ret = 0;
for (i = mb; i <= me; i++)
ret |= 1L << (31 - i);
}
else if (mb == me + 1)
ret = ~0;
else /* (mb > me + 1) */
{
ret = ~0;
for (i = me + 1; i < mb; i++)
ret &= ~(1L << (31 - i));
for (i = mb; i <= me; i++) {
ret |= 1L << (31 - i);
}
} else if (mb == me + 1) {
ret = ~0;
} else /* (mb > me + 1) */
{
ret = ~0;
for (i = me + 1; i < mb; i++) {
ret &= ~(1L << (31 - i));
}
}
return ret;
}
@ -1098,8 +1112,9 @@ extract_nb (unsigned long insn,
long ret;
ret = (insn >> 11) & 0x1f;
if (ret == 0)
ret = 32;
if (ret == 0) {
ret = 32;
}
return ret;
}
@ -1136,10 +1151,10 @@ insert_ral (unsigned long insn,
ppc_cpu_t dialect ATTRIBUTE_UNUSED,
const char **errmsg)
{
if (value == 0
|| (unsigned long) value == ((insn >> 21) & 0x1f))
*errmsg = "invalid register operand when updating";
return insn | ((value & 0x1f) << 16);
if (value == 0 || (unsigned long)value == ((insn >> 21) & 0x1f)) {
*errmsg = "invalid register operand when updating";
}
return insn | ((value & 0x1f) << 16);
}
/* The RA field in an lmw instruction, which has special value
@ -1151,9 +1166,10 @@ insert_ram (unsigned long insn,
ppc_cpu_t dialect ATTRIBUTE_UNUSED,
const char **errmsg)
{
if ((unsigned long) value >= ((insn >> 21) & 0x1f))
*errmsg = _("index register in load range");
return insn | ((value & 0x1f) << 16);
if ((unsigned long)value >= ((insn >> 21) & 0x1f)) {
*errmsg = _ ("index register in load range");
}
return insn | ((value & 0x1f) << 16);
}
/* The RA field in the DQ form lq instruction, which has special
@ -1167,8 +1183,9 @@ insert_raq (unsigned long insn,
{
long rtvalue = (insn & RT_MASK) >> 21;
if (value == rtvalue)
*errmsg = _("source and target register operands must be different");
if (value == rtvalue) {
*errmsg = _ ("source and target register operands must be different");
}
return insn | ((value & 0x1f) << 16);
}
@ -1182,9 +1199,10 @@ insert_ras (unsigned long insn,
ppc_cpu_t dialect ATTRIBUTE_UNUSED,
const char **errmsg)
{
if (value == 0)
*errmsg = _("invalid register operand when updating");
return insn | ((value & 0x1f) << 16);
if (value == 0) {
*errmsg = _ ("invalid register operand when updating");
}
return insn | ((value & 0x1f) << 16);
}
/* The RB field in an X form instruction when it must be the same as
@ -1207,9 +1225,10 @@ extract_rbs (unsigned long insn,
ppc_cpu_t dialect ATTRIBUTE_UNUSED,
int *invalid)
{
if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
*invalid = 1;
return 0;
if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f)) {
*invalid = 1;
}
return 0;
}
/* The SH field in an MD form instruction. This is split. */
@ -1259,17 +1278,17 @@ insert_sprg (unsigned long insn,
ppc_cpu_t dialect,
const char **errmsg)
{
if (value > 7
|| (value > 3
&& (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_405)) == 0))
*errmsg = _("invalid sprg number");
if (value > 7 || (value > 3 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_405)) == 0)) {
*errmsg = _ ("invalid sprg number");
}
/* If this is mfsprg4..7 then use spr 260..263 which can be read in
/* If this is mfsprg4..7 then use spr 260..263 which can be read in
user mode. Anything else must use spr 272..279. */
if (value <= 3 || (insn & 0x100) != 0)
value |= 0x10;
if (value <= 3 || (insn & 0x100) != 0) {
value |= 0x10;
}
return insn | ((value & 0x17) << 16);
return insn | ((value & 0x17) << 16);
}
static long
@ -1281,11 +1300,9 @@ extract_sprg (unsigned long insn,
/* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
If not BOOKE or 405, then both use only 272..275. */
if ((val - 0x10 > 3 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_405)) == 0)
|| (val - 0x10 > 7 && (insn & 0x100) != 0)
|| val <= 3
|| (val & 8) != 0)
*invalid = 1;
if ((val - 0x10 > 3 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_405)) == 0) || (val - 0x10 > 7 && (insn & 0x100) != 0) || val <= 3 || (val & 8) != 0) {
*invalid = 1;
}
return val & 7;
}
@ -1305,9 +1322,10 @@ insert_tbr (unsigned long insn,
ppc_cpu_t dialect ATTRIBUTE_UNUSED,
const char **errmsg ATTRIBUTE_UNUSED)
{
if (value == 0)
value = TB;
return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
if (value == 0) {
value = TB;
}
return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
}
static long
@ -1318,8 +1336,9 @@ extract_tbr (unsigned long insn,
long ret;
ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
if (ret == TB)
ret = 0;
if (ret == TB) {
ret = 0;
}
return ret;
}
@ -1400,10 +1419,10 @@ extract_xb6s (unsigned long insn,
ppc_cpu_t dialect ATTRIBUTE_UNUSED,
int *invalid)
{
if ((((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
|| (((insn >> 2) & 0x1) != ((insn >> 1) & 0x1)))
*invalid = 1;
return 0;
if ((((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f)) || (((insn >> 2) & 0x1) != ((insn >> 1) & 0x1))) {
*invalid = 1;
}
return 0;
}
/* Macros used to form opcodes. */

317
libr/asm/arch/sh/gnu/sh-dis.c
View File

@ -80,22 +80,25 @@ print_insn_shx (bfd_vma memaddr, struct disassemble_info *info)
if (i < 16)
{
if (nibs[n] == i)
continue;
goto fail;
if (nibs[n] == i) {
continue;
}
goto fail;
}
switch (i)
{
case BRANCH_8:
imm = (nibs[2] << 4) | (nibs[3]);
if (imm & 0x80)
imm |= ~0xff;
if (imm & 0x80) {
imm |= ~0xff;
}
imm = (imm * 2) + 4 ;
goto ok;
case BRANCH_12:
imm = ((nibs[1]) << 8) | (nibs[2] << 4) | (nibs[3]);
if (imm & 0x800)
imm |= ~0xfff;
if (imm & 0x800) {
imm |= ~0xfff;
}
imm = imm * 2 + 4;
goto ok;
case IMM_4:
@ -153,151 +156,150 @@ print_insn_shx (bfd_vma memaddr, struct disassemble_info *info)
fprintf_fn (stream,"%s ", op->name);
for (n = 0; n < 3 && op->arg[n] != A_END; n++)
{
if (n && op->arg[1] != A_END)
fprintf_fn (stream, ",");
switch (op->arg[n])
{
case A_IMM:
fprintf_fn (stream, "0x%02X", (unsigned char)(imm));
break;
case A_R0:
fprintf_fn (stream, "r0");
break;
case A_REG_N:
fprintf_fn (stream, "r%d", rn);
break;
case A_INC_N:
fprintf_fn (stream, "@r%d+", rn);
break;
case A_DEC_N:
fprintf_fn (stream, "@-r%d", rn);
break;
case A_IND_N:
fprintf_fn (stream, "@r%d", rn);
break;
case A_DISP_REG_N:
fprintf_fn (stream, "@(0x%X,r%d)", imm, rn);
break;
case A_REG_M:
fprintf_fn (stream, "r%d", rm);
break;
case A_INC_M:
fprintf_fn (stream, "@r%d+", rm);
break;
case A_DEC_M:
fprintf_fn (stream, "@-r%d", rm);
break;
case A_IND_M:
fprintf_fn (stream, "@r%d", rm);
break;
case A_DISP_REG_M:
fprintf_fn (stream, "@(0x%X,r%d)", imm, rm);
break;
case A_REG_B:
fprintf_fn (stream, "r%d_bank", rb);
break;
case A_DISP_PC:
disp_pc = 1;
disp_pc_addr = imm + 4 + (memaddr & relmask);
fprintf_fn(stream, "@(0x%X,PC)",imm);
break;
case A_IND_R0_REG_N:
fprintf_fn (stream, "@(r0,r%d)", rn);
break;
case A_IND_R0_REG_M:
fprintf_fn (stream, "@(r0,r%d)", rm);
break;
case A_DISP_GBR:
fprintf_fn (stream, "@(0x%X,gbr)",imm);
break;
case A_R0_GBR:
fprintf_fn (stream, "@(r0,gbr)");
break;
case A_BDISP12:
case A_BDISP8:
(*info->print_address_func) (imm + memaddr, info);
break;
case A_SR:
fprintf_fn (stream, "sr");
break;
case A_GBR:
fprintf_fn (stream, "gbr");
break;
case A_VBR:
fprintf_fn (stream, "vbr");
break;
case A_SSR:
fprintf_fn (stream, "ssr");
break;
case A_SPC:
fprintf_fn (stream, "spc");
break;
case A_MACH:
fprintf_fn (stream, "mach");
break;
case A_MACL:
fprintf_fn (stream ,"macl");
break;
case A_PR:
fprintf_fn (stream, "pr");
break;
case A_SGR:
fprintf_fn (stream, "sgr");
break;
case A_DBR:
fprintf_fn (stream, "dbr");
break;
case FD_REG_N:
if (0)
goto d_reg_n;
case F_REG_N:
fprintf_fn (stream, "fr%d", rn);
break;
case F_REG_M:
fprintf_fn (stream, "fr%d", rm);
break;
case DX_REG_N:
if (rn & 1)
{
fprintf_fn (stream, "xd%d", rn & ~1);
break;
}
d_reg_n:
case D_REG_N:
fprintf_fn (stream, "dr%d", rn);
break;
case DX_REG_M:
if (rm & 1)
{
fprintf_fn (stream, "xd%d", rm & ~1);
break;
}
case D_REG_M:
fprintf_fn (stream, "dr%d", rm);
break;
case FPSCR_M:
case FPSCR_N:
fprintf_fn (stream, "fpscr");
break;
case FPUL_M:
case FPUL_N:
fprintf_fn (stream, "fpul");
break;
case F_FR0:
fprintf_fn (stream, "fr0");
break;
case V_REG_N:
fprintf_fn (stream, "fv%d", rn*4);
break;
case V_REG_M:
fprintf_fn (stream, "fv%d", rm*4);
break;
case XMTRX_M4:
fprintf_fn (stream, "xmtrx");
break;
default:
fprintf(stderr, "sh-dis: abort");
return 0;
if (n && op->arg[1] != A_END) {
fprintf_fn (stream, ",");
}
switch (op->arg[n]) {
case A_IMM:
fprintf_fn (stream, "0x%02X", (unsigned char)(imm));
break;
case A_R0:
fprintf_fn (stream, "r0");
break;
case A_REG_N:
fprintf_fn (stream, "r%d", rn);
break;
case A_INC_N:
fprintf_fn (stream, "@r%d+", rn);
break;
case A_DEC_N:
fprintf_fn (stream, "@-r%d", rn);
break;
case A_IND_N:
fprintf_fn (stream, "@r%d", rn);
break;
case A_DISP_REG_N:
fprintf_fn (stream, "@(0x%X,r%d)", imm, rn);
break;
case A_REG_M:
fprintf_fn (stream, "r%d", rm);
break;
case A_INC_M:
fprintf_fn (stream, "@r%d+", rm);
break;
case A_DEC_M:
fprintf_fn (stream, "@-r%d", rm);
break;
case A_IND_M:
fprintf_fn (stream, "@r%d", rm);
break;
case A_DISP_REG_M:
fprintf_fn (stream, "@(0x%X,r%d)", imm, rm);
break;
case A_REG_B:
fprintf_fn (stream, "r%d_bank", rb);
break;
case A_DISP_PC:
disp_pc = 1;
disp_pc_addr = imm + 4 + (memaddr & relmask);
fprintf_fn (stream, "@(0x%X,PC)", imm);
break;
case A_IND_R0_REG_N:
fprintf_fn (stream, "@(r0,r%d)", rn);
break;
case A_IND_R0_REG_M:
fprintf_fn (stream, "@(r0,r%d)", rm);
break;
case A_DISP_GBR:
fprintf_fn (stream, "@(0x%X,gbr)", imm);
break;
case A_R0_GBR:
fprintf_fn (stream, "@(r0,gbr)");
break;
case A_BDISP12:
case A_BDISP8:
(*info->print_address_func) (imm + memaddr, info);
break;
case A_SR:
fprintf_fn (stream, "sr");
break;
case A_GBR:
fprintf_fn (stream, "gbr");
break;
case A_VBR:
fprintf_fn (stream, "vbr");
break;
case A_SSR:
fprintf_fn (stream, "ssr");
break;
case A_SPC:
fprintf_fn (stream, "spc");
break;
case A_MACH:
fprintf_fn (stream, "mach");
break;
case A_MACL:
fprintf_fn (stream, "macl");
break;
case A_PR:
fprintf_fn (stream, "pr");
break;
case A_SGR:
fprintf_fn (stream, "sgr");
break;
case A_DBR:
fprintf_fn (stream, "dbr");
break;
case FD_REG_N:
if (0) {
goto d_reg_n;
}
case F_REG_N:
fprintf_fn (stream, "fr%d", rn);
break;
case F_REG_M:
fprintf_fn (stream, "fr%d", rm);
break;
case DX_REG_N:
if (rn & 1) {
fprintf_fn (stream, "xd%d", rn & ~1);
break;
}
d_reg_n:
case D_REG_N:
fprintf_fn (stream, "dr%d", rn);
break;
case DX_REG_M:
if (rm & 1) {
fprintf_fn (stream, "xd%d", rm & ~1);
break;
}
case D_REG_M:
fprintf_fn (stream, "dr%d", rm);
break;
case FPSCR_M:
case FPSCR_N:
fprintf_fn (stream, "fpscr");
break;
case FPUL_M:
case FPUL_N:
fprintf_fn (stream, "fpul");
break;
case F_FR0:
fprintf_fn (stream, "fr0");
break;
case V_REG_N:
fprintf_fn (stream, "fv%d", rn * 4);
break;
case V_REG_M:
fprintf_fn (stream, "fv%d", rm * 4);
break;
case XMTRX_M4:
fprintf_fn (stream, "xmtrx");
break;
default:
fprintf (stderr, "sh-dis: abort");
return 0;
}
}
@ -329,12 +331,13 @@ print_insn_shx (bfd_vma memaddr, struct disassemble_info *info)
int size;
bfd_byte bytes[4];
if (relmask == ~ (bfd_vma) 1)
size = 2;
else
size = 4;
if (relmask == ~(bfd_vma)1) {
size = 2;
} else {
size = 4;
}
//read_memory_func() is broken on ALL GNU disassemblers ! see libr/asm/p/asm_sh.c
//read_memory_func() is broken on ALL GNU disassemblers ! see libr/asm/p/asm_sh.c
status = info->read_memory_func (disp_pc_addr, bytes, size, info);
if (status != 0) {
info->memory_error_func (status, memaddr, info);

361
libr/asm/arch/sparc/gnu/sparc-dis.c
View File

@ -211,9 +211,9 @@ is_delayed_branch (unsigned long insn)
{
const sparc_opcode *opcode = op->opcode;
if ((opcode->match & insn) == opcode->match
&& (opcode->lose & insn) == 0)
return opcode->flags & F_DELAYED;
if ((opcode->match & insn) == opcode->match && (opcode->lose & insn) == 0) {
return opcode->flags & F_DELAYED;
}
}
return 0;
}
@ -274,15 +274,17 @@ compare_opcodes (const void * a, const void * b)
by comparing the bitmasks). */
if (op0->architecture & current_arch_mask)
{
if (! (op1->architecture & current_arch_mask))
return -1;
if (!(op1->architecture & current_arch_mask)) {
return -1;
}
}
else
{
if (op1->architecture & current_arch_mask)
return 1;
else if (op0->architecture != op1->architecture)
return op0->architecture - op1->architecture;
if (op1->architecture & current_arch_mask) {
return 1;
} else if (op0->architecture != op1->architecture) {
return op0->architecture - op1->architecture;
}
}
/* If a bit is set in both match and lose, there is something
@ -317,8 +319,9 @@ compare_opcodes (const void * a, const void * b)
int x0 = (match0 & x) != 0;
int x1 = (match1 & x) != 0;
if (x0 != x1)
return x1 - x0;
if (x0 != x1) {
return x1 - x0;
}
}
for (i = 0; i < 32; ++i)
@ -327,8 +330,9 @@ compare_opcodes (const void * a, const void * b)
int x0 = (lose0 & x) != 0;
int x1 = (lose1 & x) != 0;
if (x0 != x1)
return x1 - x0;
if (x0 != x1) {
return x1 - x0;
}
}
/* They are functionally equal. So as long as the opcode table is
@ -338,9 +342,10 @@ compare_opcodes (const void * a, const void * b)
{
int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS);
if (alias_diff != 0)
/* Put the one that isn't an alias first. */
return alias_diff;
if (alias_diff != 0) {
/* Put the one that isn't an alias first. */
return alias_diff;
}
}
/* Except for aliases, two "identical" instructions had
@ -348,22 +353,24 @@ compare_opcodes (const void * a, const void * b)
i = strcmp (op0->name, op1->name);
if (i)
{
if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary. */
return i;
else
fprintf (stderr,
/* xgettext:c-format */
_("Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"),
op0->name, op1->name);
if (op0->flags & F_ALIAS) { /* If they're both aliases, be arbitrary. */
return i;
} else {
fprintf (stderr,
/* xgettext:c-format */
_ ("Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"),
op0->name, op1->name);
}
}
/* Fewer arguments are preferred. */
{
int length_diff = strlen (op0->args) - strlen (op1->args);
if (length_diff != 0)
/* Put the one with fewer arguments first. */
return length_diff;
if (length_diff != 0) {
/* Put the one with fewer arguments first. */
return length_diff;
}
}
/* Put 1+i before i+1. */
@ -376,12 +383,14 @@ compare_opcodes (const void * a, const void * b)
/* There is a plus in both operands. Note that a plus
sign cannot be the first character in args,
so the following [-1]'s are valid. */
if (p0[-1] == 'i' && p1[1] == 'i')
/* op0 is i+1 and op1 is 1+i, so op1 goes first. */
return 1;
if (p0[1] == 'i' && p1[-1] == 'i')
/* op0 is 1+i and op1 is i+1, so op0 goes first. */
return -1;
if (p0[-1] == 'i' && p1[1] == 'i') {
/* op0 is i+1 and op1 is 1+i, so op1 goes first. */
return 1;
}
if (p0[1] == 'i' && p1[-1] == 'i') {
/* op0 is 1+i and op1 is i+1, so op0 goes first. */
return -1;
}
}
}
@ -390,8 +399,9 @@ compare_opcodes (const void * a, const void * b)
int i0 = strncmp (op0->args, "i,1", 3) == 0;
int i1 = strncmp (op1->args, "i,1", 3) == 0;
if (i0 ^ i1)
return i0 - i1;
if (i0 ^ i1) {
return i0 - i1;
}
}
/* They are, as far as we can tell, identical.
@ -420,8 +430,9 @@ build_hash_table (const sparc_opcode **opcode_table,
memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0]));
memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0]));
if (hash_buf != NULL)
free (hash_buf);
if (hash_buf != NULL) {
free (hash_buf);
}
hash_buf = calloc (sizeof (* hash_buf), num_opcodes);
if (!hash_buf) {
return;
@ -485,12 +496,14 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
current_arch_mask = compute_arch_mask (info->mach);
if (!opcodes_initialized)
sorted_opcodes =
xmalloc (sparc_num_opcodes * sizeof (sparc_opcode *));
if (!opcodes_initialized) {
sorted_opcodes =
xmalloc (sparc_num_opcodes * sizeof (sparc_opcode *));
}
/* Reset the sorted table so we can resort it. */
for (i = 0; i < sparc_num_opcodes; ++i)
sorted_opcodes[i] = &sparc_opcodes[i];
for (i = 0; i < sparc_num_opcodes; ++i) {
sorted_opcodes[i] = &sparc_opcodes[i];
}
qsort ((char *) sorted_opcodes, sparc_num_opcodes,
sizeof (sorted_opcodes[0]), compare_opcodes);
@ -512,10 +525,11 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
/* On SPARClite variants such as DANlite (sparc86x), instructions
are always big-endian even when the machine is in little-endian mode. */
if (info->endian == BFD_ENDIAN_BIG || info->mach == bfd_mach_sparc_sparclite)
getword = bfd_getb32;
else
getword = bfd_getl32;
if (info->endian == BFD_ENDIAN_BIG || info->mach == bfd_mach_sparc_sparclite) {
getword = bfd_getb32;
} else {
getword = bfd_getl32;
}
insn = getword (buffer);
@ -529,8 +543,9 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
const sparc_opcode *opcode = op->opcode;
/* If the insn isn't supported by the current architecture, skip it. */
if (! (opcode->architecture & current_arch_mask))
continue;
if (!(opcode->architecture & current_arch_mask)) {
continue;
}
if ((opcode->match & insn) == opcode->match
&& (opcode->lose & insn) == 0)
@ -549,19 +564,21 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
/* Do we have an `add' or `or' instruction combining an
immediate with rs1? */
if (opcode->match == 0x80102000) /* or */
imm_ored_to_rs1 = 1;
if (opcode->match == 0x80002000) /* add */
imm_added_to_rs1 = 1;
if (opcode->match == 0x80102000) { /* or */
imm_ored_to_rs1 = 1;
}
if (opcode->match == 0x80002000) { /* add */
imm_added_to_rs1 = 1;
}
if (X_RS1 (insn) != X_RD (insn)
&& strchr (opcode->args, 'r') != 0)
/* Can't do simple format if source and dest are different. */
continue;
if (X_RS2 (insn) != X_RD (insn)
&& strchr (opcode->args, 'O') != 0)
/* Can't do simple format if source and dest are different. */
continue;
if (X_RS1 (insn) != X_RD (insn) && strchr (opcode->args, 'r') != 0) {
/* Can't do simple format if source and dest are different. */
continue;
}
if (X_RS2 (insn) != X_RD (insn) && strchr (opcode->args, 'O') != 0) {
/* Can't do simple format if source and dest are different. */
continue;
}
(*info->fprintf_func) (stream, "%s", opcode->name);
@ -693,12 +710,13 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
{
int imm;
if (*s == 'i')
imm = X_SIMM (insn, 13);
else if (*s == 'I')
imm = X_SIMM (insn, 11);
else
imm = X_SIMM (insn, 10);
if (*s == 'i') {
imm = X_SIMM (insn, 13);
} else if (*s == 'I') {
imm = X_SIMM (insn, 11);
} else {
imm = X_SIMM (insn, 10);
}
/* Check to see whether we have a 1+i, and take
note of that fact.
@ -707,13 +725,15 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
we will be matching 1+i rather than i+1,
so it is OK to assume that i is after +,
not before it. */
if (found_plus)
imm_added_to_rs1 = 1;
if (found_plus) {
imm_added_to_rs1 = 1;
}
if (imm <= 9)
(*info->fprintf_func) (stream, "%d", imm);
else
(*info->fprintf_func) (stream, "%#x", imm);
if (imm <= 9) {
(*info->fprintf_func) (stream, "%d", imm);
} else {
(*info->fprintf_func) (stream, "%#x", imm);
}
}
break;
@ -722,10 +742,11 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
{
int imm = X_IMM (insn, *s == 'X' ? 5 : 6);
if (imm <= 9)
(info->fprintf_func) (stream, "%d", imm);
else
(info->fprintf_func) (stream, "%#x", (unsigned) imm);
if (imm <= 9) {
(info->fprintf_func) (stream, "%d", imm);
} else {
(info->fprintf_func) (stream, "%#x", (unsigned)imm);
}
}
break;
@ -739,21 +760,21 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
int bit = 0x40, printed_one = 0;
const char *name;
if (mask == 0)
(info->fprintf_func) (stream, "0");
else
while (bit)
{
if (mask & bit)
{
if (printed_one)
(info->fprintf_func) (stream, "|");
name = sparc_decode_membar (bit);
(info->fprintf_func) (stream, "%s", name);
printed_one = 1;
if (mask == 0) {
(info->fprintf_func) (stream, "0");
} else {
while (bit) {
if (mask & bit) {
if (printed_one) {
(info->fprintf_func) (stream, "|");
}
name = sparc_decode_membar (bit);
(info->fprintf_func) (stream, "%s", name);
printed_one = 1;
}
bit >>= 1;
}
bit >>= 1;
}
}
break;
}
@ -803,63 +824,70 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
break;
case '?':
if (X_RS1 (insn) == 31)
(*info->fprintf_func) (stream, "%%ver");
else if ((unsigned) X_RS1 (insn) < 17)
(*info->fprintf_func) (stream, "%%%s",
v9_priv_reg_names[X_RS1 (insn)]);
else
(*info->fprintf_func) (stream, "%%reserved");
break;
if (X_RS1 (insn) == 31) {
(*info->fprintf_func) (stream, "%%ver");
} else if ((unsigned)X_RS1 (insn) < 17) {
(*info->fprintf_func) (stream, "%%%s",
v9_priv_reg_names[X_RS1 (insn)]);
} else {
(*info->fprintf_func) (stream, "%%reserved");
}
break;
case '!':
if ((unsigned) X_RD (insn) < 17)
(*info->fprintf_func) (stream, "%%%s",
v9_priv_reg_names[X_RD (insn)]);
else
(*info->fprintf_func) (stream, "%%reserved");
break;
if ((unsigned)X_RD (insn) < 17) {
(*info->fprintf_func) (stream, "%%%s",
v9_priv_reg_names[X_RD (insn)]);
} else {
(*info->fprintf_func) (stream, "%%reserved");
}
break;
case '$':
if ((unsigned) X_RS1 (insn) < 32)
(*info->fprintf_func) (stream, "%%%s",
v9_hpriv_reg_names[X_RS1 (insn)]);
else
(*info->fprintf_func) (stream, "%%reserved");
break;
if ((unsigned)X_RS1 (insn) < 32) {
(*info->fprintf_func) (stream, "%%%s",
v9_hpriv_reg_names[X_RS1 (insn)]);
} else {
(*info->fprintf_func) (stream, "%%reserved");
}
break;
case '%':
if ((unsigned) X_RD (insn) < 32)
(*info->fprintf_func) (stream, "%%%s",
v9_hpriv_reg_names[X_RD (insn)]);
else
(*info->fprintf_func) (stream, "%%reserved");
break;
if ((unsigned)X_RD (insn) < 32) {
(*info->fprintf_func) (stream, "%%%s",
v9_hpriv_reg_names[X_RD (insn)]);
} else {
(*info->fprintf_func) (stream, "%%reserved");
}
break;
case '/':
if (X_RS1 (insn) < 16 || X_RS1 (insn) > 25)
(*info->fprintf_func) (stream, "%%reserved");
else
(*info->fprintf_func) (stream, "%%%s",
v9a_asr_reg_names[X_RS1 (insn)-16]);
break;
if (X_RS1 (insn) < 16 || X_RS1 (insn) > 25) {
(*info->fprintf_func) (stream, "%%reserved");
} else {
(*info->fprintf_func) (stream, "%%%s",
v9a_asr_reg_names[X_RS1 (insn) - 16]);
}
break;
case '_':
if (X_RD (insn) < 16 || X_RD (insn) > 25)
(*info->fprintf_func) (stream, "%%reserved");
else
(*info->fprintf_func) (stream, "%%%s",
v9a_asr_reg_names[X_RD (insn)-16]);
break;
if (X_RD (insn) < 16 || X_RD (insn) > 25) {
(*info->fprintf_func) (stream, "%%reserved");
} else {
(*info->fprintf_func) (stream, "%%%s",
v9a_asr_reg_names[X_RD (insn) - 16]);
}
break;
case '*':
{
const char *name = sparc_decode_prefetch (X_RD (insn));
if (name)
(*info->fprintf_func) (stream, "%s", name);
else
(*info->fprintf_func) (stream, "%ld", X_RD (insn));
if (name) {
(*info->fprintf_func) (stream, "%s", name);
} else {
(*info->fprintf_func) (stream, "%ld", X_RD (insn));
}
break;
}
@ -890,10 +918,11 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
{
const char *name = sparc_decode_asi (X_ASI (insn));
if (name)
(*info->fprintf_func) (stream, "%s", name);
else
(*info->fprintf_func) (stream, "(%ld)", X_ASI (insn));
if (name) {
(*info->fprintf_func) (stream, "%s", name);
} else {
(*info->fprintf_func) (stream, "(%ld)", X_ASI (insn));
}
break;
}
@ -941,10 +970,11 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
int val = *s == 'U' ? X_RS1 (insn) : X_RD (insn);
const char *name = sparc_decode_sparclet_cpreg (val);
if (name)
(*info->fprintf_func) (stream, "%s", name);
else
(*info->fprintf_func) (stream, "%%cpreg(%d)", val);
if (name) {
(*info->fprintf_func) (stream, "%s", name);
} else {
(*info->fprintf_func) (stream, "%%cpreg(%d)", val);
}
break;
}
}
@ -962,12 +992,12 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
unsigned long prev_insn;
int errcode;
if (memaddr >= 4)
errcode =
(*info->read_memory_func)
(memaddr - 4, buffer, sizeof (buffer), info);
else
errcode = 1;
if (memaddr >= 4) {
errcode =
(*info->read_memory_func) (memaddr - 4, buffer, sizeof (buffer), info);
} else {
errcode = 1;
}
prev_insn = getword (buffer);
@ -983,13 +1013,13 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
if (is_delayed_branch (prev_insn))
{
if (memaddr >= 8)
errcode = (*info->read_memory_func)
(memaddr - 8, buffer, sizeof (buffer), info);
else
errcode = 1;
if (memaddr >= 8) {
errcode = (*info->read_memory_func) (memaddr - 8, buffer, sizeof (buffer), info);
} else {
errcode = 1;
}
prev_insn = getword (buffer);
prev_insn = getword (buffer);
}
}
@ -1005,10 +1035,11 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
info->target =
((unsigned) 0xFFFFFFFF
& ((int) X_IMM22 (prev_insn) << 10));
if (imm_added_to_rs1)
info->target += X_SIMM (insn, 13);
else
info->target |= X_SIMM (insn, 13);
if (imm_added_to_rs1) {
info->target += X_SIMM (insn, 13);
} else {
info->target |= X_SIMM (insn, 13);
}
(*info->print_address_func) (info->target, info);
info->insn_type = dis_dref;
info->data_size = 4; /* FIXME!!! */
@ -1020,14 +1051,18 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
{
/* FIXME -- check is_annulled flag. */
(void) is_annulled;
if (opcode->flags & F_UNBR)
info->insn_type = dis_branch;
if (opcode->flags & F_CONDBR)
info->insn_type = dis_condbranch;
if (opcode->flags & F_JSR)
info->insn_type = dis_jsr;
if (opcode->flags & F_DELAYED)
info->branch_delay_insns = 1;
if (opcode->flags & F_UNBR) {
info->insn_type = dis_branch;
}
if (opcode->flags & F_CONDBR) {
info->insn_type = dis_condbranch;
}
if (opcode->flags & F_JSR) {
info->insn_type = dis_jsr;
}
if (opcode->flags & F_DELAYED) {
info->branch_delay_insns = 1;
}
}
return sizeof (buffer);

24
libr/asm/arch/sparc/gnu/sparc-opc.c
View File

@ -95,9 +95,11 @@ sparc_opcode_lookup_arch (const char *name)
{
const struct sparc_opcode_arch *p;
for (p = &sparc_opcode_archs[0]; p->name; ++p)
if (strcmp (name, p->name) == 0)
return (enum sparc_opcode_arch_val) (p - &sparc_opcode_archs[0]);
for (p = &sparc_opcode_archs[0]; p->name; ++p) {
if (strcmp (name, p->name) == 0) {
return (enum sparc_opcode_arch_val) (p - &sparc_opcode_archs[0]);
}
}
return SPARC_OPCODE_ARCH_BAD;
}
@ -1843,9 +1845,11 @@ lookup_name (const arg *table, const char *name)
{
const arg *p;
for (p = table; p->name; ++p)
if (strcmp (name, p->name) == 0)
return p->value;
for (p = table; p->name; ++p) {
if (strcmp (name, p->name) == 0) {
return p->value;
}
}
return -1;
}
@ -1857,9 +1861,11 @@ lookup_value (const arg *table, int value)
{
const arg *p;
for (p = table; p->name; ++p)
if (value == p->value)
return p->name;
for (p = table; p->name; ++p) {
if (value == p->value) {
return p->name;
}
}
return NULL;
}

7
libr/asm/arch/tms320/c55x_plus/c55plus.c
View File

@ -38,8 +38,11 @@ int c55x_plus_disassemble(tms320_dasm_t *dasm, const ut8 *buf, int len) {
// opcode length
dasm->length = next_ins_pos;
ins_decoded_len = strlen(ins_decoded);
for (i = 0; i < ins_decoded_len; i++)
ins_decoded[i] = tolower((unsigned char)ins_decoded[i]);
for (i = 0; i < ins_decoded_len; i++) {
{
ins_decoded[i] = tolower ((unsigned char)ins_decoded[i]);
}
}
snprintf (dasm->syntax, sizeof(dasm->syntax), "%s", ins_decoded);
free (ins_decoded);

66
libr/asm/arch/tms320/c55x_plus/c55plus_decode.c
View File

@ -60,8 +60,9 @@ static ut32 get_ins_bits(ut32 hash_code, ut32 ins_pos, char *ins,
ut32 len, x, i;
char *op_str, *aux;
if (ins[0] == 'q')
return get_q_bits(magic_value, ins, ins_len, err_code);
if (ins[0] == 'q') {
return get_q_bits (magic_value, ins, ins_len, err_code);
}
op_str = ins_str[1 + hash_code * 4];
//printf("OPSTR => %s %d\n", ins, ins_len);
@ -83,8 +84,9 @@ static ut32 get_ins_bits(ut32 hash_code, ut32 ins_pos, char *ins,
x = len + 1;
res = (res * 2) | ((op_b >> ((1023 - len) % 8)) & 1);
if (!op_str[x])
if (!op_str[x]) {
x = 0;
}
}
if (C55PLUS_DEBUG) {
@ -245,8 +247,9 @@ static char *decode_ins(st32 hash_code, ut32 ins_pos, ut32 ins_off, ut32 *ins_le
}
}
if (C55PLUS_DEBUG)
printf("PSEUDO INS %s\n", ins);
if (C55PLUS_DEBUG) {
printf ("PSEUDO INS %s\n", ins);
}
pos = ins;
// instruction length
@ -274,8 +277,9 @@ static char *decode_ins(st32 hash_code, ut32 ins_pos, ut32 ins_off, ut32 *ins_le
token_aux[len] = '\0';
pos = aux;
if (C55PLUS_DEBUG)
printf("TOKEN AUX: %s\n", token_aux);
if (C55PLUS_DEBUG) {
printf ("TOKEN AUX: %s\n", token_aux);
}
reg = NULL;
for (i = 0; i < len; i++) {
@ -283,8 +287,9 @@ static char *decode_ins(st32 hash_code, ut32 ins_pos, ut32 ins_off, ut32 *ins_le
len = (unsigned int)(size_t)(&token_aux[i] - token_aux);
reg = &token_aux[i + 1];
if (C55PLUS_DEBUG)
printf("REG : %s\n", reg);
if (C55PLUS_DEBUG) {
printf ("REG : %s\n", reg);
}
break;
}
}
@ -306,8 +311,9 @@ static char *decode_ins(st32 hash_code, ut32 ins_pos, ut32 ins_off, ut32 *ins_le
pos++;
}
if (C55PLUS_DEBUG)
printf("RESULT DECODE: %s\n", res_decode);
if (C55PLUS_DEBUG) {
printf ("RESULT DECODE: %s\n", res_decode);
}
return res_decode;
}
@ -593,8 +599,9 @@ static char* get_token_decoded(st32 hash_code, char *ins_token, ut32 ins_token_l
sprintf(buff_aux, "-#0x%lx", (long unsigned int)ins_bits);
}
res = strdup(buff_aux);
if (!reg_arg || *reg_arg != 'm')
if (!reg_arg || *reg_arg != 'm') {
break;
}
res = strcat_dup(res, ")", 1);
res = strcat_dup("*(", res, 2);
@ -691,17 +698,21 @@ static char* get_token_decoded(st32 hash_code, char *ins_token, ut32 ins_token_l
if (reg_arg) {
if (*reg_arg == '1') {
res = get_tc2_tc1(ins_bits >> 1);
} else if (*reg_arg == '2')
res = get_tc2_tc1(ins_bits & 1);
} else res = get_tc2_tc1(ins_bits);
} else if (*reg_arg == '2') {
res = get_tc2_tc1 (ins_bits & 1);
}
} else {
res = get_tc2_tc1 (ins_bits);
}
if (!res) {
*err_code = -1;
return NULL;
}
break;
case 52:
if (ins_bits == 0)
if (ins_bits == 0) {
break;
}
if (reg_arg) {
if (*reg_arg == 'H') {
res = "hi(";
@ -766,8 +777,9 @@ static char* get_token_decoded(st32 hash_code, char *ins_token, ut32 ins_token_l
break;
case 0:
case 1:
if (!ins_bits)
if (!ins_bits) {
break;
}
if (!reg_arg) {
res = "U";
} else {
@ -775,13 +787,16 @@ static char* get_token_decoded(st32 hash_code, char *ins_token, ut32 ins_token_l
res = "uns(";
} else if (*reg_arg == ')') {
res = ")";
} else res = "<$/#>";
} else {
res = "<$/#>";
}
}
res = strdup(res);
break;
case 2:
if (!ins_bits)
if (!ins_bits) {
break;
}
if (!reg_arg) {
res = "R";
} else {
@ -789,13 +804,16 @@ static char* get_token_decoded(st32 hash_code, char *ins_token, ut32 ins_token_l
res = "rnd(";
} else if (*reg_arg == ')') {
res = ")";
} else res = "<%>";
} else {
res = "<%>";
}
}
res = strdup(res);
break;
case 12:
if (!ins_bits)
if (!ins_bits) {
break;
}
if(!reg_arg) {
res = "F";
} else {
@ -812,8 +830,9 @@ static char* get_token_decoded(st32 hash_code, char *ins_token, ut32 ins_token_l
res = strdup(res);
break;
case 29:
if (!ins_bits)
if (!ins_bits) {
break;
}
if (!reg_arg) {
res = "saturate";
} else {
@ -831,8 +850,9 @@ static char* get_token_decoded(st32 hash_code, char *ins_token, ut32 ins_token_l
res = (ins_bits != 0)? strdup("t3 = ") : NULL;
break;
case 17:
if (!ins_bits)
if (!ins_bits) {
break;
}
if (!reg_arg) {
res = "40";
} else {

25
libr/asm/arch/tms320/c55x_plus/decode_funcs.c
View File

@ -258,8 +258,9 @@ char *get_reg_pair(ut32 idx) {
default: res = NULL;
}
if(res != NULL)
res = strdup(res);
if (res != NULL) {
res = strdup (res);
}
return res;
}
@ -322,8 +323,9 @@ char *get_reg_name_3(ut32 idx) {
default: res = NULL;
}
if (res != NULL)
res = strdup(res);
if (res != NULL) {
res = strdup (res);
}
return res;
}
@ -377,8 +379,9 @@ char *get_reg_name_2(ut32 idx) {
default: res = NULL;
}
if(res != NULL)
res = strdup(res);
if (res != NULL) {
res = strdup (res);
}
return res;
}
@ -631,8 +634,9 @@ char *get_reg_name_1(ut32 idx) {
default: res = NULL;
}
if(res != NULL)
res = strdup(res);
if (res != NULL) {
res = strdup (res);
}
return res;
}
@ -846,8 +850,9 @@ char *get_status_regs_and_bits(char *reg_arg, int reg_bit) {
}
}
if(res != NULL)
res = strdup(res);
if (res != NULL) {
res = strdup (res);
}
return res;
}

1127
libr/asm/arch/tms320/c55x_plus/hashtable.c
View File

File diff suppressed because it is too large Load Diff

11
libr/asm/arch/tms320/c55x_plus/ins.c
View File

@ -50,8 +50,9 @@ ut32 get_ins_len(ut8 opcode) {
ut32 get_ins_part(ut32 pos, ut32 len) {
ut32 ret = 0;
has_failed = 0;
if (C55PLUS_DEBUG)
printf("pos => 0x%x len => %d ins_buff_len => %d\n", pos, len, ins_buff_len);
if (C55PLUS_DEBUG) {
printf ("pos => 0x%x len => %d ins_buff_len => %d\n", pos, len, ins_buff_len);
}
if ((st32)pos < 0 || pos >= ins_buff_len) {
has_failed = 1;
@ -60,9 +61,11 @@ ut32 get_ins_part(ut32 pos, ut32 len) {
for (; len > 0; --len) {
ret <<= 8;
if (pos >= ins_buff_len)
if (pos >= ins_buff_len) {
has_failed = 1;
else ret |= ins_buff[pos++];
} else {
ret |= ins_buff[pos++];
}
}
return ret;

232
libr/asm/arch/tms320/tms320_dasm.c
View File

@ -29,8 +29,9 @@ int run_f_list(tms320_dasm_t * dasm) {
ut32 temp;
insn_flag_t * flag;
if (!dasm->insn->f_list)
if (!dasm->insn->f_list) {
return 1;
}
for (flag = dasm->insn->f_list; !f_list_last(flag); flag++) {
switch (flag->v) {
@ -276,13 +277,15 @@ int run_m_list(tms320_dasm_t * dasm)
{
insn_mask_t * mask;
if (!dasm->insn->m_list)
if (!dasm->insn->m_list) {
return 1;
}
for (mask = dasm->insn->m_list; !m_list_last(mask); mask++) {
/* match bits in range [f, f + n] with mask's value */
if (get_bits(dasm->opcode64, mask->f, mask->n) != mask->v)
if (get_bits (dasm->opcode64, mask->f, mask->n) != mask->v) {
return 0;
}
}
return 1;
@ -294,8 +297,9 @@ int vreplace(char * string, const char * token, const char * fmt, va_list args)
char * pos;
pos = strstr(string, token);
if (!pos)
if (!pos) {
return 0;
}
vsnprintf(data, sizeof(data), fmt, args);
@ -566,20 +570,24 @@ const char * get_mmm_str(ut8 key, char * str)
void decode_bits(tms320_dasm_t * dasm)
{
// rounding
if (field_valid(dasm, R))
substitute(dasm->syntax, "[r]", "%s", field_value(dasm, R) ? "r" : "");
if (field_valid (dasm, R)) {
substitute (dasm->syntax, "[r]", "%s", field_value (dasm, R) ? "r" : "");
}
// unsigned
if (field_valid(dasm, u))
substitute(dasm->syntax, "[u]", "%s", field_value(dasm, u) ? "u" : "");
if (field_valid (dasm, u)) {
substitute (dasm->syntax, "[u]", "%s", field_value (dasm, u) ? "u" : "");
}
// 40 keyword
if (field_valid(dasm, g))
substitute(dasm->syntax, "[40]", "%s", field_value(dasm, g) ? "40" : "");
if (field_valid (dasm, g)) {
substitute (dasm->syntax, "[40]", "%s", field_value (dasm, g) ? "40" : "");
}
// T3 update
if (field_valid(dasm, U))
substitute(dasm->syntax, "[T3 = ]", "%s", field_value(dasm, U) ? "t3=" : "");
if (field_valid (dasm, U)) {
substitute (dasm->syntax, "[T3 = ]", "%s", field_value (dasm, U) ? "t3=" : "");
}
}
void decode_braces(tms320_dasm_t * dasm)
@ -639,96 +647,120 @@ void decode_constants(tms320_dasm_t * dasm)
{
// signed constant
if (field_valid(dasm, K8))
substitute(dasm->syntax, "K8", "0x%02X", field_value(dasm, K8));
if (field_valid(dasm, K16))
substitute(dasm->syntax, "K16", "0x%04X", be16(field_value(dasm, K16)));
if (field_valid (dasm, K8)) {
substitute (dasm->syntax, "K8", "0x%02X", field_value (dasm, K8));
}
if (field_valid (dasm, K16)) {
substitute (dasm->syntax, "K16", "0x%04X", be16 (field_value (dasm, K16)));
}
// unsigned constant
if (field_valid(dasm, k4))
substitute(dasm->syntax, "K4", "0x%01X", field_value(dasm, k4));
if (field_valid(dasm, k5))
substitute(dasm->syntax, "k5", "0x%02X", field_value(dasm, k5));
if (field_valid(dasm, k8))
substitute(dasm->syntax, "k8", "0x%02X", field_value(dasm, k8));
if (field_valid (dasm, k4)) {
substitute (dasm->syntax, "K4", "0x%01X", field_value (dasm, k4));
}
if (field_valid (dasm, k5)) {
substitute (dasm->syntax, "k5", "0x%02X", field_value (dasm, k5));
}
if (field_valid (dasm, k8)) {
substitute (dasm->syntax, "k8", "0x%02X", field_value (dasm, k8));
}
if (field_valid(dasm, k12))
substitute(dasm->syntax, "k12", "0x%03X", be16(field_value(dasm, k12)));
if (field_valid(dasm, k16))
substitute(dasm->syntax, "k16", "0x%04X", be16(field_value(dasm, k16)));
if (field_valid (dasm, k12)) {
substitute (dasm->syntax, "k12", "0x%03X", be16 (field_value (dasm, k12)));
}
if (field_valid (dasm, k16)) {
substitute (dasm->syntax, "k16", "0x%04X", be16 (field_value (dasm, k16)));
}
if (field_valid(dasm, k4) && field_valid(dasm, k3))
substitute(dasm->syntax, "k7", "0x%02X", (field_value(dasm, k3) << 4) | field_value(dasm, k4));
if (field_valid(dasm, k4) && field_valid(dasm, k5))
substitute(dasm->syntax, "k9", "0x%03X", (field_value(dasm, k5) << 4) | field_value(dasm, k4));
if (field_valid(dasm, k4) && field_valid(dasm, k8))
substitute(dasm->syntax, "k12", "0x%03X", (field_value(dasm, k8) << 4) | field_value(dasm, k4));
if (field_valid (dasm, k4) && field_valid (dasm, k3)) {
substitute (dasm->syntax, "k7", "0x%02X", (field_value (dasm, k3) << 4) | field_value (dasm, k4));
}
if (field_valid (dasm, k4) && field_valid (dasm, k5)) {
substitute (dasm->syntax, "k9", "0x%03X", (field_value (dasm, k5) << 4) | field_value (dasm, k4));
}
if (field_valid (dasm, k4) && field_valid (dasm, k8)) {
substitute (dasm->syntax, "k12", "0x%03X", (field_value (dasm, k8) << 4) | field_value (dasm, k4));
}
// dasm address label
if (field_valid(dasm, D16))
substitute(dasm->syntax, "D16", "0x%04X", be16(field_value(dasm, D16)));
if (field_valid (dasm, D16)) {
substitute (dasm->syntax, "D16", "0x%04X", be16 (field_value (dasm, D16)));
}
// immediate shift value
if (field_valid(dasm, SHFT))
substitute(dasm->syntax, "#SHFT", "0x%01X", field_value(dasm, SHFT));
if (field_valid(dasm, SHIFTW))
substitute(dasm->syntax, "#SHIFTW", "0x%02X", field_value(dasm, SHIFTW));
if (field_valid (dasm, SHFT)) {
substitute (dasm->syntax, "#SHFT", "0x%01X", field_value (dasm, SHFT));
}
if (field_valid (dasm, SHIFTW)) {
substitute (dasm->syntax, "#SHIFTW", "0x%02X", field_value (dasm, SHIFTW));
}
}
void decode_addresses(tms320_dasm_t * dasm)
{
// program address label
if (field_valid(dasm, L7))
substitute(dasm->syntax, "L7", "0x%02X", field_value(dasm, L7));
if (field_valid(dasm, L8))
substitute(dasm->syntax, "L8", "0x%02X", field_value(dasm, L8));
if (field_valid(dasm, L16))
substitute(dasm->syntax, "L16", "0x%04X", be16(field_value(dasm, L16)));
if (field_valid (dasm, L7)) {
substitute (dasm->syntax, "L7", "0x%02X", field_value (dasm, L7));
}
if (field_valid (dasm, L8)) {
substitute (dasm->syntax, "L8", "0x%02X", field_value (dasm, L8));
}
if (field_valid (dasm, L16)) {
substitute (dasm->syntax, "L16", "0x%04X", be16 (field_value (dasm, L16)));
}
// program address label
if (field_valid(dasm, l1) && field_valid(dasm, l3))
substitute(dasm->syntax, "l4", "0x%01X", (field_value(dasm, l3) << 1) | field_value(dasm, l1));
if (field_valid (dasm, l1) && field_valid (dasm, l3)) {
substitute (dasm->syntax, "l4", "0x%01X", (field_value (dasm, l3) << 1) | field_value (dasm, l1));
}
// program memory address
if (field_valid(dasm, l7))
substitute(dasm->syntax, "pmad", "0x%02X", field_value(dasm, l7));
if (field_valid(dasm, l16))
substitute(dasm->syntax, "pmad", "0x%04X", be16(field_value(dasm, l16)));
if (field_valid (dasm, l7)) {
substitute (dasm->syntax, "pmad", "0x%02X", field_value (dasm, l7));
}
if (field_valid (dasm, l16)) {
substitute (dasm->syntax, "pmad", "0x%04X", be16 (field_value (dasm, l16)));
}
// program or dasm address label
if (field_valid(dasm, P8))
substitute(dasm->syntax, "P8", "0x%02X", field_value(dasm, P8));
if (field_valid(dasm, P24))
substitute(dasm->syntax, "P24", "0x%06X", be24(field_value(dasm, P24)));
if (field_valid (dasm, P8)) {
substitute (dasm->syntax, "P8", "0x%02X", field_value (dasm, P8));
}
if (field_valid (dasm, P24)) {
substitute (dasm->syntax, "P24", "0x%06X", be24 (field_value (dasm, P24)));
}
}
void decode_swap(tms320_dasm_t * dasm)
{
char tmp[64];
if (field_valid(dasm, k6))
substitute(dasm->syntax, "SWAP ( )", get_swap_str(field_value(dasm, k6), tmp));
if (field_valid (dasm, k6)) {
substitute (dasm->syntax, "SWAP ( )", get_swap_str (field_value (dasm, k6), tmp));
}
}
void decode_relop(tms320_dasm_t * dasm)
{
if (field_valid(dasm, cc))
substitute(dasm->syntax, "RELOP", get_relop_str(field_value(dasm, cc), NULL));
if (field_valid (dasm, cc)) {
substitute (dasm->syntax, "RELOP", get_relop_str (field_value (dasm, cc), NULL));
}
}
void decode_cond(tms320_dasm_t * dasm)
{
char tmp[64];
if (field_valid(dasm, CCCCCCC))
substitute(dasm->syntax, "cond", "%s", get_cond_str(field_value(dasm, CCCCCCC), tmp));
if (field_valid (dasm, CCCCCCC)) {
substitute (dasm->syntax, "cond", "%s", get_cond_str (field_value (dasm, CCCCCCC), tmp));
}
substitute(dasm->syntax, "[label, ]", "");
}
@ -739,16 +771,19 @@ void decode_registers(tms320_dasm_t * dasm)
// transition register
if (field_valid(dasm, r))
substitute(dasm->syntax, "TRNx", "trn%d", field_value(dasm, r));
if (field_valid (dasm, r)) {
substitute (dasm->syntax, "TRNx", "trn%d", field_value (dasm, r));
}
// source and destination temporary registers
if (field_valid(dasm, ss))
substitute(dasm->syntax, "Tx", "t%d", field_value(dasm, ss));
if (field_valid (dasm, ss)) {
substitute (dasm->syntax, "Tx", "t%d", field_value (dasm, ss));
}
if (field_valid(dasm, dd))
substitute(dasm->syntax, "Tx", "t%d", field_value(dasm, dd));
if (field_valid (dasm, dd)) {
substitute (dasm->syntax, "Tx", "t%d", field_value (dasm, dd));
}
// shifted in/out bit values
@ -759,8 +794,9 @@ void decode_registers(tms320_dasm_t * dasm)
// source and destination of CRC instruction
if (field_valid(dasm, t))
substitute(dasm->syntax, "TCx", "%s", get_t_str(field_value(dasm, t), NULL));
if (field_valid (dasm, t)) {
substitute (dasm->syntax, "TCx", "%s", get_t_str (field_value (dasm, t), NULL));
}
if (field_valid(dasm, tt)) {
substitute(dasm->syntax, "TCx", "%s", get_t_str(field_value(dasm, tt) >> 0, NULL));
@ -782,10 +818,11 @@ void decode_registers(tms320_dasm_t * dasm)
// source or destination accumulator, auxiliary or temporary register
if (field_valid(dasm, FSSS) && field_valid(dasm, FDDD)) {
if (field_value(dasm, FSSS) == field_value(dasm, FDDD))
substitute(dasm->syntax, "[src,] dst", "dst");
else
substitute(dasm->syntax, "[src,] dst", "src, dst");
if (field_value (dasm, FSSS) == field_value (dasm, FDDD)) {
substitute (dasm->syntax, "[src,] dst", "dst");
} else {
substitute (dasm->syntax, "[src,] dst", "src, dst");
}
}
if (field_valid(dasm, FSSS) && field_valid(dasm, FDDD)) {
@ -823,12 +860,13 @@ void decode_registers(tms320_dasm_t * dasm)
substitute(dasm->syntax, "dst", "%s", get_freg_str(field_value(dasm, FDDD), NULL));
}
if (field_valid(dasm, XACS))
substitute(dasm->syntax, "XACsrc", "%s", get_xreg_str(field_value(dasm, XACS), NULL));
if (field_valid(dasm, XACD))
substitute(dasm->syntax, "XACdst", "%s", get_xreg_str(field_value(dasm, XACD), NULL));
if (field_valid (dasm, XACS)) {
substitute (dasm->syntax, "XACsrc", "%s", get_xreg_str (field_value (dasm, XACS), NULL));
}
if (field_valid (dasm, XACD)) {
substitute (dasm->syntax, "XACdst", "%s", get_xreg_str (field_value (dasm, XACD), NULL));
}
// source and destination accumulator registers
@ -877,8 +915,9 @@ void decode_addressing_modes(tms320_dasm_t * dasm)
{
// Cmem
if (field_valid(dasm, mm))
substitute(dasm->syntax, "Cmem", "%s", get_cmem_str(field_value(dasm, mm), NULL));
if (field_valid (dasm, mm)) {
substitute (dasm->syntax, "Cmem", "%s", get_cmem_str (field_value (dasm, mm), NULL));
}
// Xmem and Ymem
@ -952,10 +991,12 @@ static insn_item_t * finalize(tms320_dasm_t * dasm)
// add some qualifiers
if (field_value(dasm, q_lr))
replace(dasm->syntax, " ", ".lr ");
if (field_value(dasm, q_cr))
replace(dasm->syntax, " ", ".cr ");
if (field_value (dasm, q_lr)) {
replace (dasm->syntax, " ", ".lr ");
}
if (field_value (dasm, q_cr)) {
replace (dasm->syntax, " ", ".cr ");
}
return dasm->insn;
}
@ -992,14 +1033,16 @@ insn_item_t * decode_insn_head(tms320_dasm_t * dasm)
if (dasm->insn->i_list) {
dasm->insn = dasm->insn->i_list;
while (!i_list_last(dasm->insn)) {
if (run_m_list(dasm) && run_f_list(dasm))
if (run_m_list (dasm) && run_f_list (dasm)) {
break;
}
dasm->insn++;
}
}
if (!i_list_last(dasm->insn))
return decode_insn(dasm);
if (!i_list_last (dasm->insn)) {
return decode_insn (dasm);
}
return NULL;
}
@ -1058,10 +1101,12 @@ static int full_insn_size(tms320_dasm_t * dasm)
{
int qualifier_size = 0;
if (field_value(dasm, q_cr))
if (field_value (dasm, q_cr)) {
qualifier_size = 1;
if (field_value(dasm, q_lr))
}
if (field_value (dasm, q_lr)) {
qualifier_size = 1;
}
return dasm->length + qualifier_size;
}
@ -1076,18 +1121,21 @@ int tms320_dasm(tms320_dasm_t * dasm, const ut8 * stream, int len)
if (tms320_f_get_cpu(dasm) != TMS320_F_CPU_C55X_PLUS) {
if (lookup_insn_head(dasm) && decode_insn_head(dasm)) {
if (dasm->length > len)
if (dasm->length > len) {
dasm->status |= TMS320_S_INVAL;
}
}
} else {
c55x_plus_disassemble(dasm, stream, len);
}
if (strstr(dasm->syntax, "invalid"))
if (strstr (dasm->syntax, "invalid")) {
dasm->status |= TMS320_S_INVAL;
}
if (dasm->status & TMS320_S_INVAL)
strcpy(dasm->syntax, "invalid"), dasm->length = 1;
if (dasm->status & TMS320_S_INVAL) {
strcpy (dasm->syntax, "invalid"), dasm->length = 1;
}
return full_insn_size(dasm);
}

31
libr/asm/arch/tricore/gnu/cpu-tricore.c
View File

@ -85,19 +85,23 @@ bfd_default_compatible (a, b)
const bfd_arch_info_type *a;
const bfd_arch_info_type *b;
{
if (a->arch != b->arch)
return NULL;
if (a->arch != b->arch) {
return NULL;
}
if (a->bits_per_word != b->bits_per_word)
return NULL;
if (a->bits_per_word != b->bits_per_word) {
return NULL;
}
if (a->mach > b->mach)
return a;
if (a->mach > b->mach) {
return a;
}
if (b->mach > a->mach)
return b;
if (b->mach > a->mach) {
return b;
}
return a;
return a;
}
void tricore_init_arch_vars PARAMS ((unsigned long));
@ -251,10 +255,11 @@ tricore_init_arch_vars (mach)
tricore_mask_rrr2 = 0x00ff00ff;
tricore_mask_rrrr = 0x00e000ff;
tricore_mask_rrrw = 0x00e000ff;
if ((mach & bfd_mach_rider_mask) == bfd_mach_rider_2)
tricore_mask_sys = 0x0fc000ff;
else
tricore_mask_sys = 0x07c000ff;
if ((mach & bfd_mach_rider_mask) == bfd_mach_rider_2) {
tricore_mask_sys = 0x0fc000ff;
} else {
tricore_mask_sys = 0x07c000ff;
}
tricore_mask_sb = 0x00ff;
tricore_mask_sbc = 0x00ff;
tricore_mask_sbr = 0x00ff;

1591
libr/asm/arch/tricore/gnu/tricore-dis.c
View File

File diff suppressed because it is too large Load Diff

9
libr/asm/arch/v810/v810_disas.c
View File

@ -272,8 +272,9 @@ static int decode_bit_op(const ut16 instr, struct v810_cmd *cmd) {
static int decode_extended(const ut16 word1, const ut16 word2, struct v810_cmd *cmd) {
ut8 subop = OPCODE(word2);
if (subop > 0xC)
if (subop > 0xC) {
return -1;
}
snprintf (cmd->instr, V810_INSTR_MAXLEN - 1, "%s",
ext_instrs[subop]);
@ -310,8 +311,9 @@ int v810_decode_command(const ut8 *instr, int len, struct v810_cmd *cmd) {
ut16 word2 = 0;
word1 = r_read_le16 (instr);
if (len >= 4)
if (len >= 4) {
word2 = r_read_le16 (instr + 2);
}
switch (OPCODE(word1)) {
case V810_MOV:
@ -389,8 +391,9 @@ int v810_decode_command(const ut8 *instr, int len, struct v810_cmd *cmd) {
}
}
if ((ret > 0) && (len < ret))
if ((ret > 0) && (len < ret)) {
ret = -1;
}
return ret;
}

113
libr/asm/arch/vax/vax-dis.c
View File

@ -105,9 +105,9 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
{
(*info->memory_error_func) (status, start, info);
longjmp (priv->bailout, 1);
}
else
priv->max_fetched = addr;
} else {
priv->max_fetched = addr;
}
return 1;
}
@ -151,11 +151,12 @@ print_insn_mode (const char *d,
case 0x10:
case 0x20:
case 0x30: /* Literal mode $number. */
if (d[1] == 'd' || d[1] == 'f' || d[1] == 'g' || d[1] == 'h')
(*info->fprintf_func) (info->stream, "$0x%x [%c-float]", mode, d[1]);
else
(*info->fprintf_func) (info->stream, "$0x%x", mode);
break;
if (d[1] == 'd' || d[1] == 'f' || d[1] == 'g' || d[1] == 'h') {
(*info->fprintf_func) (info->stream, "$0x%x [%c-float]", mode, d[1]);
} else {
(*info->fprintf_func) (info->stream, "$0x%x", mode);
}
break;
case 0x40: /* Index: base-addr[Rn] */
p += print_insn_mode (d, size, p0 + 1, addr + 1, info);
(*info->fprintf_func) (info->stream, "[%s]", reg_names[reg]);
@ -189,55 +190,61 @@ print_insn_mode (const char *d,
}
else
{
for (i = 0; i < size; i++)
(*info->fprintf_func) (info->stream, "%02x",
p[size - i - 1]);
(*info->fprintf_func) (info->stream, " [%c-float]", d[1]);
for (i = 0; i < size; i++) {
(*info->fprintf_func) (info->stream, "%02x",
p[size - i - 1]);
}
(*info->fprintf_func) (info->stream, " [%c-float]", d[1]);
}
}
else
{
for (i = 0; i < size; i++)
(*info->fprintf_func) (info->stream, "%02x", p[size - i - 1]);
for (i = 0; i < size; i++) {
(*info->fprintf_func) (info->stream, "%02x", p[size - i - 1]);
}
}
p += size;
}
else
(*info->fprintf_func) (info->stream, "(%s)+", reg_names[reg]);
} else {
(*info->fprintf_func) (info->stream, "(%s)+", reg_names[reg]);
}
break;
case 0x90: /* Autoincrement deferred: @(Rn)+ */
if (reg == 0xF)
(*info->fprintf_func) (info->stream, "*0x%x", NEXTLONG (p));
else
(*info->fprintf_func) (info->stream, "@(%s)+", reg_names[reg]);
break;
if (reg == 0xF) {
(*info->fprintf_func) (info->stream, "*0x%x", NEXTLONG (p));
} else {
(*info->fprintf_func) (info->stream, "@(%s)+", reg_names[reg]);
}
break;
case 0xB0: /* Displacement byte deferred: *displ(Rn). */
(*info->fprintf_func) (info->stream, "*");
case 0xA0: /* Displacement byte: displ(Rn). */
if (reg == 0xF)
(*info->print_address_func) (addr + 2 + NEXTBYTE (p), info);
else
(*info->fprintf_func) (info->stream, "0x%x(%s)", NEXTBYTE (p),
reg_names[reg]);
break;
if (reg == 0xF) {
(*info->print_address_func) (addr + 2 + NEXTBYTE (p), info);
} else {
(*info->fprintf_func) (info->stream, "0x%x(%s)", NEXTBYTE (p),
reg_names[reg]);
}
break;
case 0xD0: /* Displacement word deferred: *displ(Rn). */
(*info->fprintf_func) (info->stream, "*");
case 0xC0: /* Displacement word: displ(Rn). */
if (reg == 0xF)
(*info->print_address_func) (addr + 3 + NEXTWORD (p), info);
else
(*info->fprintf_func) (info->stream, "0x%x(%s)", NEXTWORD (p),
reg_names[reg]);
break;
if (reg == 0xF) {
(*info->print_address_func) (addr + 3 + NEXTWORD (p), info);
} else {
(*info->fprintf_func) (info->stream, "0x%x(%s)", NEXTWORD (p),
reg_names[reg]);
}
break;
case 0xF0: /* Displacement long deferred: *displ(Rn). */
(*info->fprintf_func) (info->stream, "*");
case 0xE0: /* Displacement long: displ(Rn). */
if (reg == 0xF)
(*info->print_address_func) (addr + 5 + NEXTLONG (p), info);
else
(*info->fprintf_func) (info->stream, "0x%x(%s)", NEXTLONG (p),
reg_names[reg]);
break;
if (reg == 0xF) {
(*info->print_address_func) (addr + 5 + NEXTLONG (p), info);
} else {
(*info->fprintf_func) (info->stream, "0x%x(%s)", NEXTLONG (p),
reg_names[reg]);
}
break;
}
return p - p0;
@ -275,10 +282,11 @@ print_insn_arg (const char *d,
{
unsigned char *p = p0;
if (arg_len == 1)
(*info->print_address_func) (addr + 1 + NEXTBYTE (p), info);
else
(*info->print_address_func) (addr + 2 + NEXTWORD (p), info);
if (arg_len == 1) {
(*info->print_address_func) (addr + 1 + NEXTBYTE (p), info);
} else {
(*info->print_address_func) (addr + 2 + NEXTWORD (p), info);
}
return p - p0;
}
@ -303,9 +311,10 @@ print_insn_vax (bfd_vma memaddr, disassemble_info *info)
priv.max_fetched = priv.the_buffer;
priv.insn_start = memaddr;
if (setjmp (priv.bailout) != 0)
/* Error return. */
return -1;
if (setjmp (priv.bailout) != 0) {
/* Error return. */
return -1;
}
argp = NULL;
/* Check if the info buffer has more than one byte left since
@ -348,15 +357,17 @@ print_insn_vax (bfd_vma memaddr, disassemble_info *info)
FETCH_DATA (info, arg);
(*info->fprintf_func) (info->stream, "%s", votp->name);
if (*argp)
(*info->fprintf_func) (info->stream, " ");
if (*argp) {
(*info->fprintf_func) (info->stream, " ");
}
while (*argp)
{
arg += print_insn_arg (argp, arg, memaddr + arg - buffer, info);
argp += 2;
if (*argp)
(*info->fprintf_func) (info->stream, ", ");
if (*argp) {
(*info->fprintf_func) (info->stream, ", ");
}
}
return arg - buffer;

48
libr/asm/arch/wasm/wasm.c
View File

@ -354,7 +354,9 @@ int wasm_dis(WasmOp *op, const unsigned char *buf, int buf_len) {
{
st32 val = 0;
size_t n = read_i32_leb128 (buf + 1, buf + buf_len, &val);
if (!(n > 0 && n < buf_len)) goto err;
if (!(n > 0 && n < buf_len)) {
goto err;
}
switch (0x80 - val) {
case R_BIN_WASM_VALUETYPE_EMPTY:
snprintf (op->txt, R_ASM_BUFSIZE, "%s", opdef->txt);
@ -384,7 +386,9 @@ int wasm_dis(WasmOp *op, const unsigned char *buf, int buf_len) {
{
ut32 val = 0;
size_t n = read_u32_leb128 (buf + 1, buf + buf_len, &val);
if (!(n > 0 && n < buf_len)) goto err;
if (!(n > 0 && n < buf_len)) {
goto err;
}
snprintf (op->txt, R_ASM_BUFSIZE, "%s %d", opdef->txt, val);
op->len += n;
}
@ -439,10 +443,14 @@ int wasm_dis(WasmOp *op, const unsigned char *buf, int buf_len) {
{
ut32 val = 0, reserved = 0;
size_t n = read_u32_leb128 (buf + 1, buf + buf_len, &val);
if (!(n > 0 && n < buf_len)) goto err;
if (!(n > 0 && n < buf_len)) {
goto err;
}
op->len += n;
n = read_u32_leb128 (buf + op->len, buf + buf_len, &reserved);
if (!(n == 1 && op->len + n <= buf_len)) goto err;
if (!(n == 1 && op->len + n <= buf_len)) {
goto err;
}
reserved &= 0x1;
snprintf (op->txt, R_ASM_BUFSIZE, "%s %d %d", opdef->txt, val, reserved);
op->len += n;
@ -456,7 +464,9 @@ int wasm_dis(WasmOp *op, const unsigned char *buf, int buf_len) {
{
ut32 val = 0;
size_t n = read_u32_leb128 (buf + 1, buf + buf_len, &val);
if (!(n > 0 && n < buf_len)) goto err;
if (!(n > 0 && n < buf_len)) {
goto err;
}
snprintf (op->txt, R_ASM_BUFSIZE, "%s %d", opdef->txt, val);
op->len += n;
}
@ -487,10 +497,14 @@ int wasm_dis(WasmOp *op, const unsigned char *buf, int buf_len) {
{
ut32 flag = 0, offset = 0;
size_t n = read_u32_leb128 (buf + 1, buf + buf_len, &flag);
if (!(n > 0 && n < buf_len)) goto err;
if (!(n > 0 && n < buf_len)) {
goto err;
}
op->len += n;
n = read_u32_leb128 (buf + op->len, buf + buf_len, &offset);
if (!(n > 0 && op->len + n <= buf_len)) goto err;
if (!(n > 0 && op->len + n <= buf_len)) {
goto err;
}
snprintf (op->txt, R_ASM_BUFSIZE, "%s %d %d", opdef->txt, flag, offset);
op->len += n;
}
@ -500,7 +514,9 @@ int wasm_dis(WasmOp *op, const unsigned char *buf, int buf_len) {
{
ut32 reserved = 0;
size_t n = read_u32_leb128 (buf + 1, buf + buf_len, &reserved);
if (!(n == 1 && n < buf_len)) goto err;
if (!(n == 1 && n < buf_len)) {
goto err;
}
reserved &= 0x1;
snprintf (op->txt, R_ASM_BUFSIZE, "%s %d", opdef->txt, reserved);
op->len += n;
@ -511,7 +527,9 @@ int wasm_dis(WasmOp *op, const unsigned char *buf, int buf_len) {
{
st32 val = 0;
size_t n = read_i32_leb128 (buf + 1, buf + buf_len, &val);
if (!(n > 0 && n < buf_len)) goto err;
if (!(n > 0 && n < buf_len)) {
goto err;
}
snprintf (op->txt, R_ASM_BUFSIZE, "%s %" PFMT32d, opdef->txt, val);
op->len += n;
}
@ -520,7 +538,9 @@ int wasm_dis(WasmOp *op, const unsigned char *buf, int buf_len) {
{
st64 val = 0;
size_t n = read_i64_leb128 (buf + 1, buf + buf_len, &val);
if (!(n > 0 && n < buf_len)) goto err;
if (!(n > 0 && n < buf_len)) {
goto err;
}
snprintf (op->txt, R_ASM_BUFSIZE, "%s %" PFMT64d, opdef->txt, val);
op->len += n;
}
@ -529,7 +549,9 @@ int wasm_dis(WasmOp *op, const unsigned char *buf, int buf_len) {
{
ut32 val = 0;
size_t n = read_u32_leb128 (buf + 1, buf + buf_len, &val);
if (!(n > 0 && n < buf_len)) goto err;
if (!(n > 0 && n < buf_len)) {
goto err;
}
long double d = (long double)val;
snprintf (op->txt, R_ASM_BUFSIZE, "%s %" LDBLFMT, opdef->txt, d);
op->len += n;
@ -539,7 +561,9 @@ int wasm_dis(WasmOp *op, const unsigned char *buf, int buf_len) {
{
ut64 val = 0;
size_t n = read_u64_leb128 (buf + 1, buf + buf_len, &val);
if (!(n > 0 && n < buf_len)) goto err;
if (!(n > 0 && n < buf_len)) {
goto err;
}
long double d = (long double)val;
snprintf (op->txt, R_ASM_BUFSIZE, "%s %" LDBLFMT, opdef->txt, d);
op->len += n;

142
libr/asm/arch/xtensa/gnu/xtensa-dis.c
View File

@ -80,8 +80,9 @@ fetch_data (struct disassemble_info *info, bfd_vma memaddr)
{
status = (*info->read_memory_func) (memaddr, priv->byte_buf, length,
info);
if (status == 0)
return length;
if (status == 0) {
return length;
}
}
(*info->memory_error_func) (status, memaddr, info);
OPCODES_SIGLONGJMP (priv->bailout, 1);
@ -102,11 +103,12 @@ print_xtensa_operand (bfd_vma memaddr,
if (show_raw_fields)
{
if (operand_val < 0xa)
(*info->fprintf_func) (info->stream, "%u", operand_val);
else
(*info->fprintf_func) (info->stream, "0x%x", operand_val);
return;
if (operand_val < 0xa) {
(*info->fprintf_func) (info->stream, "%u", operand_val);
} else {
(*info->fprintf_func) (info->stream, "0x%x", operand_val);
}
return;
}
(void) xtensa_operand_decode (isa, opc, opnd, &operand_val);
@ -123,10 +125,11 @@ print_xtensa_operand (bfd_vma memaddr,
}
else
{
if ((signed_operand_val > -256) && (signed_operand_val < 256))
(*info->fprintf_func) (info->stream, "%d", signed_operand_val);
else
(*info->fprintf_func) (info->stream, "0x%x", signed_operand_val);
if ((signed_operand_val > -256) && (signed_operand_val < 256)) {
(*info->fprintf_func) (info->stream, "%d", signed_operand_val);
} else {
(*info->fprintf_func) (info->stream, "0x%x", signed_operand_val);
}
}
}
else
@ -165,8 +168,9 @@ print_insn_xtensa (bfd_vma memaddr, struct disassemble_info *info)
static xtensa_insnbuf slot_buffer = NULL;
int first, first_slot, valid_insn;
if (!xtensa_default_isa)
xtensa_default_isa = xtensa_isa_init (0, 0);
if (!xtensa_default_isa) {
xtensa_default_isa = xtensa_isa_init (0, 0);
}
info->target = 0;
maxsize = xtensa_isa_maxlength (xtensa_default_isa);
@ -214,24 +218,19 @@ print_insn_xtensa (bfd_vma memaddr, struct disassemble_info *info)
xtensa_insnbuf_from_chars (isa, insn_buffer, priv.byte_buf, bytes_fetched);
fmt = xtensa_format_decode (isa, insn_buffer);
if (fmt == XTENSA_UNDEFINED
|| ((size = xtensa_format_length (isa, fmt)) > bytes_fetched))
valid_insn = 0;
else
{
/* Make sure all the opcodes are valid. */
valid_insn = 1;
nslots = xtensa_format_num_slots (isa, fmt);
for (n = 0; n < nslots; n++)
{
xtensa_format_get_slot (isa, fmt, n, insn_buffer, slot_buffer);
if (xtensa_opcode_decode (isa, fmt, n, slot_buffer)
== XTENSA_UNDEFINED)
{
valid_insn = 0;
break;
}
}
if (fmt == XTENSA_UNDEFINED || ((size = xtensa_format_length (isa, fmt)) > bytes_fetched)) {
valid_insn = 0;
} else {
/* Make sure all the opcodes are valid. */
valid_insn = 1;
nslots = xtensa_format_num_slots (isa, fmt);
for (n = 0; n < nslots; n++) {
xtensa_format_get_slot (isa, fmt, n, insn_buffer, slot_buffer);
if (xtensa_opcode_decode (isa, fmt, n, slot_buffer) == XTENSA_UNDEFINED) {
valid_insn = 0;
break;
}
}
}
if (!valid_insn)
@ -240,49 +239,50 @@ print_insn_xtensa (bfd_vma memaddr, struct disassemble_info *info)
return 1;
}
if (nslots > 1)
(*info->fprintf_func) (info->stream, "{ ");
first_slot = 1;
for (n = 0; n < nslots; n++)
{
if (first_slot)
first_slot = 0;
else
(*info->fprintf_func) (info->stream, "; ");
xtensa_format_get_slot (isa, fmt, n, insn_buffer, slot_buffer);
opc = xtensa_opcode_decode (isa, fmt, n, slot_buffer);
(*info->fprintf_func) (info->stream, "%s",
xtensa_opcode_name (isa, opc));
/* Print the operands (if any). */
noperands = xtensa_opcode_num_operands (isa, opc);
first = 1;
for (i = 0; i < noperands; i++)
{
if (xtensa_operand_is_visible (isa, opc, i) == 0)
continue;
if (first)
{
(*info->fprintf_func) (info->stream, " ");
first = 0;
}
else
(*info->fprintf_func) (info->stream, ", ");
(void) xtensa_operand_get_field (isa, opc, i, fmt, n,
slot_buffer, &operand_val);
print_xtensa_operand (memaddr, info, opc, i, operand_val);
}
if (nslots > 1) {
(*info->fprintf_func) (info->stream, "{ ");
}
if (nslots > 1)
(*info->fprintf_func) (info->stream, " }");
first_slot = 1;
for (n = 0; n < nslots; n++) {
if (first_slot) {
first_slot = 0;
} else {
(*info->fprintf_func) (info->stream, "; ");
}
info->bytes_per_chunk = size;
info->display_endian = info->endian;
xtensa_format_get_slot (isa, fmt, n, insn_buffer, slot_buffer);
opc = xtensa_opcode_decode (isa, fmt, n, slot_buffer);
(*info->fprintf_func) (info->stream, "%s",
xtensa_opcode_name (isa, opc));
return size;
/* Print the operands (if any). */
noperands = xtensa_opcode_num_operands (isa, opc);
first = 1;
for (i = 0; i < noperands; i++) {
if (xtensa_operand_is_visible (isa, opc, i) == 0) {
continue;
}
if (first) {
(*info->fprintf_func) (info->stream, " ");
first = 0;
} else {
(*info->fprintf_func) (info->stream, ", ");
}
(void)xtensa_operand_get_field (isa, opc, i, fmt, n,
slot_buffer, &operand_val);
print_xtensa_operand (memaddr, info, opc, i, operand_val);
}
}
if (nslots > 1) {
(*info->fprintf_func) (info->stream, " }");
}
info->bytes_per_chunk = size;
info->display_endian = info->endian;
return size;
}

211
libr/asm/arch/xtensa/gnu/xtensa-isa.c
View File

@ -139,8 +139,9 @@ xtensa_insnbuf_to_chars (xtensa_isa isa,
int fence_post, start, increment, i, byte_count;
xtensa_format fmt;
if (num_chars == 0)
num_chars = insn_size;
if (num_chars == 0) {
num_chars = insn_size;
}
if (intisa->is_big_endian)
{
@ -156,12 +157,14 @@ xtensa_insnbuf_to_chars (xtensa_isa isa,
/* Find the instruction format. Do nothing if the buffer does not contain
a valid instruction since we need to know how many bytes to copy. */
fmt = xtensa_format_decode (isa, insn);
if (fmt == XTENSA_UNDEFINED)
return XTENSA_UNDEFINED;
if (fmt == XTENSA_UNDEFINED) {
return XTENSA_UNDEFINED;
}
byte_count = xtensa_format_length (isa, fmt);
if (byte_count == XTENSA_UNDEFINED)
return XTENSA_UNDEFINED;
if (byte_count == XTENSA_UNDEFINED) {
return XTENSA_UNDEFINED;
}
if (byte_count > num_chars)
{
@ -208,13 +211,13 @@ xtensa_insnbuf_from_chars (xtensa_isa isa,
insn_size = max_size;
}
if (num_chars == 0 || num_chars > insn_size)
num_chars = insn_size;
if (num_chars == 0 || num_chars > insn_size) {
num_chars = insn_size;
}
if (intisa->is_big_endian)
{
start = max_size - 1;
increment = -1;
if (intisa->is_big_endian) {
start = max_size - 1;
increment = -1;
}
else
{
@ -291,8 +294,9 @@ xtensa_isa_init (xtensa_isa_status *errno_p, char **error_msg_p)
CHECK_ALLOC_FOR_INIT (isa->sysreg_table[is_user], NULL,
errno_p, error_msg_p);
for (n = 0; n <= isa->max_sysreg_num[is_user]; n++)
isa->sysreg_table[is_user][n] = XTENSA_UNDEFINED;
for (n = 0; n <= isa->max_sysreg_num[is_user]; n++) {
isa->sysreg_table[is_user][n] = XTENSA_UNDEFINED;
}
}
for (n = 0; n < isa->num_sysregs; n++)
{
@ -422,8 +426,9 @@ xtensa_isa_num_pipe_stages (xtensa_isa isa)
static int max_stage = XTENSA_UNDEFINED;
/* Only compute the value once. */
if (max_stage != XTENSA_UNDEFINED)
return max_stage + 1;
if (max_stage != XTENSA_UNDEFINED) {
return max_stage + 1;
}
num_opcodes = xtensa_isa_num_opcodes (isa);
for (opcode = 0; opcode < num_opcodes; opcode++)
@ -433,8 +438,9 @@ xtensa_isa_num_pipe_stages (xtensa_isa isa)
{
use = xtensa_opcode_funcUnit_use (isa, opcode, i);
stage = use->stage;
if (stage > max_stage)
max_stage = stage;
if (stage > max_stage) {
max_stage = stage;
}
}
}
@ -548,8 +554,9 @@ xtensa_format_lookup (xtensa_isa isa, const char *fmtname)
for (fmt = 0; fmt < intisa->num_formats; fmt++)
{
if (r_str_casecmp (fmtname, intisa->formats[fmt].name) == 0)
return fmt;
if (r_str_casecmp (fmtname, intisa->formats[fmt].name) == 0) {
return fmt;
}
}
xtisa_errno = xtensa_isa_bad_format;
@ -565,8 +572,9 @@ xtensa_format_decode (xtensa_isa isa, const xtensa_insnbuf insn)
xtensa_format fmt;
fmt = (intisa->format_decode_fn) (insn);
if (fmt != XTENSA_UNDEFINED)
return fmt;
if (fmt != XTENSA_UNDEFINED) {
return fmt;
}
xtisa_errno = xtensa_isa_bad_format;
strcpy (xtisa_error_msg, "cannot decode instruction format");
@ -709,8 +717,9 @@ xtensa_opcode_decode (xtensa_isa isa, xtensa_format fmt, int slot,
slot_id = intisa->formats[fmt].slot_id[slot];
opc = (intisa->slots[slot_id].opcode_decode_fn) (slotbuf);
if (opc != XTENSA_UNDEFINED)
return opc;
if (opc != XTENSA_UNDEFINED) {
return opc;
}
xtisa_errno = xtensa_isa_bad_opcode;
strcpy (xtisa_error_msg, "cannot decode opcode");
@ -759,8 +768,9 @@ xtensa_opcode_is_branch (xtensa_isa isa, xtensa_opcode opc)
{
xtensa_isa_internal *intisa = (xtensa_isa_internal *) isa;
CHECK_OPCODE (intisa, opc, XTENSA_UNDEFINED);
if ((intisa->opcodes[opc].flags & XTENSA_OPCODE_IS_BRANCH) != 0)
return 1;
if ((intisa->opcodes[opc].flags & XTENSA_OPCODE_IS_BRANCH) != 0) {
return 1;
}
return 0;
}
@ -770,8 +780,9 @@ xtensa_opcode_is_jump (xtensa_isa isa, xtensa_opcode opc)
{
xtensa_isa_internal *intisa = (xtensa_isa_internal *) isa;
CHECK_OPCODE (intisa, opc, XTENSA_UNDEFINED);
if ((intisa->opcodes[opc].flags & XTENSA_OPCODE_IS_JUMP) != 0)
return 1;
if ((intisa->opcodes[opc].flags & XTENSA_OPCODE_IS_JUMP) != 0) {
return 1;
}
return 0;
}
@ -781,8 +792,9 @@ xtensa_opcode_is_loop (xtensa_isa isa, xtensa_opcode opc)
{
xtensa_isa_internal *intisa = (xtensa_isa_internal *) isa;
CHECK_OPCODE (intisa, opc, XTENSA_UNDEFINED);
if ((intisa->opcodes[opc].flags & XTENSA_OPCODE_IS_LOOP) != 0)
return 1;
if ((intisa->opcodes[opc].flags & XTENSA_OPCODE_IS_LOOP) != 0) {
return 1;
}
return 0;
}
@ -792,8 +804,9 @@ xtensa_opcode_is_call (xtensa_isa isa, xtensa_opcode opc)
{
xtensa_isa_internal *intisa = (xtensa_isa_internal *) isa;
CHECK_OPCODE (intisa, opc, XTENSA_UNDEFINED);
if ((intisa->opcodes[opc].flags & XTENSA_OPCODE_IS_CALL) != 0)
return 1;
if ((intisa->opcodes[opc].flags & XTENSA_OPCODE_IS_CALL) != 0) {
return 1;
}
return 0;
}
@ -899,7 +912,9 @@ xtensa_operand_name (xtensa_isa isa, xtensa_opcode opc, int opnd)
xtensa_operand_internal *intop;
intop = get_operand (intisa, opc, opnd);
if (!intop) return NULL;
if (!intop) {
return NULL;
}
return intop->name;
}
@ -918,14 +933,16 @@ xtensa_operand_is_visible (xtensa_isa isa, xtensa_opcode opc, int opnd)
CHECK_OPERAND (intisa, opc, iclass, opnd, XTENSA_UNDEFINED);
/* Special case for "sout" operands. */
if (iclass->operands[opnd].inout == 's')
return 0;
if (iclass->operands[opnd].inout == 's') {
return 0;
}
operand_id = iclass->operands[opnd].u.operand_id;
intop = &intisa->operands[operand_id];
if ((intop->flags & XTENSA_OPERAND_IS_INVISIBLE) == 0)
return 1;
if ((intop->flags & XTENSA_OPERAND_IS_INVISIBLE) == 0) {
return 1;
}
return 0;
}
@ -945,8 +962,9 @@ xtensa_operand_inout (xtensa_isa isa, xtensa_opcode opc, int opnd)
inout = iclass->operands[opnd].inout;
/* Special case for "sout" operands. */
if (inout == 's')
return 'o';
if (inout == 's') {
return 'o';
}
return inout;
}
@ -963,7 +981,9 @@ xtensa_operand_get_field (xtensa_isa isa, xtensa_opcode opc, int opnd,
xtensa_get_field_fn get_fn;
intop = get_operand (intisa, opc, opnd);
if (!intop) return -1;
if (!intop) {
return -1;
}
CHECK_FORMAT (intisa, fmt, -1);
CHECK_SLOT (intisa, fmt, slot, -1);
@ -1000,7 +1020,9 @@ xtensa_operand_set_field (xtensa_isa isa, xtensa_opcode opc, int opnd,
xtensa_set_field_fn set_fn;
intop = get_operand (intisa, opc, opnd);
if (!intop) return -1;
if (!intop) {
return -1;
}
CHECK_FORMAT (intisa, fmt, -1);
CHECK_SLOT (intisa, fmt, slot, -1);
@ -1035,8 +1057,9 @@ xtensa_operand_encode (xtensa_isa isa, xtensa_opcode opc, int opnd,
uint32 test_val, orig_val;
intop = get_operand (intisa, opc, opnd);
if (!intop)
return -1;
if (!intop) {
return -1;
}
if (!intop->encode)
{
@ -1108,11 +1131,14 @@ xtensa_operand_decode (xtensa_isa isa, xtensa_opcode opc, int opnd,
xtensa_operand_internal *intop;
intop = get_operand (intisa, opc, opnd);
if (!intop) return -1;
if (!intop) {
return -1;
}
/* Use identity function for "default" operands. */
if (!intop->decode)
return 0;
if (!intop->decode) {
return 0;
}
if ((*intop->decode) (valp))
{
@ -1131,10 +1157,13 @@ xtensa_operand_is_register (xtensa_isa isa, xtensa_opcode opc, int opnd)
xtensa_operand_internal *intop;
intop = get_operand (intisa, opc, opnd);
if (!intop) return XTENSA_UNDEFINED;
if (!intop) {
return XTENSA_UNDEFINED;
}
if ((intop->flags & XTENSA_OPERAND_IS_REGISTER) != 0)
return 1;
if ((intop->flags & XTENSA_OPERAND_IS_REGISTER) != 0) {
return 1;
}
return 0;
}
@ -1146,7 +1175,9 @@ xtensa_operand_regfile (xtensa_isa isa, xtensa_opcode opc, int opnd)
xtensa_operand_internal *intop;
intop = get_operand (intisa, opc, opnd);
if (!intop) return XTENSA_UNDEFINED;
if (!intop) {
return XTENSA_UNDEFINED;
}
return intop->regfile;
}
@ -1159,7 +1190,9 @@ xtensa_operand_num_regs (xtensa_isa isa, xtensa_opcode opc, int opnd)
xtensa_operand_internal *intop;
intop = get_operand (intisa, opc, opnd);
if (!intop) return XTENSA_UNDEFINED;
if (!intop) {
return XTENSA_UNDEFINED;
}
return intop->num_regs;
}
@ -1172,10 +1205,13 @@ xtensa_operand_is_known_reg (xtensa_isa isa, xtensa_opcode opc, int opnd)
xtensa_operand_internal *intop;
intop = get_operand (intisa, opc, opnd);
if (!intop) return XTENSA_UNDEFINED;
if (!intop) {
return XTENSA_UNDEFINED;
}
if ((intop->flags & XTENSA_OPERAND_IS_UNKNOWN) == 0)
return 1;
if ((intop->flags & XTENSA_OPERAND_IS_UNKNOWN) == 0) {
return 1;
}
return 0;
}
@ -1187,10 +1223,13 @@ xtensa_operand_is_PCrelative (xtensa_isa isa, xtensa_opcode opc, int opnd)
xtensa_operand_internal *intop;
intop = get_operand (intisa, opc, opnd);
if (!intop) return XTENSA_UNDEFINED;
if (!intop) {
return XTENSA_UNDEFINED;
}
if ((intop->flags & XTENSA_OPERAND_IS_PCRELATIVE) != 0)
return 1;
if ((intop->flags & XTENSA_OPERAND_IS_PCRELATIVE) != 0) {
return 1;
}
return 0;
}
@ -1203,10 +1242,13 @@ xtensa_operand_do_reloc (xtensa_isa isa, xtensa_opcode opc, int opnd,
xtensa_operand_internal *intop;
intop = get_operand (intisa, opc, opnd);
if (!intop) return -1;
if (!intop) {
return -1;
}
if ((intop->flags & XTENSA_OPERAND_IS_PCRELATIVE) == 0)
return 0;
if ((intop->flags & XTENSA_OPERAND_IS_PCRELATIVE) == 0) {
return 0;
}
if (!intop->do_reloc)
{
@ -1235,10 +1277,13 @@ xtensa_operand_undo_reloc (xtensa_isa isa, xtensa_opcode opc, int opnd,
xtensa_operand_internal *intop;
intop = get_operand (intisa, opc, opnd);
if (!intop) return -1;
if (!intop) {
return -1;
}
if ((intop->flags & XTENSA_OPERAND_IS_PCRELATIVE) == 0)
return 0;
if ((intop->flags & XTENSA_OPERAND_IS_PCRELATIVE) == 0) {
return 0;
}
if (!intop->undo_reloc)
{
@ -1371,8 +1416,9 @@ xtensa_regfile_lookup (xtensa_isa isa, const char *name)
/* The expected number of regfiles is small; use a linear search. */
for (n = 0; n < intisa->num_regfiles; n++)
{
if (!filename_cmp (intisa->regfiles[n].name, name))
return n;
if (!filename_cmp (intisa->regfiles[n].name, name)) {
return n;
}
}
xtisa_errno = xtensa_isa_bad_regfile;
@ -1399,10 +1445,12 @@ xtensa_regfile_lookup_shortname (xtensa_isa isa, const char *shortname)
{
/* Ignore regfile views since they always have the same shortnames
as their parents. */
if (intisa->regfiles[n].parent != n)
continue;
if (!filename_cmp (intisa->regfiles[n].shortname, shortname))
return n;
if (intisa->regfiles[n].parent != n) {
continue;
}
if (!filename_cmp (intisa->regfiles[n].shortname, shortname)) {
return n;
}
}
xtisa_errno = xtensa_isa_bad_regfile;
@ -1526,8 +1574,9 @@ xtensa_state_is_exported (xtensa_isa isa, xtensa_state st)
{
xtensa_isa_internal *intisa = (xtensa_isa_internal *) isa;
CHECK_STATE (intisa, st, XTENSA_UNDEFINED);
if ((intisa->states[st].flags & XTENSA_STATE_IS_EXPORTED) != 0)
return 1;
if ((intisa->states[st].flags & XTENSA_STATE_IS_EXPORTED) != 0) {
return 1;
}
return 0;
}
@ -1537,8 +1586,9 @@ xtensa_state_is_shared_or (xtensa_isa isa, xtensa_state st)
{
xtensa_isa_internal *intisa = (xtensa_isa_internal *) isa;
CHECK_STATE (intisa, st, XTENSA_UNDEFINED);
if ((intisa->states[st].flags & XTENSA_STATE_IS_SHARED_OR) != 0)
return 1;
if ((intisa->states[st].flags & XTENSA_STATE_IS_SHARED_OR) != 0) {
return 1;
}
return 0;
}
@ -1563,8 +1613,9 @@ xtensa_sysreg_lookup (xtensa_isa isa, int num, int is_user)
{
xtensa_isa_internal *intisa = (xtensa_isa_internal *) isa;
if (is_user != 0)
is_user = 1;
if (is_user != 0) {
is_user = 1;
}
if (num < 0 || num > intisa->max_sysreg_num[is_user]
|| intisa->sysreg_table[is_user][num] == XTENSA_UNDEFINED)
@ -1633,8 +1684,9 @@ xtensa_sysreg_is_user (xtensa_isa isa, xtensa_sysreg sysreg)
{
xtensa_isa_internal *intisa = (xtensa_isa_internal *) isa;
CHECK_SYSREG (intisa, sysreg, XTENSA_UNDEFINED);
if (intisa->sysregs[sysreg].is_user)
return 1;
if (intisa->sysregs[sysreg].is_user) {
return 1;
}
return 0;
}
@ -1718,8 +1770,9 @@ xtensa_interface_has_side_effect (xtensa_isa isa, xtensa_interface intf)
{
xtensa_isa_internal *intisa = (xtensa_isa_internal *) isa;
CHECK_INTERFACE (intisa, intf, XTENSA_UNDEFINED);
if ((intisa->interfaces[intf].flags & XTENSA_INTERFACE_HAS_SIDE_EFFECT) != 0)
return 1;
if ((intisa->interfaces[intf].flags & XTENSA_INTERFACE_HAS_SIDE_EFFECT) != 0) {
return 1;
}
return 0;
}

1724
libr/asm/arch/xtensa/gnu/xtensa-modules.c
View File

File diff suppressed because it is too large Load Diff

3
libr/asm/arch/z80/z80.c
View File

@ -28,8 +28,9 @@ static ut8 z80_op_24_branch_index_res (ut8 hex) {
static int z80OpLength (const ut8 *buf, int len) {
z80_opcode *op;
int type = 0, ret = 0;
if (len < 1)
if (len < 1) {
return 0;
}
op = z80_op;
if (op[buf[0]].type & Z80_OP_UNK) {
if (len < 2) {

57
libr/asm/asm.c
View File

@ -224,8 +224,9 @@ R_API int r_asm_filter_input(RAsm *a, const char *f) {
}
R_API int r_asm_filter_output(RAsm *a, const char *f) {
if (!a->ofilter)
if (!a->ofilter) {
a->ofilter = r_parse_new ();
}
if (!r_parse_use (a->ofilter, f)) {
r_parse_free (a->ofilter);
a->ofilter = NULL;
@ -528,7 +529,9 @@ static char *replace_directives_for(char *str, char *token) {
char *q = str;
bool changes = false;
for (;;) {
if (q) p = strstr (q, token);
if (q) {
p = strstr (q, token);
}
if (p) {
char *nl = strchr (p, '\n');
if (nl) {
@ -542,7 +545,9 @@ static char *replace_directives_for(char *str, char *token) {
q = nl;
changes = true;
} else {
if (q) r_strbuf_append (sb, q);
if (q) {
r_strbuf_append (sb, q);
}
break;
}
}
@ -809,10 +814,16 @@ R_API RAsmCode* r_asm_massemble(RAsm *a, const char *buf) {
// XXX TODO remove arch-specific hacks
if (!strncmp (a->cur->arch, "avr", 3)) {
for (ptr_start = buf_token; *ptr_start &&
isavrseparator (*ptr_start); ptr_start++);
isavrseparator (*ptr_start);
ptr_start++) {
;
}
} else {
for (ptr_start = buf_token; *ptr_start &&
IS_SEPARATOR (*ptr_start); ptr_start++);
IS_SEPARATOR (*ptr_start);
ptr_start++) {
;
}
}
if (!strncmp (ptr_start, "/*", 2)) {
if (!strstr (ptr_start + 2, "*/")) {
@ -895,42 +906,44 @@ R_API RAsmCode* r_asm_massemble(RAsm *a, const char *buf) {
r_asm_use (a, "arm");
r_asm_set_bits (a, 16);
ret = 0;
} else if (!strncmp (ptr, ".arch ", 6))
} else if (!strncmp (ptr, ".arch ", 6)) {
ret = r_asm_pseudo_arch (a, ptr+6);
else if (!strncmp (ptr, ".bits ", 6))
} else if (!strncmp (ptr, ".bits ", 6)) {
ret = r_asm_pseudo_bits (a, ptr+6);
else if (!strncmp (ptr, ".fill ", 6))
} else if (!strncmp (ptr, ".fill ", 6)) {
ret = r_asm_pseudo_fill (&op, ptr+6);
else if (!strncmp (ptr, ".kernel ", 8))
} else if (!strncmp (ptr, ".kernel ", 8)) {
r_syscall_setup (a->syscall, a->cur->arch, a->bits, asmcpu, ptr + 8);
else if (!strncmp (ptr, ".cpu ", 5))
} else if (!strncmp (ptr, ".cpu ", 5)) {
r_asm_set_cpu (a, ptr + 5);
else if (!strncmp (ptr, ".os ", 4))
} else if (!strncmp (ptr, ".os ", 4)) {
r_syscall_setup (a->syscall, a->cur->arch, a->bits, asmcpu, ptr + 4);
else if (!strncmp (ptr, ".hex ", 5)) {
} else if (!strncmp (ptr, ".hex ", 5)) {
ret = r_asm_pseudo_hex (&op, ptr + 5);
} else if ((!strncmp (ptr, ".int16 ", 7)) || !strncmp (ptr, ".short ", 7))
} else if ((!strncmp (ptr, ".int16 ", 7)) || !strncmp (ptr, ".short ", 7)) {
ret = r_asm_pseudo_int16 (a, &op, ptr+7);
else if (!strncmp (ptr, ".int32 ", 7))
} else if (!strncmp (ptr, ".int32 ", 7)) {
ret = r_asm_pseudo_int32 (a, &op, ptr+7);
else if (!strncmp (ptr, ".int64 ", 7))
} else if (!strncmp (ptr, ".int64 ", 7)) {
ret = r_asm_pseudo_int64 (a, &op, ptr+7);
else if (!strncmp (ptr, ".size", 5))
} else if (!strncmp (ptr, ".size", 5)) {
ret = true; // do nothing, ignored
else if (!strncmp (ptr, ".section", 8))
} else if (!strncmp (ptr, ".section", 8)) {
ret = true; // do nothing, ignored
else if ((!strncmp (ptr, ".byte ", 6)) || (!strncmp (ptr, ".int8 ", 6)))
} else if ((!strncmp (ptr, ".byte ", 6)) || (!strncmp (ptr, ".int8 ", 6))) {
ret = r_asm_pseudo_byte (&op, ptr+6);
else if (!strncmp (ptr, ".glob", 5)) { // .global .globl
// eprintf (".global directive not yet implemented\n");
} else if (!strncmp (ptr, ".glob", 5)) { // .global .globl
// eprintf (".global directive not yet implemented\n");
ret = 0;
continue;
} else if (!strncmp (ptr, ".equ ", 5)) {
ptr2 = strchr (ptr + 5, ',');
if (!ptr2)
if (!ptr2) {
ptr2 = strchr (ptr + 5, '=');
if (!ptr2)
}
if (!ptr2) {
ptr2 = strchr (ptr + 5, ' ');
}
if (ptr2) {
*ptr2 = '\0';
r_asm_code_set_equ (acode, ptr + 5, ptr2 + 1);

31
libr/asm/p/asm_avr.c
View File

@ -60,16 +60,18 @@ static int parse_specialreg(const char *reg) {
/* radare tolower instruction in rasm, so we use 'y' instead of 'Y'
and so on for other registers */
if (found == -1 && reg[1] == '+') {
if (reg[0] == 'y' && len > 2)
if (reg[0] == 'y' && len > 2) {
found = OPERAND_YPQ;
else if (reg[0] == 'z' && len > 2)
} else if (reg[0] == 'z' && len > 2) {
found = OPERAND_ZPQ;
}
}
if (found == -1 && reg[2] == '+') {
if (reg[0] == 'y' && len > 2)
if (reg[0] == 'y' && len > 2) {
found = OPERAND_YPQ;
else if (reg[0] == 'z' && len > 2)
} else if (reg[0] == 'z' && len > 2) {
found = OPERAND_ZPQ;
}
}
}
return found;
@ -106,15 +108,17 @@ static int search_instruction(RAsm *a, char instr[3][MAX_TOKEN_SIZE], int args)
// handling (e)lpm instruction with 2 args
if (instructionSet[i].opcodeMask >= 0x9004 &&
instructionSet[i].opcodeMask <= 0x9007) {
if (instructionSet[i].operandTypes[1] == parse_specialreg(instr[2]))
if (instructionSet[i].operandTypes[1] == parse_specialreg (instr[2])) {
return i;
// handling ld & ldd instruction with 2 args
}
// handling ld & ldd instruction with 2 args
} else if (instructionSet[i].mnemonic[0] == 'l'
&& instructionSet[i].mnemonic[1] == 'd'
&& (instructionSet[i].mnemonic[2] == 'd' || instructionSet[i].mnemonic[2] == '\0')) {
if (instructionSet[i].operandTypes[1] == parse_specialreg(instr[2]))
if (instructionSet[i].operandTypes[1] == parse_specialreg (instr[2])) {
return i;
// handling lds command, distinguishing long from 16-bit version
}
// handling lds command, distinguishing long from 16-bit version
} else if (instructionSet[i].mnemonic[0] == 'l'
&& instructionSet[i].mnemonic[1] == 'd'
&& instructionSet[i].mnemonic[2] == 's'
@ -131,9 +135,10 @@ static int search_instruction(RAsm *a, char instr[3][MAX_TOKEN_SIZE], int args)
&& instructionSet[i].mnemonic[1] == 't'
&& (instructionSet[i].mnemonic[2] == 'd' || instructionSet[i].mnemonic[2] == '\0')) {
if (instructionSet[i].operandTypes[0] == parse_specialreg(instr[1]))
if (instructionSet[i].operandTypes[0] == parse_specialreg (instr[1])) {
return i;
// handling sts long command
}
// handling sts long command
} else if (instructionSet[i].mnemonic[0] == 's'
&& instructionSet[i].mnemonic[1] == 't'
&& instructionSet[i].mnemonic[2] == 's'
@ -260,8 +265,9 @@ static int assemble_operand(RAsm *a, const char *operand, int type, uint32_t *re
temp -= a->pc + 2;
}
temp /= 2; // in WORDs
if(temp >= -64 && temp <= 63)
if (temp >= -64 && temp <= 63) {
ret = 0;
}
*res = temp;
break;
case OPERAND_IO_REGISTER:
@ -304,8 +310,9 @@ static int assemble_operand(RAsm *a, const char *operand, int type, uint32_t *re
if (strlen(operand) > 1) {
// returns register number (r__)
*res = getnum(a, operand + 1);
if (*res <=32)
if (*res <= 32) {
ret = 0;
}
}
break;
case OPERAND_REGISTER_STARTR16:

10
libr/asm/p/asm_cris_gnu.c
View File

@ -40,8 +40,9 @@ static void memory_error_func(int status, bfd_vma memaddr, struct disassemble_in
static void print_address(bfd_vma address, struct disassemble_info *info) {
char tmp[32];
if (!buf_global)
if (!buf_global) {
return;
}
sprintf(tmp, "0x%08"PFMT64x"", (ut64)address);
strcat(buf_global, tmp);
}
@ -50,13 +51,16 @@ static int buf_fprintf(void *stream, const char *format, ...) {
int flen, glen;
va_list ap;
char *tmp;
if (!buf_global)
if (!buf_global) {
return 0;
}
va_start (ap, format);
flen = strlen (format);
glen = strlen (buf_global);
tmp = malloc (flen + glen + 2);
if (!tmp) return 0;
if (!tmp) {
return 0;
}
memcpy (tmp, buf_global, glen);
memcpy (tmp+glen, format, flen);
tmp[flen+glen] = 0;

80
libr/asm/p/asm_lm32.c
View File

@ -21,7 +21,9 @@ static int reg_number_to_string(ut8 reg, char *str) {
}
}
//register number not found in array. this shouldn't happen
if (match_idx == 0xff) return -1;
if (match_idx == 0xff) {
return -1;
}
strcpy (str, RAsmLm32Regs[match_idx].name);
return 0;
}
@ -83,7 +85,9 @@ static int csr_number_to_string(ut8 csr, char *str) {
}
}
//csr number not found in array
if (match_idx == 0xff) return -1;
if (match_idx == 0xff) {
return -1;
}
strcpy (str, RAsmLm32Csrs[match_idx].name);
return 0;
}
@ -153,7 +157,9 @@ static bool is_pseudo_instr_raise(RAsmLm32Instruction *instr) {
static int r_asm_lm32_decode(RAsmLm32Instruction *instr) {
instr->op = extract_opcode (instr->value);
if (instr->op >= RAsmLm32OpcodeNumber) return -1;
if (instr->op >= RAsmLm32OpcodeNumber) {
return -1;
}
instr->op_decode = RAsmLm32OpcodeList[instr->op];
switch (instr->op_decode.type) {
@ -175,23 +181,31 @@ static int r_asm_lm32_decode(RAsmLm32Instruction *instr) {
instr->immediate = extract_imm16 (instr->value);
break;
case reg_imm5:
if (is_invalid_imm5_instr (instr)) return -1;
if (is_invalid_imm5_instr (instr)) {
return -1;
}
instr->dest_reg = extract_reg_v (instr->value);
instr->src0_reg = extract_reg_u (instr->value);
instr->immediate = extract_imm5 (instr->value);
break;
case raise_instr:
if (is_invalid_imm5_instr (instr)) return -1;
if (is_invalid_imm5_instr (instr)) {
return -1;
}
//might be less bits used, but this shouldn't hurt
//invalid parameters are catched in print_pseudo_instruction anyway
instr->immediate = extract_imm5 (instr->value);
break;
case one_reg:
if (is_invalid_one_reg_instr (instr)) return -1;
if (is_invalid_one_reg_instr (instr)) {
return -1;
}
instr->src0_reg = extract_reg_u (instr->value);
break;
case two_regs:
if (is_invalid_two_reg_instr (instr)) return -1;
if (is_invalid_two_reg_instr (instr)) {
return -1;
}
instr->dest_reg = extract_reg_w (instr->value);
instr->src0_reg = extract_reg_u (instr->value);
break;
@ -201,13 +215,17 @@ static int r_asm_lm32_decode(RAsmLm32Instruction *instr) {
instr->src1_reg = extract_reg_u (instr->value);
break;
case reg_csr: //wcsr
if (is_invalid_wcsr_instr (instr)) return -1;
if (is_invalid_wcsr_instr (instr)) {
return -1;
}
instr->src0_reg = extract_reg_v (instr->value);
instr->csr = extract_reg_u (instr->value);
break;
case csr_reg: //rcsr
//bitmask is the same as the two register one
if (is_invalid_two_reg_instr (instr)) return -1;
if (is_invalid_two_reg_instr (instr)) {
return -1;
}
instr->dest_reg = extract_reg_w (instr->value);
instr->csr = extract_reg_u (instr->value);
break;
@ -235,24 +253,44 @@ static int write_reg_names_to_struct(RAsmLm32Instruction *instr) {
case reg_imm16_zeroextend:
case reg_imm5:
case two_regs:
if (reg_number_to_string (instr->dest_reg, instr->dest_reg_str)) return -1;
if (reg_number_to_string (instr->src0_reg, instr->src0_reg_str)) return -1;
if (reg_number_to_string (instr->dest_reg, instr->dest_reg_str)) {
return -1;
}
if (reg_number_to_string (instr->src0_reg, instr->src0_reg_str)) {
return -1;
}
break;
case one_reg:
if (reg_number_to_string (instr->src0_reg, instr->src0_reg_str)) return -1;
if (reg_number_to_string (instr->src0_reg, instr->src0_reg_str)) {
return -1;
}
break;
case three_regs:
if (reg_number_to_string (instr->dest_reg, instr->dest_reg_str)) return -1;
if (reg_number_to_string (instr->src0_reg, instr->src0_reg_str)) return -1;
if (reg_number_to_string (instr->src1_reg, instr->src1_reg_str)) return -1;
if (reg_number_to_string (instr->dest_reg, instr->dest_reg_str)) {
return -1;
}
if (reg_number_to_string (instr->src0_reg, instr->src0_reg_str)) {
return -1;
}
if (reg_number_to_string (instr->src1_reg, instr->src1_reg_str)) {
return -1;
}
break;
case reg_csr:
if (reg_number_to_string (instr->src0_reg, instr->src0_reg_str)) return -1;
if (csr_number_to_string (instr->csr, instr->csr_reg_str)) return -1;
if (reg_number_to_string (instr->src0_reg, instr->src0_reg_str)) {
return -1;
}
if (csr_number_to_string (instr->csr, instr->csr_reg_str)) {
return -1;
}
break;
case csr_reg:
if (reg_number_to_string (instr->dest_reg, instr->dest_reg_str)) return -1;
if (csr_number_to_string (instr->csr, instr->csr_reg_str)) return -1;
if (reg_number_to_string (instr->dest_reg, instr->dest_reg_str)) {
return -1;
}
if (csr_number_to_string (instr->csr, instr->csr_reg_str)) {
return -1;
}
break;
case raise_instr:
case imm26:
@ -314,7 +352,9 @@ static int print_pseudo_instruction(RAsmLm32Instruction *instr, char *str) {
static int r_asm_lm32_stringify(RAsmLm32Instruction *instr, char *str) {
if (write_reg_names_to_struct (instr)) return -1;
if (write_reg_names_to_struct (instr)) {
return -1;
}
//pseudo instructions need some special handling
if (instr->pseudoInstruction) {

18
libr/asm/p/asm_m68k_cs.c
View File

@ -35,18 +35,24 @@ static int disassemble(RAsm *a, RAsmOp *op, const ut8 *buf, int len) {
}
// replace this with the asm.features?
if (a->cpu && strstr (a->cpu, "68000"))
if (a->cpu && strstr (a->cpu, "68000")) {
mode |= CS_MODE_M68K_000;
if (a->cpu && strstr (a->cpu, "68010"))
}
if (a->cpu && strstr (a->cpu, "68010")) {
mode |= CS_MODE_M68K_010;
if (a->cpu && strstr (a->cpu, "68020"))
}
if (a->cpu && strstr (a->cpu, "68020")) {
mode |= CS_MODE_M68K_020;
if (a->cpu && strstr (a->cpu, "68030"))
}
if (a->cpu && strstr (a->cpu, "68030")) {
mode |= CS_MODE_M68K_030;
if (a->cpu && strstr (a->cpu, "68040"))
}
if (a->cpu && strstr (a->cpu, "68040")) {
mode |= CS_MODE_M68K_040;
if (a->cpu && strstr (a->cpu, "68060"))
}
if (a->cpu && strstr (a->cpu, "68060")) {
mode |= CS_MODE_M68K_060;
}
if (op) {
op->size = 4;
}

20
libr/asm/p/asm_mcs96.c
View File

@ -7,11 +7,21 @@
#include "../arch/mcs96/mcs96.h"
static int mcs96_len (const ut8 buf) {
if (mcs96_op[buf].type & MCS96_6B) return 6;
if (mcs96_op[buf].type & MCS96_5B) return 5;
if (mcs96_op[buf].type & MCS96_4B) return 4;
if (mcs96_op[buf].type & MCS96_3B) return 3;
if (mcs96_op[buf].type & MCS96_2B) return 2;
if (mcs96_op[buf].type & MCS96_6B) {
return 6;
}
if (mcs96_op[buf].type & MCS96_5B) {
return 5;
}
if (mcs96_op[buf].type & MCS96_4B) {
return 4;
}
if (mcs96_op[buf].type & MCS96_3B) {
return 3;
}
if (mcs96_op[buf].type & MCS96_2B) {
return 2;
}
return 1;
}

3
libr/asm/p/asm_mips_gnu.c
View File

@ -43,8 +43,9 @@ static void print_address(bfd_vma address, struct disassemble_info *info) {
static int buf_fprintf(void *stream, const char *format, ...) {
va_list ap;
char *tmp;
if (!buf_global || !format)
if (!buf_global || !format) {
return false;
}
va_start (ap, format);
tmp = malloc (strlen (format)+strlen (buf_global)+2);
if (!tmp) {

7
libr/asm/p/asm_ppc_gnu.c
View File

@ -41,13 +41,16 @@ static int buf_fprintf(void *stream, const char *format, ...) {
int flen, glen;
va_list ap;
char *tmp;
if (!buf_global)
if (!buf_global) {
return 0;
}
va_start (ap, format);
flen = strlen (format);
glen = strlen (buf_global);
tmp = malloc (flen + glen + 2);
if (!tmp) return 0;
if (!tmp) {
return 0;
}
memcpy (tmp, buf_global, glen);
memcpy (tmp+glen, format, flen);
tmp[flen+glen] = 0;

9
libr/asm/p/asm_sh.c
View File

@ -32,8 +32,9 @@ static void memory_error_func(int status, bfd_vma memaddr, struct disassemble_in
static void print_address(bfd_vma address, struct disassemble_info *info) {
char tmp[32];
if (!buf_global)
if (!buf_global) {
return;
}
sprintf (tmp, "0x%08"PFMT64x"", (ut64)address);
strcat (buf_global, tmp);
}
@ -42,11 +43,13 @@ static int buf_fprintf(void *stream, const char *format, ...) {
va_list ap;
char *tmp;
int ret;
if (!buf_global)
if (!buf_global) {
return 0;
}
tmp = malloc (strlen (format)+strlen (buf_global)+2);
if (!tmp)
if (!tmp) {
return 0;
}
va_start (ap, format);
sprintf (tmp, "%s%s", buf_global, format);
ret = vsprintf (buf_global, tmp, ap);

24
libr/asm/p/asm_snes.c
View File

@ -10,7 +10,9 @@
static struct snes_asm_flags* snesflags = NULL;
static bool snes_asm_init (void* user) {
if (!snesflags) snesflags = malloc(sizeof( struct snes_asm_flags ));
if (!snesflags) {
snesflags = malloc (sizeof (struct snes_asm_flags));
}
memset(snesflags,0,sizeof (struct snes_asm_flags));
return 0;
}
@ -23,14 +25,24 @@ static bool snes_asm_fini (void* user) {
static int dis(RAsm *a, RAsmOp *op, const ut8 *buf, int len) {
int dlen = snesDisass (snesflags->M, snesflags->X, a->pc, op, buf, len);
if (dlen<0) dlen=0;
if (dlen < 0) {
dlen = 0;
}
op->size = dlen;
if (buf[0] == 0xc2) { //REP
if ( buf[1] & 0x10 ) snesflags->X = 0;
if ( buf[1] & 0x20 ) snesflags->M = 0;
if (buf[1] & 0x10) {
snesflags->X = 0;
}
if (buf[1] & 0x20) {
snesflags->M = 0;
}
} else if (buf[0] == 0xe2) { //SEP
if ( buf[1] & 0x10 ) snesflags->X = 1;
if ( buf[1] & 0x20 ) snesflags->M = 1;
if (buf[1] & 0x10) {
snesflags->X = 1;
}
if (buf[1] & 0x20) {
snesflags->M = 1;
}
}
return dlen;
}

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