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887f5bfa8c
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1221 Commits

Author SHA1 Message Date
Sven Steinbauer
887f5bfa8c Support extended 64bit registers [Fix #5364] 2016-07-25 18:02:46 +02:00
pancake
6c549b424a Remove x86.tab from r2 master (moved to extras) 2016-07-25 03:47:47 +02:00
pancake
845bfebc9e Fix null deref in x86.nz 2016-07-25 03:42:28 +02:00
pancake
91fe80f4ca Fix avr's rjmp disasm, analysis and esil 2016-07-25 03:19:16 +02:00
Maijin
22de895ef5 Rename CSR disasm/anal into XAP4 Fix #5355 2016-07-23 00:41:42 +02:00
Sven Steinbauer
996e767e0d Refactor nz assembler 
Refactor nz assembler
 2016-07-22 18:33:54 +02:00
Maijin
e3a05bdb76 Kill libr/asm/t 2016-07-12 22:51:47 +02:00
Maijin
c274afe748 Fix #3286 - Use stdbool.h 2016-07-12 22:15:19 +02:00
bsmiles32
622e828e1d Add basic support for N64 RSP processor. (#5269) 
* Add basic support for N64 RSP processor.
This includes:
* a table driven instruction decoder (rsp_idec)
* a disassembler
* a very primitive anal plugin
 2016-07-03 22:03:26 +02:00
pancake
2cc433cefa Fixes for avr to make travis green 2016-07-02 02:37:00 +02:00
pancake
9864ef8841 Lowercase all registers to match RReg rules in AVR 2016-07-01 15:22:23 +02:00
Álvaro Felipe Melchor
4396598081 Fix oob read reported by revskill on mk68 code 2016-06-30 23:15:25 +02:00
Álvaro Felipe Melchor
d69a502eb5 fix indentation m68k_disasm 2016-06-30 23:01:24 +02:00
pancake
98e90dd3cf Implement RSyscall.IO in disasm loop for X86 and AVR 2016-06-29 17:02:43 +02:00
pancake
fe644e60ff Fix crash in r2 -a arm -b32 -c'wa str r0' 2016-06-27 15:58:43 +02:00
Sven Steinbauer
2c086751b9 Add fsincos instruction [fix #5204] (#5205) 2016-06-24 15:08:52 +02:00
Sven Steinbauer
995c952c5d Fix #5097 : mov instruction with rex regs 
sil, dil, spl, and bpl, registers now supported
 2016-06-22 13:04:23 +02:00
Sven Steinbauer
db76ef6497 Add bt instruction [fix #1277] (#5194) 2016-06-22 12:31:08 +02:00
Sylvain Pelissier
50aed82b66 Add lfence, mfence and sfence to x86.nz (#5193) 2016-06-22 10:29:26 +02:00
danielps
1b21628964 V810: Fix floating-point instructions (#5186) 2016-06-20 23:39:01 +02:00
pancake
f96f00d62d Fix #5158 - Merge r_db into r_util 2016-06-17 12:19:16 +02:00
Sven Steinbauer
d45101eebe Add offset support to add instruction (#5137) 
support syntax for

add eax, [ecx]
add ecx, [eba +/- 3]
 2016-06-15 15:33:14 +02:00
pancake
e032a48cbe Fix latest 26 COVs 2016-06-14 23:47:58 +02:00
pancake
8a82e5cae6 Implement 'cbz' in armass-thumb 2016-06-13 11:12:20 +02:00
Sven Steinbauer
deebcc5f46 Add check for 64bit overflow (#5116) 2016-06-10 17:02:51 +02:00
Jeffrey Crowell
3e8a0cc693 replace usage of killed r_str_trim 2016-06-10 01:12:07 +00:00
Sven Steinbauer
00e964e9b6 Add support to mov for negative immediates (#5090) 
mov eax, -3
 2016-06-07 12:23:44 +02:00
Sven Steinbauer
6e4a1b55b1 Error if moving 64bit val to 32bit reg (#5088) 
mov eax, 0x1122334455667788 now errors if trying to assemble with -b64.
 2016-06-07 11:01:35 +02:00
pancake
eb9feef231 Fixes for powerpc endian in mach0 and other issues 2016-06-06 22:57:22 +02:00
pancake
608b79d2b4 Finally fix the build on osx-ppc 2016-06-06 17:30:07 +02:00
pancake
5903bc0d10 Fix #5083 - null deref in armass 2016-06-06 16:53:56 +02:00
pancake
d3394d5a7a Fix latest 28 COVs 2016-06-02 03:19:31 +02:00
pancake
03294af32b Fix null deref in libr_asm and add lang-python r2pm pkg 2016-06-02 02:45:38 +02:00
pancake
95b2e511f5 Fix some warnings 2016-06-01 12:23:10 +02:00
Sven Steinbauer
63dd8590d7 Refactor mov assembly for nz (#5057) 
* reg offset code consolidated to single location and simplified
* Refactor `getreg` for `arg` and `arg2` to use `r0` and `r1` throughout
        `mov` case

Should clean it up a little.
 2016-06-01 12:15:33 +02:00
Karol Harasim
d190e0d3c3 Add description for Xtensa instructions 2016-05-31 21:48:18 +02:00
pancake
c64eeaa266 Initial implementation of asm.assembler to select different assembler plugin than the disasm 2016-05-30 18:53:32 +02:00
Duncan Ogilvie
216de66e68 fixed jcc (#5034) 2016-05-30 04:21:02 +02:00
Duncan Ogilvie
021a3ea8b2 Update x86 (#5035) 2016-05-30 04:20:29 +02:00
Duncan Ogilvie
18ffea18cc added/fixed various cmovXX opcodes (#5033) 
As per the Intel manual:

```
CMOVcc - Conditional Move:
| Opcode          | Instruction       | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                            
| 0F 47 /r        | CMOVA r16, r/m16  | RM   | Valid      | Valid          | Move if above (CF=0 and ZF=0).         
| REX.W + 0F 43 /r| CMOVAE r64, r/m64 | RM   | Valid      | N.E.           | Move if above or equal (CF=0).         
| 0F 42 /r        | CMOVB r16, r/m16  | RM   | Valid      | Valid          | Move if below (CF=1).                  
| REX.W + 0F 46 /r| CMOVBE r64, r/m64 | RM   | Valid      | N.E.           | Move if below or equal (CF=1 or ZF=1). 
| 0F 42 /r        | CMOVC r16, r/m16  | RM   | Valid      | Valid          | Move if carry (CF=1).                  
| REX.W + 0F 44 /r| CMOVE r64, r/m64  | RM   | Valid      | N.E.           | Move if equal (ZF=1).                  
| 0F 4F /r        | CMOVG r16, r/m16  | RM   | Valid      | Valid          | Move if greater (ZF=0 and SF=OF).      
| REX.W + 0F 4D /r| CMOVGE r64, r/m64 | RM   | Valid      | N.E.           | Move if greater or equal (SF=OF).      
| 0F 4C /r        | CMOVL r16, r/m16  | RM   | Valid      | Valid          | Move if less (SF!= OF).                 
| REX.W + 0F 4E /r| CMOVLE r64, r/m64 | RM   | Valid      | N.E.           | Move if less or equal (ZF=1 or SF!= OF).
| 0F 46 /r        | CMOVNA r16, r/m16 | RM   | Valid      | Valid          | Move if not above (CF=1 or ZF=1).      
| REX.W + 0F 42 /r| CMOVNAE r64, r/m64| RM   | Valid      | N.E.           | Move if not above or equal (CF=1).     
| 0F 43 /r        | CMOVNB r16, r/m16 | RM   | Valid      | Valid          | Move if not below (CF=0).              
| REX.W + 0F 47 /r| CMOVNBE r64, r/m64| RM   | Valid      | N.E.           | Move if not below or equal (CF=0 and   
|                 |                   |      |            |                | ZF=0).                                 
| 0F 43 /r        | CMOVNC r16, r/m16 | RM   | Valid      | Valid          | Move if not carry (CF=0).              
| REX.W + 0F 45 /r| CMOVNE r64, r/m64 | RM   | Valid      | N.E.           | Move if not equal (ZF=0).              
| 0F 4E /r        | CMOVNG r16, r/m16 | RM   | Valid      | Valid          | Move if not greater (ZF=1 or SF!= OF).  
| REX.W + 0F 4C /r| CMOVNGE r64, r/m64| RM   | Valid      | N.E.           | Move if not greater or equal (SF!= OF). 
| 0F 4D /r        | CMOVNL r16, r/m16 | RM   | Valid      | Valid          | Move if not less (SF=OF).              
| REX.W + 0F 4F /r| CMOVNLE r64, r/m64| RM   | Valid      | N.E.           | Move if not less or equal (ZF=0 and    
|                 |                   |      |            |                | SF=OF).                                
| 0F 41 /r        | CMOVNO r16, r/m16 | RM   | Valid      | Valid          | Move if not overflow (OF=0).           
| REX.W + 0F 4B /r| CMOVNP r64, r/m64 | RM   | Valid      | N.E.           | Move if not parity (PF=0).             
| 0F 49 /r        | CMOVNS r16, r/m16 | RM   | Valid      | Valid          | Move if not sign (SF=0).               
| REX.W + 0F 45 /r| CMOVNZ r64, r/m64 | RM   | Valid      | N.E.           | Move if not zero (ZF=0).               
| 0F 40 /r        | CMOVO r16, r/m16  | RM   | Valid      | Valid          | Move if overflow (OF=1).               
| REX.W + 0F 4A /r| CMOVP r64, r/m64  | RM   | Valid      | N.E.           | Move if parity (PF=1).                 
| 0F 4A /r        | CMOVPE r16, r/m16 | RM   | Valid      | Valid          | Move if parity even (PF=1).            
| REX.W + 0F 4B /r| CMOVPO r64, r/m64 | RM   | Valid      | N.E.           | Move if parity odd (PF=0).             
| 0F 48 /r        | CMOVS r16, r/m16  | RM   | Valid      | Valid          | Move if sign (SF=1).                   
| REX.W + 0F 44 /r| CMOVZ r64, r/m64  | RM   | Valid      | N.E.           | Move if zero (ZF=1).
```

* fixed typo

* or -> nor
 2016-05-30 04:20:19 +02:00
Sven Steinbauer
c58689bae1 Fixes for mov op for nz assembler (#5020) 
A number of fixes and updates to the `mov` command for the nz assembler
including:

* handling of `esp` register in more cases
* able to handle negative offsets for target register both byte and word
* able to handle negative offsets for target with immediate value as
        source, both byte and word
* refactor mov block of code to be more consistent (further work needed)
 2016-05-27 18:11:01 +02:00
Sven Steinbauer
76a4e0ca7a Add support for immediate word for sub (#5006) 
`nz` now generates the correct opcode when using a word as an immediate
in the `sub` instruction with a register + offset as the target

Also adds support for word register offsets and refactors that portion
of the code a little

For 32bit only so far
 2016-05-25 17:22:00 +02:00
jvoisin
4b8af71ef4 Removed a duplicate loopne and loopnz entry 
removed a duplicate `loopne` and `loopnz` entry
 2016-05-25 15:24:13 +02:00
Jeffrey Crowell
2a77791616 add 64bit xchg instruction 
still broken for the special case of xchg (E|R)ax, r(32|64)

but will add that next
 2016-05-24 15:13:37 +00:00
Roman Valls Guimerà
6f66ba9b84 Typo "intro"->"into memory" (#4991) 2016-05-24 16:07:38 +02:00
Anton Kochkov
f6b18bcb56 Fix CID 1356018 2016-05-24 08:54:39 +03:00
Sven Steinbauer
8da8ad740f Cleanup fixes 
* For commit comments and compiler errors
* Fixes for PR comments
* fix some "infer fixes" commits

Signed-off-by: Riccardo Schirone <sirmy15@gmail.com>
 2016-05-23 11:25:44 +02:00
Sven Steinbauer
599b6553e4 Infer fixes for asm 
Signed-off-by: Riccardo Schirone <sirmy15@gmail.com>
 2016-05-23 11:25:44 +02:00
pancake
7f6029f17c Fix OR x86.nz test 2016-05-18 11:17:26 +02:00
pancake
2fd754a76c Fix #4938 - Implement 'or REG, NUM' in the x86.nz assembler 2016-05-18 10:48:48 +02:00