- This check was necessary to fix assertions in decompilations for
arm64
- maxC->getValue().getActiveBits() is used to still alow biger
contants, that can be represented by uint64_t
The original escaping was flawed (for example, it did not escape backslashes,
which caused the produced JSONs to be invalid). The fix is to use json.dump() [1],
which properly escapes all the needed characters.
[1] https://docs.python.org/3/library/json.html#json.dump
* support: Parallelize compilation of YARA rules during installation (#540).
When you run cmake with -DRETDEC_COMPILE_YARA=ON (the default), YARA rules that
RetDec uses are compiled during the installation step, which makes
decompilations run faster (no need to compile them on the fly during each
decompilation). The issue is that YARA rules are compiled sequentially, which
takes around 50 seconds to compile them on my machine.
This commit parallelizes their compilation by using all available cores. Now,
the compilation takes around 10 seconds on my machine (Intel Xeon E5-1650 @
3.60GHz, 6 cores with HT = 12 threads).
* support: Do not create a pool when there are no YARA files to compile.
There is no need to create a thread pool when there are no YARA files to
compile. This saves us a bit of time during each re-install.
RetDec runs the `dot` (or `dot.exe` on Windows) program from Graphivz to convert
the graphs from `.dot` files to PNG files. This program has to be reachable
from PATH. We should mention this as it may not be obvious (see #553).
* Arm64: System registers + bariers + Pseudo for vector registers
* Arm64: Neg instruction can take d registers for some reason
* Arm64: Helper functions to extract value from vector registers
- those are used in simple mov instructions or sometimes in pseudo
* Arm64: Regular ADD can take FP operands + test
- include function decl in header from last commit
* Arm64: PSTATE operands + More systemregs
- fixed FMinMax and Movi vector variants to generate psuedo
* Arm64: Create missing register type
* Arm64: Generate all conditional codes
- Fixed generation of AL and NV conditions
* Arm64: Cond branch tests
- altered the definition of conditional instruction to be only true if
ARM64_CC_INVALID, and generate allways true for AL and NV
* Arm64: Missing B16 register
* Arm64: Temporary solution for Msl shift and stopped ignoring DMB ins
* Arm64: UXTX + SXTX extensions fix
* Arm64: try to solve unhandled regs better
* Arm64: Add and sub can have fp registers as operands
For some reason this is valid and the operation is addition integerwise
* Arm64: Removed debug output
This file defines many symbols that are also defined in winnt.h.
Including it in our headers might cause that both files are included at
one place and name collisions occurr.
