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580.76.05

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This commit is contained in:
Maneet Singh
2025-08-12 12:13:43 -07:00
parent 307159f262
commit 288f16e614
64 changed files with 2037 additions and 863 deletions
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README.md
+12 -3
View File
@@ -1,7 +1,7 @@
# NVIDIA Linux Open GPU Kernel Module Source
This is the source release of the NVIDIA Linux open GPU kernel modules,
version 580.65.06.
version 580.76.05.
## How to Build
@@ -17,7 +17,7 @@ as root:
Note that the kernel modules built here must be used with GSP
firmware and user-space NVIDIA GPU driver components from a corresponding
580.65.06 driver release. This can be achieved by installing
580.76.05 driver release. This can be achieved by installing
the NVIDIA GPU driver from the .run file using the `--no-kernel-modules`
option. E.g.,
@@ -185,7 +185,7 @@ table below).
For details on feature support and limitations, see the NVIDIA GPU driver
end user README here:
https://us.download.nvidia.com/XFree86/Linux-x86_64/580.65.06/README/kernel_open.html
https://us.download.nvidia.com/XFree86/Linux-x86_64/580.76.05/README/kernel_open.html
For vGPU support, please refer to the README.vgpu packaged in the vGPU Host
Package for more details.
@@ -951,6 +951,7 @@ Subsystem Device ID.
| NVIDIA GB200 | 2941 10DE 21CA |
| NVIDIA GeForce RTX 5090 | 2B85 |
| NVIDIA GeForce RTX 5090 D | 2B87 |
| NVIDIA GeForce RTX 5090 D V2 | 2B8C |
| NVIDIA RTX PRO 6000 Blackwell Workstation Edition | 2BB1 1028 204B |
| NVIDIA RTX PRO 6000 Blackwell Workstation Edition | 2BB1 103C 204B |
| NVIDIA RTX PRO 6000 Blackwell Workstation Edition | 2BB1 10DE 204B |
@@ -972,6 +973,10 @@ Subsystem Device ID.
| NVIDIA RTX PRO 4500 Blackwell | 2C31 103C 2051 |
| NVIDIA RTX PRO 4500 Blackwell | 2C31 10DE 2051 |
| NVIDIA RTX PRO 4500 Blackwell | 2C31 17AA 2051 |
| NVIDIA RTX PRO 4000 Blackwell SFF Edition | 2C33 1028 2053 |
| NVIDIA RTX PRO 4000 Blackwell SFF Edition | 2C33 103C 2053 |
| NVIDIA RTX PRO 4000 Blackwell SFF Edition | 2C33 10DE 2053 |
| NVIDIA RTX PRO 4000 Blackwell SFF Edition | 2C33 17AA 2053 |
| NVIDIA RTX PRO 4000 Blackwell | 2C34 1028 2052 |
| NVIDIA RTX PRO 4000 Blackwell | 2C34 103C 2052 |
| NVIDIA RTX PRO 4000 Blackwell | 2C34 10DE 2052 |
@@ -984,6 +989,10 @@ Subsystem Device ID.
| NVIDIA GeForce RTX 5060 | 2D05 |
| NVIDIA GeForce RTX 5070 Laptop GPU | 2D18 |
| NVIDIA GeForce RTX 5060 Laptop GPU | 2D19 |
| NVIDIA RTX PRO 2000 Blackwell | 2D30 1028 2054 |
| NVIDIA RTX PRO 2000 Blackwell | 2D30 103C 2054 |
| NVIDIA RTX PRO 2000 Blackwell | 2D30 10DE 2054 |
| NVIDIA RTX PRO 2000 Blackwell | 2D30 17AA 2054 |
| NVIDIA RTX PRO 2000 Blackwell Generation Laptop GPU | 2D39 |
| NVIDIA GeForce RTX 5070 Laptop GPU | 2D58 |
| NVIDIA GeForce RTX 5060 Laptop GPU | 2D59 |
kernel-open/Kbuild
+1 -1
View File
@@ -79,7 +79,7 @@ ccflags-y += -I$(src)/common/inc
ccflags-y += -I$(src)
ccflags-y += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-format-extra-args
ccflags-y += -D__KERNEL__ -DMODULE -DNVRM
ccflags-y += -DNV_VERSION_STRING=\"580.65.06\"
ccflags-y += -DNV_VERSION_STRING=\"580.76.05\"
# Include and link Tegra out-of-tree modules.
ifneq ($(wildcard /usr/src/nvidia/nvidia-oot),)
kernel-open/common/inc/nv.h
+19 -15
View File
@@ -656,23 +656,24 @@ typedef NV_STATUS (*nvPmaEvictRangeCallback)(void *, NvU64, NvU64, nvgpuGpuMemor
* flags
*/
#define NV_FLAG_OPEN 0x0001
#define NV_FLAG_EXCLUDE 0x0002
#define NV_FLAG_CONTROL 0x0004
#define NV_FLAG_PCI_P2P_UNSUPPORTED_CHIPSET 0x0008
#define NV_FLAG_SOC_DISPLAY 0x0010
#define NV_FLAG_USES_MSI 0x0020
#define NV_FLAG_USES_MSIX 0x0040
#define NV_FLAG_PASSTHRU 0x0080
#define NV_FLAG_SUSPENDED 0x0100
#define NV_FLAG_OPEN 0x0001
#define NV_FLAG_EXCLUDE 0x0002
#define NV_FLAG_CONTROL 0x0004
#define NV_FLAG_PCI_P2P_UNSUPPORTED_CHIPSET 0x0008
#define NV_FLAG_SOC_DISPLAY 0x0010
#define NV_FLAG_USES_MSI 0x0020
#define NV_FLAG_USES_MSIX 0x0040
#define NV_FLAG_PASSTHRU 0x0080
#define NV_FLAG_SUSPENDED 0x0100
#define NV_FLAG_HAS_CONSOLE_IN_SYSMEM_CARVEOUT 0x0200
/* To be set when an FLR needs to be triggered after device shut down. */
#define NV_FLAG_TRIGGER_FLR 0x0400
#define NV_FLAG_PERSISTENT_SW_STATE 0x0800
#define NV_FLAG_IN_RECOVERY 0x1000
#define NV_FLAG_PCI_REMOVE_IN_PROGRESS 0x2000
#define NV_FLAG_UNBIND_LOCK 0x4000
#define NV_FLAG_TRIGGER_FLR 0x0400
#define NV_FLAG_PERSISTENT_SW_STATE 0x0800
#define NV_FLAG_IN_RECOVERY 0x1000
#define NV_FLAG_PCI_REMOVE_IN_PROGRESS 0x2000
#define NV_FLAG_UNBIND_LOCK 0x4000
/* To be set when GPU is not present on the bus, to help device teardown */
#define NV_FLAG_IN_SURPRISE_REMOVAL 0x8000
#define NV_FLAG_IN_SURPRISE_REMOVAL 0x8000
typedef enum
{
@@ -729,6 +730,9 @@ typedef enum
#define NV_IS_DEVICE_IN_SURPRISE_REMOVAL(nv) \
(((nv)->flags & NV_FLAG_IN_SURPRISE_REMOVAL) != 0)
#define NV_HAS_CONSOLE_IN_SYSMEM_CARVEOUT(nv) \
(((nv)->flags & NV_FLAG_HAS_CONSOLE_IN_SYSMEM_CARVEOUT) != 0)
/*
* For console setup by EFI GOP, the base address is BAR1.
* For console setup by VBIOS, the base address is BAR2 + 16MB.
kernel-open/nvidia-uvm/uvm_va_range.c
+2 -1
View File
@@ -785,7 +785,8 @@ static NV_STATUS va_range_add_gpu_va_space_managed(uvm_va_range_managed_t *manag
NV_STATUS status = NV_OK;
const bool should_add_remote_mappings =
uvm_processor_mask_test(&managed_range->policy.accessed_by, gpu->id) ||
uvm_processor_mask_test(&managed_range->va_range.uvm_lite_gpus, gpu->id);
uvm_processor_mask_test(&managed_range->va_range.uvm_lite_gpus, gpu->id) ||
gpu->parent->is_integrated_gpu;
// By this time, the gpu is already in the registration mask.
const bool should_disable_read_duplication =
kernel-open/nvidia/nv.c
+41 -26
View File
@@ -1450,16 +1450,16 @@ static int nv_start_device(nv_state_t *nv, nvidia_stack_t *sp)
{
rc = os_alloc_mutex(&nvl->isr_bh_unlocked_mutex);
if (rc != 0)
goto failed;
goto failed_release_irq;
nv_kthread_q_item_init(&nvl->bottom_half_q_item, nvidia_isr_bh_unlocked, (void *)nv);
rc = nv_kthread_q_init(&nvl->bottom_half_q, nv_device_name);
if (rc != 0)
goto failed;
goto failed_release_irq;
kthread_init = NV_TRUE;
rc = nv_kthread_q_init(&nvl->queue.nvk, "nv_queue");
if (rc)
goto failed;
goto failed_release_irq;
nv->queue = &nvl->queue;
if (nv_platform_use_auto_online(nvl))
@@ -1467,33 +1467,18 @@ static int nv_start_device(nv_state_t *nv, nvidia_stack_t *sp)
rc = nv_kthread_q_init(&nvl->remove_numa_memory_q,
"nv_remove_numa_memory");
if (rc)
goto failed;
goto failed_release_irq;
remove_numa_memory_kthread_init = NV_TRUE;
}
}
if (!rm_init_adapter(sp, nv))
{
if (!(nv->flags & NV_FLAG_USES_MSIX) &&
!(nv->flags & NV_FLAG_SOC_DISPLAY))
{
free_irq(nv->interrupt_line, (void *) nvl);
}
else if (nv->flags & NV_FLAG_SOC_DISPLAY)
{
nv_soc_free_irqs(nv);
}
#if defined(NV_LINUX_PCIE_MSI_SUPPORTED)
else
{
nv_free_msix_irq(nvl);
}
#endif
NV_DEV_PRINTF(NV_DBG_ERRORS, nv,
"rm_init_adapter failed, device minor number %d\n",
nvl->minor_num);
rc = -EIO;
goto failed;
goto failed_release_irq;
}
{
@@ -1527,6 +1512,26 @@ static int nv_start_device(nv_state_t *nv, nvidia_stack_t *sp)
return 0;
failed_release_irq:
if (!(nv->flags & NV_FLAG_PERSISTENT_SW_STATE))
{
if (!(nv->flags & NV_FLAG_USES_MSIX) &&
!(nv->flags & NV_FLAG_SOC_DISPLAY))
{
free_irq(nv->interrupt_line, (void *) nvl);
}
else if (nv->flags & NV_FLAG_SOC_DISPLAY)
{
nv_soc_free_irqs(nv);
}
#if defined(NV_LINUX_PCIE_MSI_SUPPORTED)
else
{
nv_free_msix_irq(nvl);
}
#endif
}
failed:
#if defined(NV_LINUX_PCIE_MSI_SUPPORTED)
if (nv->flags & NV_FLAG_USES_MSI)
@@ -2452,6 +2457,7 @@ nvidia_ioctl(
if (arg_cmd == NV_ESC_WAIT_OPEN_COMPLETE)
{
nv_ioctl_wait_open_complete_t *params = arg_copy;
params->rc = nvlfp->open_rc;
params->adapterStatus = nvlfp->adapter_status;
goto done_early;
@@ -6154,8 +6160,13 @@ void NV_API_CALL nv_get_screen_info(
if (!registered_fb[i])
continue;
/* Make sure base address is mapped to GPU BAR */
if (NV_IS_CONSOLE_MAPPED(nv, registered_fb[i]->fix.smem_start))
/*
* Ensure that either this is a zero-FB SOC GPU with a console in
* the system carveout, or it’s a dGPU device with console mapped
* onto its BAR.
*/
if (NV_HAS_CONSOLE_IN_SYSMEM_CARVEOUT(nv) ||
NV_IS_CONSOLE_MAPPED(nv, registered_fb[i]->fix.smem_start))
{
*pPhysicalAddress = registered_fb[i]->fix.smem_start;
*pFbWidth = registered_fb[i]->var.xres;
@@ -6203,9 +6214,13 @@ void NV_API_CALL nv_get_screen_info(
physAddr |= (NvU64)screen_info.ext_lfb_base << 32;
}
#endif
/* Make sure base address is mapped to GPU BAR */
if (NV_IS_CONSOLE_MAPPED(nv, physAddr))
/*
* Ensure that either this is a zero-FB SOC GPU with a console in the
* system carveout, or it’s a dGPU device with console mapped onto its
* BAR.
*/
if (NV_HAS_CONSOLE_IN_SYSMEM_CARVEOUT(nv) ||
NV_IS_CONSOLE_MAPPED(nv, physAddr))
{
*pPhysicalAddress = physAddr;
*pFbWidth = screen_info.lfb_width;
@@ -6222,7 +6237,7 @@ void NV_API_CALL nv_get_screen_info(
* If screen info can't be fetched with previous methods, then try
* to get the base address and size from the memory resource tree.
*/
if (pci_dev != NULL)
if ((pci_dev != NULL) && !NV_HAS_CONSOLE_IN_SYSMEM_CARVEOUT(nv))
{
BUILD_BUG_ON(NV_GPU_BAR_INDEX_IMEM != NV_GPU_BAR_INDEX_FB + 1);
for (i = NV_GPU_BAR_INDEX_FB; i <= NV_GPU_BAR_INDEX_IMEM; i++)
kernel-open/nvidia/os-interface.c
+1 -1
View File
@@ -2313,7 +2313,7 @@ static int os_numa_verify_gpu_memory_zone(struct notifier_block *nb,
return NOTIFY_OK;
}
#define ADD_REMOVE_GPU_MEMORY_NUM_SEGMENTS 4
#define ADD_REMOVE_GPU_MEMORY_NUM_SEGMENTS 128
NV_STATUS NV_API_CALL os_numa_add_gpu_memory
(
src/common/displayport/inc/dp_connectorimpl.h
+3
View File
@@ -391,6 +391,9 @@ namespace DisplayPort
bool bForceDisableTunnelBwAllocation;
bool bDisableEffBppSST8b10b;
// Use regkey DP_DSC_DEVID_WAR to toggle this flag.
bool bEnableDevId;
Group *perHeadAttachedGroup[NV_MAX_HEADS];
NvU32 inTransitionHeadMask;
src/common/displayport/inc/dp_regkeydatabase.h
+4
View File
@@ -100,6 +100,9 @@
// Bug 5088957 : Force head shutdown in DpLib
#define NV_DP_REGKEY_FORCE_HEAD_SHUTDOWN "DP_WAR_5088957"
// This regkey forces devID to be exposed to vendors via DPCD 0x309 for DSC-enabled SKUs.
#define NV_DP_REGKEY_EXPOSE_DSC_DEVID_WAR "DP_DSC_DEVID_WAR"
//
// Data Base used to store all the regkey values.
// The actual data base is declared statically in dp_evoadapter.cpp.
@@ -142,6 +145,7 @@ struct DP_REGKEY_DATABASE
bool bSkipZeroOuiCache;
bool bEnable5147205Fix;
bool bForceHeadShutdown;
bool bEnableDevId;
};
extern struct DP_REGKEY_DATABASE dpRegkeyDatabase;
src/common/displayport/src/dp_configcaps2x.cpp
+10
View File
@@ -285,6 +285,16 @@ void DPCDHALImpl2x::parseAndReadCaps()
DPCDHALImpl::parseAndReadCaps();
// reset DP tunneling UHBR caps
caps2x.dpInTunnelingCaps.bUHBR_10GSupported = NV_FALSE;
caps2x.dpInTunnelingCaps.bUHBR_13_5GSupported = NV_FALSE;
caps2x.dpInTunnelingCaps.bUHBR_20GSupported = NV_FALSE;
// reset rxCableCaps
caps2x.rxCableCaps.bUHBR_10GSupported = NV_TRUE;
caps2x.rxCableCaps.bUHBR_13_5GSupported = NV_TRUE;
caps2x.rxCableCaps.bUHBR_20GSupported = NV_TRUE;
// 02206h
if (AuxRetry::ack == bus.read(NV_DPCD14_EXTENDED_MAIN_LINK_CHANNEL_CODING, &buffer[0], 1))
{
src/common/displayport/src/dp_connectorimpl.cpp
+21 -3
View File
@@ -51,6 +51,17 @@
#include "ctrl/ctrl0073/ctrl0073dp.h"
#include "dp_tracing.h"
/*
* This is needed by Synaptics to disable DisplayExpand feature
* in some of their docking station based on if GPU supports DSC.
* Feature is not needed if DSC is supported.
* Customers reported problems with the feature enabled on GB20x devices
* and requested GPU DSC detection to disable DisplayExpand feature.
* DSC is supported in Turing and later SKUs hence
* exposing Turing DevId to customers to address their requirement.
*/
#define TURING_DEV_ID 0x1E
using namespace DisplayPort;
ConnectorImpl::ConnectorImpl(MainLink * main, AuxBus * auxBus, Timer * timer, Connector::EventSink * sink)
@@ -184,6 +195,7 @@ void ConnectorImpl::applyRegkeyOverrides(const DP_REGKEY_DATABASE& dpRegkeyDatab
this->bForceDisableTunnelBwAllocation = dpRegkeyDatabase.bForceDisableTunnelBwAllocation;
this->bSkipZeroOuiCache = dpRegkeyDatabase.bSkipZeroOuiCache;
this->bForceHeadShutdownFromRegkey = dpRegkeyDatabase.bForceHeadShutdown;
this->bEnableDevId = dpRegkeyDatabase.bEnableDevId;
this->bDisableEffBppSST8b10b = dpRegkeyDatabase.bDisableEffBppSST8b10b;
}
@@ -3904,14 +3916,20 @@ bool ConnectorImpl::getIgnoreSourceOuiHandshake()
bool ConnectorImpl::performIeeeOuiHandshake()
{
const char *ieeeOuiDevId = "NVIDIA";
NvU8 chipRevision = 0x0;
bool bGpuDscSupported = NV_FALSE;
main->getDscCaps(&bGpuDscSupported);
if ((this->bEnableDevId) && (bGpuDscSupported))
{
chipRevision = TURING_DEV_ID;
}
if (!hal->getOuiSupported() || getIgnoreSourceOuiHandshake())
return false;
if (hal->setOuiSource(DPCD_OUI_NVIDIA, ieeeOuiDevId, 6 /* string length of ieeeOuiDevId */, 0) == AuxRetry::ack)
if (hal->setOuiSource(DPCD_OUI_NVIDIA, ieeeOuiDevId, 6 /* string length of ieeeOuiDevId */, chipRevision) == AuxRetry::ack)
{
NvU8 chipRevision = 0;
// parse client OUI.
if (hal->getOuiSink(ouiId, &modelName[0], sizeof(modelName), chipRevision))
{
src/common/displayport/src/dp_evoadapter.cpp
+2 -1
View File
@@ -106,7 +106,8 @@ const struct
{NV_DP_REGKEY_DISABLE_AVOID_HBR3_WAR, &dpRegkeyDatabase.bDisableAvoidHBR3War, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_SKIP_ZERO_OUI_CACHE, &dpRegkeyDatabase.bSkipZeroOuiCache, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_ENABLE_FIX_FOR_5147205, &dpRegkeyDatabase.bEnable5147205Fix, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_FORCE_HEAD_SHUTDOWN, &dpRegkeyDatabase.bForceHeadShutdown, DP_REG_VAL_BOOL}
{NV_DP_REGKEY_FORCE_HEAD_SHUTDOWN, &dpRegkeyDatabase.bForceHeadShutdown, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_EXPOSE_DSC_DEVID_WAR, &dpRegkeyDatabase.bEnableDevId, DP_REG_VAL_BOOL}
};
EvoMainLink::EvoMainLink(EvoInterface * provider, Timer * timer) :
src/common/displayport/src/dp_wardatabase.cpp
+14
View File
@@ -112,6 +112,20 @@ void ConnectorImpl2x::applyOuiWARs()
}
}
break;
case 0xAD6000:
if ((modelName[0] == 'M') &&
(modelName[1] == 'C') &&
(modelName[2] == '2') &&
(modelName[3] == '9') &&
(modelName[4] == '0'))
{
bForceHeadShutdownPerMonitor = true;
bApplyStuffDummySymbolsWAR = true;
bStuffDummySymbolsFor128b132b = false;
bStuffDummySymbolsFor8b10b = true;
}
break;
}
}
src/common/inc/nvBldVer.h
+10 -10
View File
@@ -36,25 +36,25 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r580_78
#define NV_BUILD_BRANCH r580_92
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r580_78
#define NV_PUBLIC_BRANCH r580_92
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r580/r580_78-179"
#define NV_BUILD_CHANGELIST_NUM (36308443)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r580/r580_92-206"
#define NV_BUILD_CHANGELIST_NUM (36361462)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r580/r580_78-179"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36308443)
#define NV_BUILD_NAME "rel/gpu_drv/r580/r580_92-206"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36361462)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r580_78-7"
#define NV_BUILD_CHANGELIST_NUM (36308443)
#define NV_BUILD_BRANCH_VERSION "r580_92-5"
#define NV_BUILD_CHANGELIST_NUM (36361462)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "580.88"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36308443)
#define NV_BUILD_NAME "580.97"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36361462)
#define NV_BUILD_BRANCH_BASE_VERSION R580
#endif
// End buildmeister python edited section
src/common/inc/nvUnixVersion.h
+1 -1
View File
@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "580.65.06"
#define NV_VERSION_STRING "580.76.05"
#else
src/common/nvswitch/kernel/ls10/tnvl_ls10.c
+2 -1
View File
@@ -977,7 +977,8 @@ nvswitch_tnvl_get_attestation_report_ls10
"%s: Response measurement size (%d) is greater than the attestation max size (%d)\n",
__FUNCTION__,
pRspPayload->measurementSize, NVSWITCH_ATTESTATION_REPORT_MAX_SIZE);
return -NVL_ERR_INVALID_STATE;
status = -NVL_ERR_INVALID_STATE;
goto ErrorExit;
}
nvswitch_os_memcpy(params->attestationReport,
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h
+23
View File
@@ -4196,6 +4196,8 @@ typedef struct NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS {
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_INCORRECT_CHASSIS_SN 3
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_NO_PARTITION 4
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_INSUFFICIENT_NVLINKS 5
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_INCOMPATIBLE_GPU_FW 6
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_INVALID_LOCATION 7
#define NV2080_CTRL_GPU_FABRIC_HEALTH_SUMMARY_NOT_SUPPORTED 0
#define NV2080_CTRL_GPU_FABRIC_HEALTH_SUMMARY_HEALTHY 1
@@ -4731,4 +4733,25 @@ typedef struct NV2080_CTRL_RUSD_GET_SUPPORTED_FEATURES_PARAMS {
NvU32 supportedFeatures;
} NV2080_CTRL_RUSD_GET_SUPPORTED_FEATURES_PARAMS;
/*
* NV2080_CTRL_CMD_GPU_FORCE_GSP_UNLOAD
*
* This command is used to trigger GSP Unload
*
* flags[IN]
* Flags passed by caller - For future use.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INSUFFICIENT_PERMISSIONS
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_GPU_FORCE_GSP_UNLOAD (0x208001ebU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_FORCE_GSP_UNLOAD_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GPU_FORCE_GSP_UNLOAD_PARAMS_MESSAGE_ID (0xebU)
typedef struct NV2080_CTRL_GPU_FORCE_GSP_UNLOAD_PARAMS {
NvU32 flags;
} NV2080_CTRL_GPU_FORCE_GSP_UNLOAD_PARAMS;
/* _ctrl2080gpu_h_ */
src/nvidia/arch/nvalloc/unix/include/nv.h
+19 -15
View File
@@ -656,23 +656,24 @@ typedef NV_STATUS (*nvPmaEvictRangeCallback)(void *, NvU64, NvU64, nvgpuGpuMemor
* flags
*/
#define NV_FLAG_OPEN 0x0001
#define NV_FLAG_EXCLUDE 0x0002
#define NV_FLAG_CONTROL 0x0004
#define NV_FLAG_PCI_P2P_UNSUPPORTED_CHIPSET 0x0008
#define NV_FLAG_SOC_DISPLAY 0x0010
#define NV_FLAG_USES_MSI 0x0020
#define NV_FLAG_USES_MSIX 0x0040
#define NV_FLAG_PASSTHRU 0x0080
#define NV_FLAG_SUSPENDED 0x0100
#define NV_FLAG_OPEN 0x0001
#define NV_FLAG_EXCLUDE 0x0002
#define NV_FLAG_CONTROL 0x0004
#define NV_FLAG_PCI_P2P_UNSUPPORTED_CHIPSET 0x0008
#define NV_FLAG_SOC_DISPLAY 0x0010
#define NV_FLAG_USES_MSI 0x0020
#define NV_FLAG_USES_MSIX 0x0040
#define NV_FLAG_PASSTHRU 0x0080
#define NV_FLAG_SUSPENDED 0x0100
#define NV_FLAG_HAS_CONSOLE_IN_SYSMEM_CARVEOUT 0x0200
/* To be set when an FLR needs to be triggered after device shut down. */
#define NV_FLAG_TRIGGER_FLR 0x0400
#define NV_FLAG_PERSISTENT_SW_STATE 0x0800
#define NV_FLAG_IN_RECOVERY 0x1000
#define NV_FLAG_PCI_REMOVE_IN_PROGRESS 0x2000
#define NV_FLAG_UNBIND_LOCK 0x4000
#define NV_FLAG_TRIGGER_FLR 0x0400
#define NV_FLAG_PERSISTENT_SW_STATE 0x0800
#define NV_FLAG_IN_RECOVERY 0x1000
#define NV_FLAG_PCI_REMOVE_IN_PROGRESS 0x2000
#define NV_FLAG_UNBIND_LOCK 0x4000
/* To be set when GPU is not present on the bus, to help device teardown */
#define NV_FLAG_IN_SURPRISE_REMOVAL 0x8000
#define NV_FLAG_IN_SURPRISE_REMOVAL 0x8000
typedef enum
{
@@ -729,6 +730,9 @@ typedef enum
#define NV_IS_DEVICE_IN_SURPRISE_REMOVAL(nv) \
(((nv)->flags & NV_FLAG_IN_SURPRISE_REMOVAL) != 0)
#define NV_HAS_CONSOLE_IN_SYSMEM_CARVEOUT(nv) \
(((nv)->flags & NV_FLAG_HAS_CONSOLE_IN_SYSMEM_CARVEOUT) != 0)
/*
* For console setup by EFI GOP, the base address is BAR1.
* For console setup by VBIOS, the base address is BAR2 + 16MB.
src/nvidia/arch/nvalloc/unix/include/osapi.h
+2
View File
@@ -178,6 +178,8 @@ void RmUpdateGc6ConsoleRefCount (nv_state_t *, NvBool);
NvBool rm_get_uefi_console_status (nv_state_t *);
NvU64 rm_get_uefi_console_size (nv_state_t *, NvU64 *);
void rm_check_s0ix_regkey_and_platform_support(void);
RM_API *RmUnixRmApiPrologue (nv_state_t *, THREAD_STATE_NODE *, NvU32 module);
void RmUnixRmApiEpilogue (nv_state_t *, THREAD_STATE_NODE *);
src/nvidia/arch/nvalloc/unix/src/dynamic-power.c
+10
View File
@@ -806,6 +806,16 @@ void NV_API_CALL rm_init_tegra_dynamic_power_management(
NV_EXIT_RM_RUNTIME(sp,fp);
}
void rm_check_s0ix_regkey_and_platform_support(void)
{
OBJSYS *pSys = SYS_GET_INSTANCE();
NvU32 data;
NvBool status = ((nv_platform_supports_s0ix()) &&
((osReadRegistryDword(NULL, NV_REG_ENABLE_S0IX_POWER_MANAGEMENT, &data) == NV_OK) && (data == 1)));
pSys->setProperty(pSys, PDB_PROP_SYS_SUPPORTS_S0IX, status);
}
/*!
* @brief Initialize state related to dynamic power management.
* Called once per GPU during driver initialization.
src/nvidia/arch/nvalloc/unix/src/escape.c
+5
View File
@@ -192,6 +192,11 @@ static void RmCreateOsDescriptor(NVOS32_PARAMETERS *pApi, API_SECURITY_INFO secI
}
done:
if (pPteArray != NULL)
{
os_free_mem(pPteArray);
}
if (rmStatus != NV_OK)
pApi->status = rmStatus;
}
src/nvidia/arch/nvalloc/unix/src/os.c
+6 -6
View File
@@ -925,11 +925,11 @@ NV_STATUS osAllocPagesInternal(
// For carveout, the memory is already reserved so we don't have
// to allocate memory.
//
if (memdescGetFlag(pMemDesc, MEMDESC_FLAGS_ALLOC_FROM_SCANOUT_CARVEOUT) ||
if (memdescIsCarveoutMemory(pMemDesc) ||
memdescGetFlag(pMemDesc, MEMDESC_FLAGS_GUEST_ALLOCATED))
{
// We only support scanout carveout with contiguous memory.
if (memdescGetFlag(pMemDesc, MEMDESC_FLAGS_ALLOC_FROM_SCANOUT_CARVEOUT) &&
// We only support carveout with contiguous memory.
if (memdescIsCarveoutMemory(pMemDesc) &&
!memdescGetContiguity(pMemDesc, AT_CPU))
{
status = NV_ERR_NOT_SUPPORTED;
@@ -955,7 +955,7 @@ NV_STATUS osAllocPagesInternal(
cpuCacheAttrib,
memdescGetGuestId(pMemDesc),
memdescGetPteArray(pMemDesc, AT_CPU),
memdescGetFlag(pMemDesc, MEMDESC_FLAGS_ALLOC_FROM_SCANOUT_CARVEOUT),
memdescIsCarveoutMemory(pMemDesc),
&pMemData);
}
else
@@ -3424,7 +3424,7 @@ osIovaMap
// address is same as the DMA address.
//
//
if (memdescGetFlag(pIovaMapping->pPhysMemDesc, MEMDESC_FLAGS_ALLOC_FROM_SCANOUT_CARVEOUT) ||
if (memdescIsCarveoutMemory(pIovaMapping->pPhysMemDesc) ||
memdescGetFlag(pIovaMapping->pPhysMemDesc, MEMDESC_FLAGS_GUEST_ALLOCATED))
{
return NV_OK;
@@ -3597,7 +3597,7 @@ osIovaUnmap
// For guest-allocated or carveout memory, we never actually remapped the
// memory, so we shouldn't try to unmap it here.
//
if (memdescGetFlag(pIovaMapping->pPhysMemDesc, MEMDESC_FLAGS_ALLOC_FROM_SCANOUT_CARVEOUT) ||
if (memdescIsCarveoutMemory(pIovaMapping->pPhysMemDesc) ||
memdescGetFlag(pIovaMapping->pPhysMemDesc, MEMDESC_FLAGS_GUEST_ALLOCATED))
{
return;
src/nvidia/arch/nvalloc/unix/src/osapi.c
+1 -1
View File
@@ -2416,7 +2416,7 @@ static NV_STATUS RmGetAllocPrivate(
bPeerIoMem = memdescGetFlag(pMemDesc, MEMDESC_FLAGS_PEER_IO_MEM);
if (!(pMemDesc->Allocated || bPeerIoMem ||
(memdescGetFlag(pMemDesc, MEMDESC_FLAGS_ALLOC_FROM_SCANOUT_CARVEOUT)) ||
memdescIsCarveoutMemory(pMemDesc) ||
(memdescGetFlag(pMemDesc, MEMDESC_FLAGS_ALLOW_EXT_SYSMEM_USER_CPU_MAPPING))))
{
NV_PRINTF(LEVEL_ERROR, "Mmap is not allowed\n");
src/nvidia/arch/nvalloc/unix/src/osinit.c
+22
View File
@@ -269,6 +269,8 @@ NV_STATUS osRmInitRm(void)
return status;
}
rm_check_s0ix_regkey_and_platform_support();
// Setup any ThreadState defaults
threadStateInitSetupFlags(THREAD_STATE_SETUP_FLAGS_ENABLED |
THREAD_STATE_SETUP_FLAGS_TIMEOUT_ENABLED |
@@ -845,6 +847,11 @@ osInitNvMapping(
{
nv->flags |= NV_FLAG_TRIGGER_FLR;
}
if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_SOC_SDM))
{
nv->flags |= NV_FLAG_HAS_CONSOLE_IN_SYSMEM_CARVEOUT;
}
}
void osInitScalabilityOptions
@@ -1016,6 +1023,21 @@ RmSetConsolePreservationParams(OBJGPU *pGpu)
return;
}
//
// If this is the zero FB SOC GPU with a console in system carveout, then
// the console memory is not mapped onto the BAR. The kernel can directly
// access the console memory, while the GPU accesses system carveout memory
// through the SMMU.
// The carveout is a reserved region of system memory that doesn’t get used
// in standard memory allocation.
//
// In this scenario, you don’t need to reserve console memory or BAR mapping.
//
if (NV_HAS_CONSOLE_IN_SYSMEM_CARVEOUT(nv))
{
return;
}
//
// Check the OS layer for any video memory used by a console
// driver that should be reserved.
src/nvidia/generated/g_gpu_nvoc.c
+11 -1
View File
@@ -513,7 +513,17 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) {
pThis->setProperty(pThis, PDB_PROP_GPU_RUSD_POLLING_SUPPORT_MONOLITHIC, NV_FALSE);
}
pThis->setProperty(pThis, PDB_PROP_GPU_RECOVERY_REBOOT_REQUIRED, NV_FALSE);
pThis->setProperty(pThis, PDB_PROP_GPU_ALLOC_ISO_SYS_MEM_FROM_CARVEOUT, NV_FALSE);
// NVOC Property Hal field -- PDB_PROP_GPU_ALLOC_ISO_SYS_MEM_FROM_CARVEOUT
if (( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000c00UL) )) /* ChipHal: GB20B | GB20C */
{
pThis->setProperty(pThis, PDB_PROP_GPU_ALLOC_ISO_SYS_MEM_FROM_CARVEOUT, NV_TRUE);
}
// default
else
{
pThis->setProperty(pThis, PDB_PROP_GPU_ALLOC_ISO_SYS_MEM_FROM_CARVEOUT, NV_FALSE);
}
pThis->deviceInstance = 32;
src/nvidia/generated/g_gpu_nvoc.h
+5
View File
@@ -1344,6 +1344,7 @@ struct OBJGPU {
DEVICE_MAPPING *pDeviceMappingsByDeviceInstance[13];
void *gpuCfgAddr;
TIMEOUT_DATA timeoutData;
NvU32 bug5203024OverrideTimeouts;
NvU32 computeModeRules;
NvS32 computeModeRefCount;
NvHandle hComputeModeReservation;
@@ -4460,6 +4461,8 @@ NV_STATUS gpuGetNameString_T234D(struct OBJGPU *pGpu, NvU32 arg2, void *arg3);
NV_STATUS gpuGetNameString_FWCLIENT(struct OBJGPU *pGpu, NvU32 arg2, void *arg3);
NV_STATUS gpuGetNameString_GB20B(struct OBJGPU *pGpu, NvU32 arg2, void *arg3);
NV_STATUS gpuGetNameString_IMPL(struct OBJGPU *pGpu, NvU32 arg2, void *arg3);
NV_STATUS gpuGetShortNameString_VF(struct OBJGPU *pGpu, NvU8 *arg2);
@@ -4468,6 +4471,8 @@ NV_STATUS gpuGetShortNameString_T234D(struct OBJGPU *pGpu, NvU8 *arg2);
NV_STATUS gpuGetShortNameString_FWCLIENT(struct OBJGPU *pGpu, NvU8 *arg2);
NV_STATUS gpuGetShortNameString_GB20B(struct OBJGPU *pGpu, NvU8 *arg2);
NV_STATUS gpuGetShortNameString_IMPL(struct OBJGPU *pGpu, NvU8 *arg2);
static inline NV_STATUS gpuInitBranding_56cd7a(struct OBJGPU *pGpu) {
src/nvidia/generated/g_kern_gmmu_nvoc.c
+1 -1
View File
@@ -1048,7 +1048,7 @@ static void __nvoc_init_funcTable_KernelGmmu_1(KernelGmmu *pThis, GpuHalspecOwne
// kgmmuReadShadowBufPutIndex -- halified (2 hals) body
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x70000000UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000006UL) )) /* ChipHal: GH100 | GB100 | GB102 | GB110 | GB112 */
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000fe6UL) )) /* ChipHal: GH100 | GB100 | GB102 | GB110 | GB112 | GB202 | GB203 | GB205 | GB206 | GB207 | GB20B | GB20C */
{
pThis->__kgmmuReadShadowBufPutIndex__ = &kgmmuReadShadowBufPutIndex_GH100;
}
src/nvidia/generated/g_mem_desc_nvoc.h
+12
View File
@@ -123,6 +123,7 @@ typedef NvU32 NV_ADDRESS_SPACE;
typedef NvU32 MEMDESC_CUSTOM_HEAP;
#define MEMDESC_CUSTOM_HEAP_NONE 0
#define MEMDESC_CUSTOM_HEAP_ACR 1
#define MEMDESC_CUSTOM_HEAP_SCANOUT_CARVEOUT 2
//
// Address translation identifiers:
@@ -426,6 +427,7 @@ typedef struct ADDRESS_TRANSLATION_ *ADDRESS_TRANSLATION;
//
#define MEMDESC_FLAGS_ALLOC_AS_LOCALIZED NVBIT64(50)
// Indicate whether memdesc tracks the memory allocated from the scanout-carevout heap.
#define MEMDESC_FLAGS_ALLOC_FROM_SCANOUT_CARVEOUT NVBIT64(51)
// Force-compress pte kind when mapping with virtual pte kind
@@ -441,6 +443,9 @@ typedef struct ADDRESS_TRANSLATION_ *ADDRESS_TRANSLATION;
// Indicate if memdesc is allocated for non IO-coherent memory.
#define MEMDESC_FLAGS_NON_IO_COHERENT NVBIT64(54)
// Indicate if memdesc is tracking the uefi carveout memory.
#define MEMDESC_FLAGS_ALLOC_FROM_UEFI_CARVEOUT NVBIT64(55)
//
// RM internal allocations owner tags
// Total 200 tags are introduced, out of which some are already
@@ -1216,6 +1221,13 @@ NV_STATUS memdescFillMemdescForPhysAttr(MEMORY_DESCRIPTOR *pMemDesc, ADDRESS_TRA
NvBool memdescIsEgm(MEMORY_DESCRIPTOR *pMemDesc);
NvU64 memdescGetAdjustedPageSize(MEMORY_DESCRIPTOR *pMemDesc);
static inline NvBool
memdescIsCarveoutMemory(MEMORY_DESCRIPTOR *pMemDesc)
{
return !!(pMemDesc->_flags & (MEMDESC_FLAGS_ALLOC_FROM_SCANOUT_CARVEOUT |
MEMDESC_FLAGS_ALLOC_FROM_UEFI_CARVEOUT));
}
/*!
* @brief Get PTE kind
*
src/nvidia/generated/g_mem_mgr_nvoc.c
+115 -5
View File
@@ -541,14 +541,28 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, GpuHalsp
pThis->__memmgrInitFbRegions__ = &memmgrInitFbRegions_IMPL;
}
// memmgrAllocateConsoleRegion -- halified (2 hals) body
// memmgrAllocateConsoleRegion -- halified (4 hals) body
if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
{
pThis->__memmgrAllocateConsoleRegion__ = &memmgrAllocateConsoleRegion_56cd7a;
}
else
{
pThis->__memmgrAllocateConsoleRegion__ = &memmgrAllocateConsoleRegion_IMPL;
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x80000000UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000c00UL) )) /* ChipHal: GB10B | GB20B | GB20C */
{
pThis->__memmgrAllocateConsoleRegion__ = &memmgrAllocateConsoleRegion_GB10B;
}
else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x71f0ffe0UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e6UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 | GB100 | GB102 | GB110 | GB112 | GB202 | GB203 | GB205 | GB206 | GB207 */
{
pThis->__memmgrAllocateConsoleRegion__ = &memmgrAllocateConsoleRegion_GM107;
}
// default
else
{
pThis->__memmgrAllocateConsoleRegion__ = &memmgrAllocateConsoleRegion_56cd7a;
}
}
// memmgrScrubHandlePostSchedulingEnable -- halified (2 hals) body
@@ -1334,6 +1348,102 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, GpuHalsp
pThis->__memmgrGetFBEndReserveSizeEstimate__ = &memmgrGetFBEndReserveSizeEstimate_GM107;
}
// memmgrInitZeroFbRegionsHal -- halified (2 hals) body
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x80000000UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000c00UL) )) /* ChipHal: GB10B | GB20B | GB20C */
{
pThis->__memmgrInitZeroFbRegionsHal__ = &memmgrInitZeroFbRegionsHal_GB10B;
}
// default
else
{
pThis->__memmgrInitZeroFbRegionsHal__ = &memmgrInitZeroFbRegionsHal_56cd7a;
}
// memmgrAllocScanoutCarveoutRegionResources -- halified (2 hals) body
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x80000000UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000c00UL) )) /* ChipHal: GB10B | GB20B | GB20C */
{
pThis->__memmgrAllocScanoutCarveoutRegionResources__ = &memmgrAllocScanoutCarveoutRegionResources_GB10B;
}
// default
else
{
pThis->__memmgrAllocScanoutCarveoutRegionResources__ = &memmgrAllocScanoutCarveoutRegionResources_46f6a7;
}
// memmgrAllocFromScanoutCarveoutRegion -- halified (2 hals) body
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x80000000UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000c00UL) )) /* ChipHal: GB10B | GB20B | GB20C */
{
pThis->__memmgrAllocFromScanoutCarveoutRegion__ = &memmgrAllocFromScanoutCarveoutRegion_GB10B;
}
// default
else
{
pThis->__memmgrAllocFromScanoutCarveoutRegion__ = &memmgrAllocFromScanoutCarveoutRegion_46f6a7;
}
// memmgrFreeScanoutCarveoutRegionResources -- halified (2 hals) body
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x80000000UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000c00UL) )) /* ChipHal: GB10B | GB20B | GB20C */
{
pThis->__memmgrFreeScanoutCarveoutRegionResources__ = &memmgrFreeScanoutCarveoutRegionResources_GB10B;
}
// default
else
{
pThis->__memmgrFreeScanoutCarveoutRegionResources__ = &memmgrFreeScanoutCarveoutRegionResources_b3696a;
}
// memmgrFreeFromScanoutCarveoutRegion -- halified (2 hals) body
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x80000000UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000c00UL) )) /* ChipHal: GB10B | GB20B | GB20C */
{
pThis->__memmgrFreeFromScanoutCarveoutRegion__ = &memmgrFreeFromScanoutCarveoutRegion_GB10B;
}
// default
else
{
pThis->__memmgrFreeFromScanoutCarveoutRegion__ = &memmgrFreeFromScanoutCarveoutRegion_b3696a;
}
// memmgrCreateScanoutCarveoutHeap -- halified (2 hals) body
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x80000000UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000c00UL) )) /* ChipHal: GB10B | GB20B | GB20C */
{
pThis->__memmgrCreateScanoutCarveoutHeap__ = &memmgrCreateScanoutCarveoutHeap_GB10B;
}
// default
else
{
pThis->__memmgrCreateScanoutCarveoutHeap__ = &memmgrCreateScanoutCarveoutHeap_46f6a7;
}
// memmgrDestroyScanoutCarveoutHeap -- halified (2 hals) body
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x80000000UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000c00UL) )) /* ChipHal: GB10B | GB20B | GB20C */
{
pThis->__memmgrDestroyScanoutCarveoutHeap__ = &memmgrDestroyScanoutCarveoutHeap_GB10B;
}
// default
else
{
pThis->__memmgrDestroyScanoutCarveoutHeap__ = &memmgrDestroyScanoutCarveoutHeap_46f6a7;
}
// memmgrDuplicateFromScanoutCarveoutRegion -- halified (2 hals) body
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x80000000UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000c00UL) )) /* ChipHal: GB10B | GB20B | GB20C */
{
pThis->__memmgrDuplicateFromScanoutCarveoutRegion__ = &memmgrDuplicateFromScanoutCarveoutRegion_GB10B;
}
// default
else
{
pThis->__memmgrDuplicateFromScanoutCarveoutRegion__ = &memmgrDuplicateFromScanoutCarveoutRegion_46f6a7;
}
// memmgrIsMemoryIoCoherent -- halified (2 hals) body
if (( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000c00UL) )) /* ChipHal: GB20B | GB20C */
{
@@ -1380,13 +1490,13 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, GpuHalsp
{
pThis->__memmgrGetLocalizedMemorySupported__ = &memmgrGetLocalizedMemorySupported_3dd2c9;
}
} // End __nvoc_init_funcTable_MemoryManager_1 with approximately 175 basic block(s).
} // End __nvoc_init_funcTable_MemoryManager_1 with approximately 193 basic block(s).
// Initialize vtable(s) for 91 virtual method(s).
// Initialize vtable(s) for 99 virtual method(s).
void __nvoc_init_funcTable_MemoryManager(MemoryManager *pThis, GpuHalspecOwner *pGpuhalspecowner, RmHalspecOwner *pRmhalspecowner) {
// Initialize vtable(s) with 77 per-object function pointer(s).
// Initialize vtable(s) with 85 per-object function pointer(s).
__nvoc_init_funcTable_MemoryManager_1(pThis, pGpuhalspecowner, pRmhalspecowner);
}
src/nvidia/generated/g_mem_mgr_nvoc.h
+133 -14
View File
@@ -501,7 +501,6 @@ struct __nvoc_inner_struc_MemoryManager_2__ {
NvU64 minFBPSize;
NvU32 fbRegionPriority[16];
NvU64 ReservedConsoleDispMemSize;
PMEMORY_DESCRIPTOR pReservedConsoleMemDesc;
NvU32 lowerRangeMag;
NvU32 lowerRangeScale;
NvU32 middleRangeMag;
@@ -536,12 +535,12 @@ struct MemoryManager {
struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; // engstate super
struct MemoryManager *__nvoc_pbase_MemoryManager; // memmgr
// Vtable with 77 per-object function pointers
// Vtable with 85 per-object function pointers
NvU64 (*__memmgrDeterminePageSize__)(struct MemoryManager * /*this*/, NvHandle, NvU64, NvU32, NvU32, NvU32 *, NvU32 *); // halified (2 hals) body
NV_STATUS (*__memmgrFreeHwResources__)(OBJGPU *, struct MemoryManager * /*this*/, FB_ALLOC_INFO *); // halified (2 hals) body
NV_STATUS (*__memmgrCreateHeap__)(struct MemoryManager * /*this*/); // halified (2 hals) body
NV_STATUS (*__memmgrInitFbRegions__)(OBJGPU *, struct MemoryManager * /*this*/); // halified (2 hals) body
NV_STATUS (*__memmgrAllocateConsoleRegion__)(OBJGPU *, struct MemoryManager * /*this*/, FB_REGION_DESCRIPTOR *); // halified (2 hals) body
NV_STATUS (*__memmgrAllocateConsoleRegion__)(OBJGPU *, struct MemoryManager * /*this*/); // halified (4 hals) body
NV_STATUS (*__memmgrScrubHandlePostSchedulingEnable__)(OBJGPU *, struct MemoryManager * /*this*/); // halified (2 hals) body
NV_STATUS (*__memmgrScrubHandlePreSchedulingDisable__)(OBJGPU *, struct MemoryManager * /*this*/); // halified (2 hals) body
NV_STATUS (*__memmgrMemUtilsChannelInitialize__)(OBJGPU *, struct MemoryManager * /*this*/, OBJCHANNEL *); // halified (2 hals) body
@@ -610,6 +609,14 @@ struct MemoryManager {
NV_STATUS (*__memmgrGetBlackListPages__)(OBJGPU *, struct MemoryManager * /*this*/, BLACKLIST_ADDRESS *, NvU32 *); // halified (3 hals) body
NV_STATUS (*__memmgrDiscoverMIGPartitionableMemoryRange__)(OBJGPU *, struct MemoryManager * /*this*/, struct NV_RANGE *); // halified (2 hals) body
NvU32 (*__memmgrGetFBEndReserveSizeEstimate__)(OBJGPU *, struct MemoryManager * /*this*/); // halified (2 hals)
NV_STATUS (*__memmgrInitZeroFbRegionsHal__)(OBJGPU *, struct MemoryManager * /*this*/); // halified (2 hals) body
NV_STATUS (*__memmgrAllocScanoutCarveoutRegionResources__)(struct MemoryManager * /*this*/, NV_MEMORY_ALLOCATION_PARAMS *, NvU32, NvU32 *, MEMORY_DESCRIPTOR *); // halified (2 hals) body
NV_STATUS (*__memmgrAllocFromScanoutCarveoutRegion__)(POBJGPU, struct MemoryManager * /*this*/, NvU32, NV_MEMORY_ALLOCATION_PARAMS *, NvU32 *, PMEMORY_DESCRIPTOR *); // halified (2 hals) body
void (*__memmgrFreeScanoutCarveoutRegionResources__)(struct MemoryManager * /*this*/, NvU64); // halified (2 hals) body
void (*__memmgrFreeFromScanoutCarveoutRegion__)(POBJGPU, struct MemoryManager * /*this*/, PMEMORY_DESCRIPTOR); // halified (2 hals) body
NV_STATUS (*__memmgrCreateScanoutCarveoutHeap__)(OBJGPU *, struct MemoryManager * /*this*/); // halified (2 hals) body
NV_STATUS (*__memmgrDestroyScanoutCarveoutHeap__)(OBJGPU *, struct MemoryManager * /*this*/); // halified (2 hals) body
NV_STATUS (*__memmgrDuplicateFromScanoutCarveoutRegion__)(POBJGPU, struct MemoryManager * /*this*/, PMEMORY_DESCRIPTOR); // halified (2 hals) body
NvBool (*__memmgrIsMemoryIoCoherent__)(OBJGPU *, struct MemoryManager * /*this*/, NV_MEMORY_ALLOCATION_PARAMS *); // halified (2 hals) body
NvU8 (*__memmgrGetLocalizedOffset__)(OBJGPU *, struct MemoryManager * /*this*/); // halified (2 hals) body
NvBool (*__memmgrIsFlaSysmemSupported__)(OBJGPU *, struct MemoryManager * /*this*/); // halified (2 hals) body
@@ -619,6 +626,7 @@ struct MemoryManager {
// NvBool PDB_PROP_MEMMGR_IS_MISSING inherited from OBJENGSTATE
// Data members
OBJEHEAP *pScanoutHeap;
NvBool bFbsrWddmModeEnabled;
NvBool bFbRegionsSupported;
NvBool bPmaSupportedOnPlatform;
@@ -674,6 +682,7 @@ struct MemoryManager {
NvBool bDisableGlobalCeUtils;
OBJSCRUB eccScrubberState;
struct __nvoc_inner_struc_MemoryManager_2__ Ram;
PMEMORY_DESCRIPTOR pReservedConsoleMemDesc;
NvU32 PteKindOverride;
NvU32 zbcSurfaces;
NvU64 overrideInitHeapMin;
@@ -1110,12 +1119,12 @@ static inline NV_STATUS memmgrReserveVbiosVgaRegions(OBJGPU *pGpu, struct Memory
#endif // __nvoc_mem_mgr_h_disabled
#ifdef __nvoc_mem_mgr_h_disabled
static inline NV_STATUS memmgrReserveConsoleRegion(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_REGION_DESCRIPTOR *arg3) {
static inline NV_STATUS memmgrReserveConsoleRegion(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) {
NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!");
return NV_ERR_NOT_SUPPORTED;
}
#else // __nvoc_mem_mgr_h_disabled
#define memmgrReserveConsoleRegion(pGpu, pMemoryManager, arg3) memmgrReserveConsoleRegion_56cd7a(pGpu, pMemoryManager, arg3)
#define memmgrReserveConsoleRegion(pGpu, pMemoryManager) memmgrReserveConsoleRegion_56cd7a(pGpu, pMemoryManager)
#endif // __nvoc_mem_mgr_h_disabled
void memmgrReleaseConsoleRegion_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager);
@@ -1727,7 +1736,7 @@ static inline NV_STATUS memmgrGetCarveoutRegionInfo(POBJGPU pGpu, struct MemoryM
return NV_ERR_NOT_SUPPORTED;
}
#else // __nvoc_mem_mgr_h_disabled
#define memmgrGetCarveoutRegionInfo(pGpu, pMemoryManager, pParams) memmgrGetCarveoutRegionInfo_56cd7a(pGpu, pMemoryManager, pParams)
#define memmgrGetCarveoutRegionInfo(pGpu, pMemoryManager, pParams) memmgrGetCarveoutRegionInfo_KERNEL(pGpu, pMemoryManager, pParams)
#endif // __nvoc_mem_mgr_h_disabled
@@ -1763,10 +1772,10 @@ static inline NV_STATUS memmgrGetCarveoutRegionInfo(POBJGPU pGpu, struct MemoryM
#define memmgrInitFbRegions(pGpu, pMemoryManager) memmgrInitFbRegions_DISPATCH(pGpu, pMemoryManager)
#define memmgrInitFbRegions_HAL(pGpu, pMemoryManager) memmgrInitFbRegions_DISPATCH(pGpu, pMemoryManager)
#define memmgrReserveVbiosVgaRegions_HAL(pGpu, pMemoryManager) memmgrReserveVbiosVgaRegions(pGpu, pMemoryManager)
#define memmgrReserveConsoleRegion_HAL(pGpu, pMemoryManager, arg3) memmgrReserveConsoleRegion(pGpu, pMemoryManager, arg3)
#define memmgrReserveConsoleRegion_HAL(pGpu, pMemoryManager) memmgrReserveConsoleRegion(pGpu, pMemoryManager)
#define memmgrAllocateConsoleRegion_FNPTR(pMemoryManager) pMemoryManager->__memmgrAllocateConsoleRegion__
#define memmgrAllocateConsoleRegion(pGpu, pMemoryManager, arg3) memmgrAllocateConsoleRegion_DISPATCH(pGpu, pMemoryManager, arg3)
#define memmgrAllocateConsoleRegion_HAL(pGpu, pMemoryManager, arg3) memmgrAllocateConsoleRegion_DISPATCH(pGpu, pMemoryManager, arg3)
#define memmgrAllocateConsoleRegion(pGpu, pMemoryManager) memmgrAllocateConsoleRegion_DISPATCH(pGpu, pMemoryManager)
#define memmgrAllocateConsoleRegion_HAL(pGpu, pMemoryManager) memmgrAllocateConsoleRegion_DISPATCH(pGpu, pMemoryManager)
#define memmgrGetKindComprForGpu_HAL(pMemoryManager, arg2, pGpu, offset, kind, pComprInfo) memmgrGetKindComprForGpu(pMemoryManager, arg2, pGpu, offset, kind, pComprInfo)
#define memmgrScrubInit_HAL(pGpu, pMemoryManager) memmgrScrubInit(pGpu, pMemoryManager)
#define memmgrScrubHandlePostSchedulingEnable_FNPTR(pMemoryManager) pMemoryManager->__memmgrScrubHandlePostSchedulingEnable__
@@ -2001,6 +2010,30 @@ static inline NV_STATUS memmgrGetCarveoutRegionInfo(POBJGPU pGpu, struct MemoryM
#define memmgrFreeFbsrMemory_HAL(pGpu, pMemoryManager) memmgrFreeFbsrMemory(pGpu, pMemoryManager)
#define memmgrReserveVgaWorkspaceMemDescForFbsr_HAL(pGpu, pMemoryManager) memmgrReserveVgaWorkspaceMemDescForFbsr(pGpu, pMemoryManager)
#define memmgrCalculateHeapOffsetWithGSP_HAL(pGpu, pMemoryManager, offset) memmgrCalculateHeapOffsetWithGSP(pGpu, pMemoryManager, offset)
#define memmgrInitZeroFbRegionsHal_FNPTR(pMemoryManager) pMemoryManager->__memmgrInitZeroFbRegionsHal__
#define memmgrInitZeroFbRegionsHal(pGpu, pMemoryManager) memmgrInitZeroFbRegionsHal_DISPATCH(pGpu, pMemoryManager)
#define memmgrInitZeroFbRegionsHal_HAL(pGpu, pMemoryManager) memmgrInitZeroFbRegionsHal_DISPATCH(pGpu, pMemoryManager)
#define memmgrAllocScanoutCarveoutRegionResources_FNPTR(pMemoryManager) pMemoryManager->__memmgrAllocScanoutCarveoutRegionResources__
#define memmgrAllocScanoutCarveoutRegionResources(pMemoryManager, pAllocData, owner, pHeapFlag, pMemDesc) memmgrAllocScanoutCarveoutRegionResources_DISPATCH(pMemoryManager, pAllocData, owner, pHeapFlag, pMemDesc)
#define memmgrAllocScanoutCarveoutRegionResources_HAL(pMemoryManager, pAllocData, owner, pHeapFlag, pMemDesc) memmgrAllocScanoutCarveoutRegionResources_DISPATCH(pMemoryManager, pAllocData, owner, pHeapFlag, pMemDesc)
#define memmgrAllocFromScanoutCarveoutRegion_FNPTR(pMemoryManager) pMemoryManager->__memmgrAllocFromScanoutCarveoutRegion__
#define memmgrAllocFromScanoutCarveoutRegion(pGpu, pMemoryManager, owner, pVidHeapAlloc, pHeapFlag, ppMemDesc) memmgrAllocFromScanoutCarveoutRegion_DISPATCH(pGpu, pMemoryManager, owner, pVidHeapAlloc, pHeapFlag, ppMemDesc)
#define memmgrAllocFromScanoutCarveoutRegion_HAL(pGpu, pMemoryManager, owner, pVidHeapAlloc, pHeapFlag, ppMemDesc) memmgrAllocFromScanoutCarveoutRegion_DISPATCH(pGpu, pMemoryManager, owner, pVidHeapAlloc, pHeapFlag, ppMemDesc)
#define memmgrFreeScanoutCarveoutRegionResources_FNPTR(pMemoryManager) pMemoryManager->__memmgrFreeScanoutCarveoutRegionResources__
#define memmgrFreeScanoutCarveoutRegionResources(pMemoryManager, base) memmgrFreeScanoutCarveoutRegionResources_DISPATCH(pMemoryManager, base)
#define memmgrFreeScanoutCarveoutRegionResources_HAL(pMemoryManager, base) memmgrFreeScanoutCarveoutRegionResources_DISPATCH(pMemoryManager, base)
#define memmgrFreeFromScanoutCarveoutRegion_FNPTR(pMemoryManager) pMemoryManager->__memmgrFreeFromScanoutCarveoutRegion__
#define memmgrFreeFromScanoutCarveoutRegion(pGpu, pMemoryManager, pMemDesc) memmgrFreeFromScanoutCarveoutRegion_DISPATCH(pGpu, pMemoryManager, pMemDesc)
#define memmgrFreeFromScanoutCarveoutRegion_HAL(pGpu, pMemoryManager, pMemDesc) memmgrFreeFromScanoutCarveoutRegion_DISPATCH(pGpu, pMemoryManager, pMemDesc)
#define memmgrCreateScanoutCarveoutHeap_FNPTR(pMemoryManager) pMemoryManager->__memmgrCreateScanoutCarveoutHeap__
#define memmgrCreateScanoutCarveoutHeap(pGpu, pMemoryManager) memmgrCreateScanoutCarveoutHeap_DISPATCH(pGpu, pMemoryManager)
#define memmgrCreateScanoutCarveoutHeap_HAL(pGpu, pMemoryManager) memmgrCreateScanoutCarveoutHeap_DISPATCH(pGpu, pMemoryManager)
#define memmgrDestroyScanoutCarveoutHeap_FNPTR(pMemoryManager) pMemoryManager->__memmgrDestroyScanoutCarveoutHeap__
#define memmgrDestroyScanoutCarveoutHeap(pGpu, pMemoryManager) memmgrDestroyScanoutCarveoutHeap_DISPATCH(pGpu, pMemoryManager)
#define memmgrDestroyScanoutCarveoutHeap_HAL(pGpu, pMemoryManager) memmgrDestroyScanoutCarveoutHeap_DISPATCH(pGpu, pMemoryManager)
#define memmgrDuplicateFromScanoutCarveoutRegion_FNPTR(pMemoryManager) pMemoryManager->__memmgrDuplicateFromScanoutCarveoutRegion__
#define memmgrDuplicateFromScanoutCarveoutRegion(pGpu, pMemoryManager, pMemDesc) memmgrDuplicateFromScanoutCarveoutRegion_DISPATCH(pGpu, pMemoryManager, pMemDesc)
#define memmgrDuplicateFromScanoutCarveoutRegion_HAL(pGpu, pMemoryManager, pMemDesc) memmgrDuplicateFromScanoutCarveoutRegion_DISPATCH(pGpu, pMemoryManager, pMemDesc)
#define memmgrGetCarveoutRegionInfo_HAL(pGpu, pMemoryManager, pParams) memmgrGetCarveoutRegionInfo(pGpu, pMemoryManager, pParams)
#define memmgrIsMemoryIoCoherent_FNPTR(pMemoryManager) pMemoryManager->__memmgrIsMemoryIoCoherent__
#define memmgrIsMemoryIoCoherent(pGpu, pMemoryManager, pAllocData) memmgrIsMemoryIoCoherent_DISPATCH(pGpu, pMemoryManager, pAllocData)
@@ -2076,8 +2109,8 @@ static inline NV_STATUS memmgrInitFbRegions_DISPATCH(OBJGPU *pGpu, struct Memory
return pMemoryManager->__memmgrInitFbRegions__(pGpu, pMemoryManager);
}
static inline NV_STATUS memmgrAllocateConsoleRegion_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_REGION_DESCRIPTOR *arg3) {
return pMemoryManager->__memmgrAllocateConsoleRegion__(pGpu, pMemoryManager, arg3);
static inline NV_STATUS memmgrAllocateConsoleRegion_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) {
return pMemoryManager->__memmgrAllocateConsoleRegion__(pGpu, pMemoryManager);
}
static inline NV_STATUS memmgrScrubHandlePostSchedulingEnable_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) {
@@ -2352,6 +2385,38 @@ static inline NvU32 memmgrGetFBEndReserveSizeEstimate_DISPATCH(OBJGPU *pGpu, str
return pMemoryManager->__memmgrGetFBEndReserveSizeEstimate__(pGpu, pMemoryManager);
}
static inline NV_STATUS memmgrInitZeroFbRegionsHal_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) {
return pMemoryManager->__memmgrInitZeroFbRegionsHal__(pGpu, pMemoryManager);
}
static inline NV_STATUS memmgrAllocScanoutCarveoutRegionResources_DISPATCH(struct MemoryManager *pMemoryManager, NV_MEMORY_ALLOCATION_PARAMS *pAllocData, NvU32 owner, NvU32 *pHeapFlag, MEMORY_DESCRIPTOR *pMemDesc) {
return pMemoryManager->__memmgrAllocScanoutCarveoutRegionResources__(pMemoryManager, pAllocData, owner, pHeapFlag, pMemDesc);
}
static inline NV_STATUS memmgrAllocFromScanoutCarveoutRegion_DISPATCH(POBJGPU pGpu, struct MemoryManager *pMemoryManager, NvU32 owner, NV_MEMORY_ALLOCATION_PARAMS *pVidHeapAlloc, NvU32 *pHeapFlag, PMEMORY_DESCRIPTOR *ppMemDesc) {
return pMemoryManager->__memmgrAllocFromScanoutCarveoutRegion__(pGpu, pMemoryManager, owner, pVidHeapAlloc, pHeapFlag, ppMemDesc);
}
static inline void memmgrFreeScanoutCarveoutRegionResources_DISPATCH(struct MemoryManager *pMemoryManager, NvU64 base) {
pMemoryManager->__memmgrFreeScanoutCarveoutRegionResources__(pMemoryManager, base);
}
static inline void memmgrFreeFromScanoutCarveoutRegion_DISPATCH(POBJGPU pGpu, struct MemoryManager *pMemoryManager, PMEMORY_DESCRIPTOR pMemDesc) {
pMemoryManager->__memmgrFreeFromScanoutCarveoutRegion__(pGpu, pMemoryManager, pMemDesc);
}
static inline NV_STATUS memmgrCreateScanoutCarveoutHeap_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) {
return pMemoryManager->__memmgrCreateScanoutCarveoutHeap__(pGpu, pMemoryManager);
}
static inline NV_STATUS memmgrDestroyScanoutCarveoutHeap_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) {
return pMemoryManager->__memmgrDestroyScanoutCarveoutHeap__(pGpu, pMemoryManager);
}
static inline NV_STATUS memmgrDuplicateFromScanoutCarveoutRegion_DISPATCH(POBJGPU pGpu, struct MemoryManager *pMemoryManager, PMEMORY_DESCRIPTOR pMemDesc) {
return pMemoryManager->__memmgrDuplicateFromScanoutCarveoutRegion__(pGpu, pMemoryManager, pMemDesc);
}
static inline NvBool memmgrIsMemoryIoCoherent_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NV_MEMORY_ALLOCATION_PARAMS *pAllocData) {
return pMemoryManager->__memmgrIsMemoryIoCoherent__(pGpu, pMemoryManager, pAllocData);
}
@@ -2403,7 +2468,7 @@ static inline NV_STATUS memmgrReserveVbiosVgaRegions_56cd7a(OBJGPU *pGpu, struct
}
static inline NV_STATUS memmgrReserveConsoleRegion_56cd7a(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_REGION_DESCRIPTOR *arg3) {
static inline NV_STATUS memmgrReserveConsoleRegion_56cd7a(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) {
return NV_OK;
}
@@ -2580,6 +2645,10 @@ static inline NV_STATUS memmgrCalculateHeapOffsetWithGSP_46f6a7(OBJGPU *pGpu, st
}
NV_STATUS memmgrGetCarveoutRegionInfo_KERNEL(POBJGPU pGpu, struct MemoryManager *pMemoryManager, NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO_PARAMS *pParams);
NV_STATUS memmgrGetCarveoutRegionInfo_GB10B(POBJGPU pGpu, struct MemoryManager *pMemoryManager, NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO_PARAMS *pParams);
static inline NV_STATUS memmgrGetCarveoutRegionInfo_56cd7a(POBJGPU pGpu, struct MemoryManager *pMemoryManager, NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO_PARAMS *pParams) {
return NV_OK;
}
@@ -2625,11 +2694,13 @@ static inline NV_STATUS memmgrInitFbRegions_56cd7a(OBJGPU *pGpu, struct MemoryMa
NV_STATUS memmgrInitFbRegions_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager);
static inline NV_STATUS memmgrAllocateConsoleRegion_56cd7a(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_REGION_DESCRIPTOR *arg3) {
static inline NV_STATUS memmgrAllocateConsoleRegion_56cd7a(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) {
return NV_OK;
}
NV_STATUS memmgrAllocateConsoleRegion_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_REGION_DESCRIPTOR *arg3);
NV_STATUS memmgrAllocateConsoleRegion_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager);
NV_STATUS memmgrAllocateConsoleRegion_GB10B(OBJGPU *pGpu, struct MemoryManager *pMemoryManager);
NV_STATUS memmgrScrubHandlePostSchedulingEnable_GP100(OBJGPU *pGpu, struct MemoryManager *pMemoryManager);
@@ -3087,6 +3158,54 @@ NvU32 memmgrGetFBEndReserveSizeEstimate_GB100(OBJGPU *pGpu, struct MemoryManager
NvU32 memmgrGetFBEndReserveSizeEstimate_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager);
NV_STATUS memmgrInitZeroFbRegionsHal_GB10B(OBJGPU *pGpu, struct MemoryManager *pMemoryManager);
static inline NV_STATUS memmgrInitZeroFbRegionsHal_56cd7a(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) {
return NV_OK;
}
NV_STATUS memmgrAllocScanoutCarveoutRegionResources_GB10B(struct MemoryManager *pMemoryManager, NV_MEMORY_ALLOCATION_PARAMS *pAllocData, NvU32 owner, NvU32 *pHeapFlag, MEMORY_DESCRIPTOR *pMemDesc);
static inline NV_STATUS memmgrAllocScanoutCarveoutRegionResources_46f6a7(struct MemoryManager *pMemoryManager, NV_MEMORY_ALLOCATION_PARAMS *pAllocData, NvU32 owner, NvU32 *pHeapFlag, MEMORY_DESCRIPTOR *pMemDesc) {
return NV_ERR_NOT_SUPPORTED;
}
NV_STATUS memmgrAllocFromScanoutCarveoutRegion_GB10B(POBJGPU pGpu, struct MemoryManager *pMemoryManager, NvU32 owner, NV_MEMORY_ALLOCATION_PARAMS *pVidHeapAlloc, NvU32 *pHeapFlag, PMEMORY_DESCRIPTOR *ppMemDesc);
static inline NV_STATUS memmgrAllocFromScanoutCarveoutRegion_46f6a7(POBJGPU pGpu, struct MemoryManager *pMemoryManager, NvU32 owner, NV_MEMORY_ALLOCATION_PARAMS *pVidHeapAlloc, NvU32 *pHeapFlag, PMEMORY_DESCRIPTOR *ppMemDesc) {
return NV_ERR_NOT_SUPPORTED;
}
void memmgrFreeScanoutCarveoutRegionResources_GB10B(struct MemoryManager *pMemoryManager, NvU64 base);
static inline void memmgrFreeScanoutCarveoutRegionResources_b3696a(struct MemoryManager *pMemoryManager, NvU64 base) {
return;
}
void memmgrFreeFromScanoutCarveoutRegion_GB10B(POBJGPU pGpu, struct MemoryManager *pMemoryManager, PMEMORY_DESCRIPTOR pMemDesc);
static inline void memmgrFreeFromScanoutCarveoutRegion_b3696a(POBJGPU pGpu, struct MemoryManager *pMemoryManager, PMEMORY_DESCRIPTOR pMemDesc) {
return;
}
NV_STATUS memmgrCreateScanoutCarveoutHeap_GB10B(OBJGPU *pGpu, struct MemoryManager *pMemoryManager);
static inline NV_STATUS memmgrCreateScanoutCarveoutHeap_46f6a7(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) {
return NV_ERR_NOT_SUPPORTED;
}
NV_STATUS memmgrDestroyScanoutCarveoutHeap_GB10B(OBJGPU *pGpu, struct MemoryManager *pMemoryManager);
static inline NV_STATUS memmgrDestroyScanoutCarveoutHeap_46f6a7(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) {
return NV_ERR_NOT_SUPPORTED;
}
NV_STATUS memmgrDuplicateFromScanoutCarveoutRegion_GB10B(POBJGPU pGpu, struct MemoryManager *pMemoryManager, PMEMORY_DESCRIPTOR pMemDesc);
static inline NV_STATUS memmgrDuplicateFromScanoutCarveoutRegion_46f6a7(POBJGPU pGpu, struct MemoryManager *pMemoryManager, PMEMORY_DESCRIPTOR pMemDesc) {
return NV_ERR_NOT_SUPPORTED;
}
NvBool memmgrIsMemoryIoCoherent_GB20B(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NV_MEMORY_ALLOCATION_PARAMS *pAllocData);
static inline NvBool memmgrIsMemoryIoCoherent_88bc07(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NV_MEMORY_ALLOCATION_PARAMS *pAllocData) {
src/nvidia/generated/g_nv_name_released.h
+9
View File
@@ -5416,6 +5416,7 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x2941, 0x21ca, 0x10de, "NVIDIA GB200" },
{ 0x2B85, 0x0000, 0x0000, "NVIDIA GeForce RTX 5090" },
{ 0x2B87, 0x0000, 0x0000, "NVIDIA GeForce RTX 5090 D" },
{ 0x2B8C, 0x0000, 0x0000, "NVIDIA GeForce RTX 5090 D V2" },
{ 0x2BB1, 0x204b, 0x1028, "NVIDIA RTX PRO 6000 Blackwell Workstation Edition" },
{ 0x2BB1, 0x204b, 0x103c, "NVIDIA RTX PRO 6000 Blackwell Workstation Edition" },
{ 0x2BB1, 0x204b, 0x10de, "NVIDIA RTX PRO 6000 Blackwell Workstation Edition" },
@@ -5437,6 +5438,10 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x2C31, 0x2051, 0x103c, "NVIDIA RTX PRO 4500 Blackwell" },
{ 0x2C31, 0x2051, 0x10de, "NVIDIA RTX PRO 4500 Blackwell" },
{ 0x2C31, 0x2051, 0x17aa, "NVIDIA RTX PRO 4500 Blackwell" },
{ 0x2C33, 0x2053, 0x1028, "NVIDIA RTX PRO 4000 Blackwell SFF Edition" },
{ 0x2C33, 0x2053, 0x103c, "NVIDIA RTX PRO 4000 Blackwell SFF Edition" },
{ 0x2C33, 0x2053, 0x10de, "NVIDIA RTX PRO 4000 Blackwell SFF Edition" },
{ 0x2C33, 0x2053, 0x17aa, "NVIDIA RTX PRO 4000 Blackwell SFF Edition" },
{ 0x2C34, 0x2052, 0x1028, "NVIDIA RTX PRO 4000 Blackwell" },
{ 0x2C34, 0x2052, 0x103c, "NVIDIA RTX PRO 4000 Blackwell" },
{ 0x2C34, 0x2052, 0x10de, "NVIDIA RTX PRO 4000 Blackwell" },
@@ -5449,6 +5454,10 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x2D05, 0x0000, 0x0000, "NVIDIA GeForce RTX 5060" },
{ 0x2D18, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070 Laptop GPU" },
{ 0x2D19, 0x0000, 0x0000, "NVIDIA GeForce RTX 5060 Laptop GPU" },
{ 0x2D30, 0x2054, 0x1028, "NVIDIA RTX PRO 2000 Blackwell" },
{ 0x2D30, 0x2054, 0x103c, "NVIDIA RTX PRO 2000 Blackwell" },
{ 0x2D30, 0x2054, 0x10de, "NVIDIA RTX PRO 2000 Blackwell" },
{ 0x2D30, 0x2054, 0x17aa, "NVIDIA RTX PRO 2000 Blackwell" },
{ 0x2D39, 0x0000, 0x0000, "NVIDIA RTX PRO 2000 Blackwell Generation Laptop GPU" },
{ 0x2D58, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070 Laptop GPU" },
{ 0x2D59, 0x0000, 0x0000, "NVIDIA GeForce RTX 5060 Laptop GPU" },
src/nvidia/generated/g_subdevice_nvoc.c
+563 -548
View File
File diff suppressed because it is too large Load Diff
src/nvidia/generated/g_subdevice_nvoc.h
+12
View File
@@ -2932,6 +2932,16 @@ static inline NV_STATUS subdeviceCtrlCmdGpuGetCachedInfo(struct Subdevice *pSubd
#define subdeviceCtrlCmdGpuGetCachedInfo(pSubdevice, pGpuInfoParams) subdeviceCtrlCmdGpuGetCachedInfo_IMPL(pSubdevice, pGpuInfoParams)
#endif // __nvoc_subdevice_h_disabled
NV_STATUS subdeviceCtrlCmdGpuForceGspUnload_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_FORCE_GSP_UNLOAD_PARAMS *pGpuInfoParams);
#ifdef __nvoc_subdevice_h_disabled
static inline NV_STATUS subdeviceCtrlCmdGpuForceGspUnload(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_FORCE_GSP_UNLOAD_PARAMS *pGpuInfoParams) {
NV_ASSERT_FAILED_PRECOMP("Subdevice was disabled!");
return NV_ERR_NOT_SUPPORTED;
}
#else // __nvoc_subdevice_h_disabled
#define subdeviceCtrlCmdGpuForceGspUnload(pSubdevice, pGpuInfoParams) subdeviceCtrlCmdGpuForceGspUnload_IMPL(pSubdevice, pGpuInfoParams)
#endif // __nvoc_subdevice_h_disabled
NV_STATUS subdeviceCtrlCmdGpuGetInfoV2_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_INFO_V2_PARAMS *pGpuInfoParams);
#ifdef __nvoc_subdevice_h_disabled
static inline NV_STATUS subdeviceCtrlCmdGpuGetInfoV2(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_INFO_V2_PARAMS *pGpuInfoParams) {
@@ -7555,6 +7565,8 @@ NV_STATUS subdeviceCtrlCmdGrStaticGetFecsTraceDefines_IMPL(struct Subdevice *pSu
NV_STATUS subdeviceCtrlCmdGpuGetCachedInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_INFO_V2_PARAMS *pGpuInfoParams);
NV_STATUS subdeviceCtrlCmdGpuForceGspUnload_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_FORCE_GSP_UNLOAD_PARAMS *pGpuInfoParams);
NV_STATUS subdeviceCtrlCmdGpuGetInfoV2_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_INFO_V2_PARAMS *pGpuInfoParams);
NV_STATUS subdeviceCtrlCmdGpuGetIpVersion_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS *pGpuIpVersionParams);
src/nvidia/generated/g_system_mem_nvoc.c
+2
View File
@@ -487,8 +487,10 @@ const struct NVOC_EXPORT_INFO __nvoc_export_info__SystemMemory =
/*pExportEntries=*/ __nvoc_exported_method_def_SystemMemory
};
void __nvoc_sysmemDestruct(SystemMemory*);
void __nvoc_dtor_StandardMemory(StandardMemory*);
void __nvoc_dtor_SystemMemory(SystemMemory *pThis) {
__nvoc_sysmemDestruct(pThis);
__nvoc_dtor_StandardMemory(&pThis->__nvoc_base_StandardMemory);
PORT_UNREFERENCED_VARIABLE(pThis);
}
src/nvidia/generated/g_system_mem_nvoc.h
+3
View File
@@ -180,6 +180,9 @@ static inline NV_STATUS sysmemCtrlCmdGetSurfacePhysPages(struct SystemMemory *pS
#define sysmemCtrlCmdGetSurfacePhysPages(pStandardMemory, pParams) sysmemCtrlCmdGetSurfacePhysPages_IMPL(pStandardMemory, pParams)
#endif // __nvoc_system_mem_h_disabled
void sysmemDestruct_IMPL(struct SystemMemory *pSystemMemory);
#define __nvoc_sysmemDestruct(pSystemMemory) sysmemDestruct_IMPL(pSystemMemory)
// Wrapper macros for halified functions
#define sysmemInitAllocRequest_FNPTR(pSystemMemory) pSystemMemory->__sysmemInitAllocRequest__
src/nvidia/generated/g_system_nvoc.c
+1
View File
@@ -116,6 +116,7 @@ void __nvoc_init_dataField_OBJSYS(OBJSYS *pThis) {
pThis->clientListDeferredFreeLimit = 0;
pThis->setProperty(pThis, PDB_PROP_SYS_RECOVERY_REBOOT_REQUIRED, NV_FALSE);
pThis->setProperty(pThis, PDB_PROP_SYS_SUPPORTS_S0IX, (0));
}
NV_STATUS __nvoc_ctor_Object(Object* );
src/nvidia/generated/g_system_nvoc.h
+4 -1
View File
@@ -430,7 +430,7 @@ struct OBJSYS {
struct OBJTRACEABLE *__nvoc_pbase_OBJTRACEABLE; // traceable super
struct OBJSYS *__nvoc_pbase_OBJSYS; // sys
// 35 PDB properties
// 36 PDB properties
NvBool PDB_PROP_SYS_SBIOS_NVIF_POWERMIZER_LIMIT;
NvBool PDB_PROP_SYS_MXM_THERMAL_CONTROL_PRESENT;
NvBool PDB_PROP_SYS_POWER_BATTERY;
@@ -466,6 +466,7 @@ struct OBJSYS {
NvBool PDB_PROP_SYS_DESTRUCTING;
NvBool PDB_PROP_SYS_ALLOW_UNKNOWN_4PART_IDS;
NvBool PDB_PROP_SYS_RECOVERY_REBOOT_REQUIRED;
NvBool PDB_PROP_SYS_SUPPORTS_S0IX;
// Data members
NvU32 apiLockMask;
@@ -619,6 +620,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJSYS;
#define PDB_PROP_SYS_ALLOW_UNKNOWN_4PART_IDS_BASE_NAME PDB_PROP_SYS_ALLOW_UNKNOWN_4PART_IDS
#define PDB_PROP_SYS_RECOVERY_REBOOT_REQUIRED_BASE_CAST
#define PDB_PROP_SYS_RECOVERY_REBOOT_REQUIRED_BASE_NAME PDB_PROP_SYS_RECOVERY_REBOOT_REQUIRED
#define PDB_PROP_SYS_SUPPORTS_S0IX_BASE_CAST
#define PDB_PROP_SYS_SUPPORTS_S0IX_BASE_NAME PDB_PROP_SYS_SUPPORTS_S0IX
NV_STATUS __nvoc_objCreateDynamic_OBJSYS(OBJSYS**, Dynamic*, NvU32, va_list);
src/nvidia/generated/rmconfig.h
+1
View File
@@ -323,6 +323,7 @@
#define RMCFG_FEATURE_VBLANK_CALLBACK 1 // Vblank callback functionality within RM
#define RMCFG_FEATURE_TEGRA_SOC_NVDISPLAY 1 // Tegra SOC NvDisplay Driver
#define RMCFG_FEATURE_TEGRA_SOC_NVDISPLAY_MINIMAL 0 // Enable only those parts of display code which are needed for Tegra SOC NvDisplay Driver
#define RMCFG_FEATURE_TEGRA_SOC_SCANOUT_CARVEOUT 1 // Enable scanout carveout Tegra SOC NvDisplay Driver
#define RMCFG_FEATURE_HEAD_REGIONAL_CRC 1 // Display Head Regional CRC support
#define RMCFG_FEATURE_FEATURE_GH180 1 // RMconfig to encapsulate GH180 features
#define RMCFG_FEATURE_MIG_GFX 1 // RMconfig to encapsulate MIG With GFX support (SMG)
src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h
+1
View File
@@ -221,6 +221,7 @@ typedef struct GspSystemInfo
NvU64 hostPageSize;
NvBool bIsCmcBasedHws;
NvBool bGspNocatEnabled;
NvBool bS0ixSupport;
} GspSystemInfo;
src/nvidia/inc/kernel/gpuvideo/rmifvideng.h
+10 -2
View File
@@ -85,8 +85,16 @@ typedef struct
* You can reorder or change below this point but update version.
* Make sure to align it to 16B as ucode expect 16byte alignment to DMA efficiently.
*/
NvU32 videoPgPmuHandshake; // Handshake between PMU and Video Ucode for SW controlled IDLE signal.
NvU64 rsvd2; // reserved field
NvU32 videoPgPmuHandshake; // Handshake between PMU and Video Ucode for SW controlled IDLE signal.
#if (defined(NVRM) || defined(GB10X_OVERRIDE_TIMEOUT))
NvU32 videngTimeoutMs; // SW WAR for bug 5203864, increasing timeouts on GB10x via regkey RmOverrideInternalTimeoutsMs.
// Specify the timeout value in ms. If the value is 0, do not override the timeouts sent from KMD and/or UMD.
NvU32 rsvd2; // reserved field
#else
NvU64 rsvd2; // reserved field
#endif
} NV_VIDENG_BOOT_PARAMS, *PNV_VIDENG_BOOT_PARAMS;
#endif // RMIFVIDENG_H
src/nvidia/interface/nvrm_registry.h
+57 -10
View File
@@ -64,7 +64,7 @@
// Type Dword
// Change all RM internal timeouts to experiment with Bug 5203024.
//
// Some timeouts may still silently clamp to differnt min/max values and this
// Some timeouts may still silently clamp to different min/max values and this
// regkey does NOT validate their range.
//
#define NV_REG_STR_RM_BUG5203024_OVERRIDE_TIMEOUT "RmOverrideInternalTimeoutsMs"
@@ -74,16 +74,30 @@
#define NV_REG_STR_RM_BUG5203024_OVERRIDE_TIMEOUT_FLAGS_SET_RM_DEFAULT_TIMEOUT 31:31
// Same effect as setting "RmWatchDogTimeOut" to VALUE_MS (converted to seconds)
#define NV_REG_STR_RM_BUG5203024_OVERRIDE_TIMEOUT_FLAGS_SET_RC_WATCHDOG_TIMEOUT 30:30
// Same effect as setting "RmEngineContextSwitchTimeout" to VALUE_MS (converted to usec)
// Same effect as setting "RmEngineContextSwitchTimeoutUs" to VALUE_MS (converted to usec)
#define NV_REG_STR_RM_BUG5203024_OVERRIDE_TIMEOUT_FLAGS_SET_CTXSW_TIMEOUT 29:29
// Currently has no effect
#define NV_REG_STR_RM_BUG5203024_OVERRIDE_TIMEOUT_FLAGS_SET_VIDENG_TIMEOUT 28:28
// Currently has no effect
#define NV_REG_STR_RM_BUG5203024_OVERRIDE_TIMEOUT_FLAGS_SET_PMU_INTERNAL_TIMEOUT 27:27
// Currently has no effect
// Disables FECS watchdog (timeout value is ignored)
#define NV_REG_STR_RM_BUG5203024_OVERRIDE_TIMEOUT_FLAGS_SET_FECS_WATCHDOG_TIMEOUT 26:26
//
// This regkey is experimental
//
// Type Dword
// Change video Watchdog and GP timeouts to experiment with Bug 5203024.
// Stores the timeout value in ms.
// If this regkey is set and has non-zero value, also disables MB timeouts.
//
// Some timeouts may still silently clamp to different min/max values and this
// regkey does NOT validate their range.
//
#define NV_REG_STR_RM_BUG5203024_OVERRIDE_VIDEO_TIMEOUT "RmVideoEngineTimeoutMs"
//
// Type Dword
// Override default RM timeout. Measured in milliseconds.
@@ -1415,6 +1429,33 @@
#define NV_REG_PROCESS_NONSTALL_INTR_IN_LOCKLESS_ISR_DISABLE 0x00000000
#define NV_REG_PROCESS_NONSTALL_INTR_IN_LOCKLESS_ISR_ENABLE 0x00000001
//
// Type: DWORD
// Sets the Initial runlist Context switch timeout value in base 2 microseconds
// (1024 nanosecond timer ticks).
// Default: 0x003fffff base2 usec ~ 4.3 seconds
//
// The lower 31 bits have these limits
// Min: 0x00000002
// Max: 0x7fffffff
// A value of 0 means CTXSW timeout is disabled entirely.
//
// It is possible for a privileged client to change this value for all engines
// using a ctrl call.
//
// If MSB (bit 31) is set, then the timeout value set will be "locked" and the
// ctrl call to change it will fail.
//
#define NV_REG_STR_RM_CTXSW_TIMEOUT "RmEngineContextSwitchTimeoutUs"
#define NV_REG_STR_RM_CTXSW_TIMEOUT_DEFAULT 0x003fffff
#define NV_REG_STR_RM_CTXSW_TIMEOUT_TIME 30:0
#define NV_REG_STR_RM_CTXSW_TIMEOUT_TIME_DISABLE 0x00000000
#define NV_REG_STR_RM_CTXSW_TIMEOUT_LOCK 31:31
#define NV_REG_STR_RM_CTXSW_TIMEOUT_LOCK_FALSE 0x0
#define NV_REG_STR_RM_CTXSW_TIMEOUT_LOCK_TRUE 0x1
#define NV_REG_STR_RM_ROBUST_CHANNELS "RmRobustChannels"
#define NV_REG_STR_RM_ROBUST_CHANNELS_ENABLE 0x00000001
#define NV_REG_STR_RM_ROBUST_CHANNELS_DISABLE 0x00000000
@@ -1426,14 +1467,14 @@
#define NV_REG_STR_RM_RC_WATCHDOG_DEFAULT NV_REG_STR_RM_RC_WATCHDOG_ENABLE
#define NV_REG_STR_RM_WATCHDOG_TIMEOUT "RmWatchDogTimeOut"
#define NV_REG_STR_RM_WATCHDOG_TIMEOUT_LOW 0x00000007
#define NV_REG_STR_RM_WATCHDOG_TIMEOUT_HI 0x0000000C
#define NV_REG_STR_RM_WATCHDOG_TIMEOUT_DEFAULT NV_REG_STR_RM_WATCHDOG_TIMEOUT_LOW
#define NV_REG_STR_RM_WATCHDOG_TIMEOUT_LOW 5
#define NV_REG_STR_RM_WATCHDOG_TIMEOUT_HI 60
#define NV_REG_STR_RM_WATCHDOG_TIMEOUT_DEFAULT 7
#define NV_REG_STR_RM_WATCHDOG_INTERVAL "RmWatchDogInterval"
#define NV_REG_STR_RM_WATCHDOG_INTERVAL_LOW 0x00000007
#define NV_REG_STR_RM_WATCHDOG_INTERVAL_HI 0x0000000C
#define NV_REG_STR_RM_WATCHDOG_INTERVAL_DEFAULT NV_REG_STR_RM_WATCHDOG_INTERVAL_LOW
#define NV_REG_STR_RM_WATCHDOG_INTERVAL "RmWatchDogInterval"
#define NV_REG_STR_RM_WATCHDOG_INTERVAL_LOW 5
#define NV_REG_STR_RM_WATCHDOG_INTERVAL_HI 30
#define NV_REG_STR_RM_WATCHDOG_INTERVAL_DEFAULT 7
// Enable/Disable watchcat in GSP-RM partition
// Default is Enabled
@@ -2664,6 +2705,12 @@
#define NV_REG_STR_RM_FORCE_GR_SCRUBBER_CHANNEL_DISABLE 0x00000000
#define NV_REG_STR_RM_FORCE_GR_SCRUBBER_CHANNEL_ENABLE 0x00000001
// Type DWORD
// Allows extending PMU FB Operationg Timeout (DMA / FBFlush) on certain profiles
// This currently takes effect on GB10X profile only
#define NV_REG_STR_RM_PMU_FB_TIMEOUT_US "RmPmuFBTimeoutUs"
#define NV_REG_STR_RM_PMU_FB_TIMEOUT_US_DEFAULT (0)
//
// Type: Dword
//
src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c
+1
View File
@@ -4925,6 +4925,7 @@ kbusIsDirectMappingAllowed_GM107
}
*bDirectSysMappingAllowed =
(memdescGetCustomHeap(pMemDesc) == MEMDESC_CUSTOM_HEAP_SCANOUT_CARVEOUT) ||
(!(bAllowReflectedMapping) &&
(!memdescGetFlag(pMemDesc, MEMDESC_FLAGS_ENCRYPTED)) &&
(memdescGetGpuCacheAttrib(pMemDesc) != NV_MEMORY_CACHED) &&
src/nvidia/src/kernel/gpu/conf_compute/arch/blackwell/conf_compute_keystore_gb100.c
+41 -36
View File
@@ -79,7 +79,6 @@ confComputeKeyStoreDeriveViaChannel_GB100
const uint8_t *pStr = NULL;
NvU8 curKeySeed[CC_EXPORT_MASTER_KEY_SIZE_BYTES] = {0};
//
// SEC2 Per Channel key support has not been added yet. Hence SEC2 keys need to be restored from keystore.
// For CE, keys would be derived per channel. Replace the return with logic for deriving SEC2 keys
@@ -119,25 +118,6 @@ confComputeKeyStoreDeriveViaChannel_GB100
portMemSet(pKey, 0, sizeof(pConfCompute->channelKeySeed));
return NV_ERR_FATAL_ERROR;
}
//
// IVs are moved to per channel from Blackwell onwards. Hence setting IV to 0.
// In Blackwell, message counter and channel counter start at 0. Channel
// counter is used to track the number of IV rotations done.
//
pKernelChannel->clientKmb.encryptBundle.iv[2] = 0;
pKernelChannel->clientKmb.encryptBundle.iv[1] = 0;
pKernelChannel->clientKmb.encryptBundle.iv[0] = 0;
pKernelChannel->clientKmb.encryptBundle.ivMask[2] = 0;
pKernelChannel->clientKmb.encryptBundle.ivMask[1] = 0;
pKernelChannel->clientKmb.encryptBundle.ivMask[0] = 0;
pKernelChannel->clientKmb.decryptBundle.iv[2] = 0;
pKernelChannel->clientKmb.decryptBundle.iv[1] = 0;
pKernelChannel->clientKmb.decryptBundle.iv[0] = 0;
pKernelChannel->clientKmb.decryptBundle.ivMask[2] = 0;
pKernelChannel->clientKmb.decryptBundle.ivMask[1] = 0;
pKernelChannel->clientKmb.decryptBundle.ivMask[0] = 0;
}
}
@@ -174,6 +154,11 @@ confComputeKeyStoreRetrieveViaChannel_GB100
)
{
if ((ivOperation < CHANNEL_IV_OPERATION_NONE) || (ivOperation >= CHANNEL_IV_OPERATION_INVALID))
{
return NV_ERR_INVALID_ARGUMENT;
}
//
// SEC2 Per Channel key support has not been added yet. Hence SEC2 keys need to be restored from keystore.
// For CE, keys would be derived per channel.
@@ -185,26 +170,46 @@ confComputeKeyStoreRetrieveViaChannel_GB100
}
else if (RM_ENGINE_TYPE_IS_COPY(kchannelGetEngineType(pKernelChannel)))
{
if (ivOperation < CHANNEL_IV_OPERATION_NONE || ivOperation >= CHANNEL_IV_OPERATION_INVALID)
// On Blackwell per-channel CE keys initialize to all zeroes.
if (ivOperation == CHANNEL_IV_OPERATION_INCLUDE_ONLY)
{
return NV_ERR_INVALID_ARGUMENT;
}
const NvBool bIvRotate = (ivOperation == CHANNEL_IV_OPERATION_ROTATE_ONLY)
|| (ivOperation == CHANNEL_IV_OPERATION_INCLUDE_AND_ROTATE);
const NvBool bRotateEncrypt = (rotateOperation == ROTATE_IV_ENCRYPT) || (rotateOperation == ROTATE_IV_ALL_VALID);
const NvBool bRotateDecrypt = (rotateOperation == ROTATE_IV_DECRYPT) || (rotateOperation == ROTATE_IV_ALL_VALID);
NV_ASSERT(rotateOperation == ROTATE_IV_ALL_VALID);
// Handle encryption IV rotation
if (bRotateEncrypt && bIvRotate)
{
confComputeIncChannelCounter(&keyMaterialBundle->encryptBundle);
}
pKernelChannel->clientKmb.encryptBundle.iv[2] = 0;
pKernelChannel->clientKmb.encryptBundle.iv[1] = 0;
pKernelChannel->clientKmb.encryptBundle.iv[0] = 0;
pKernelChannel->clientKmb.encryptBundle.ivMask[2] = 0;
pKernelChannel->clientKmb.encryptBundle.ivMask[1] = 0;
pKernelChannel->clientKmb.encryptBundle.ivMask[0] = 0;
// Handle decryption IV rotation
if (bRotateDecrypt && bIvRotate)
pKernelChannel->clientKmb.decryptBundle.iv[2] = 0;
pKernelChannel->clientKmb.decryptBundle.iv[1] = 0;
pKernelChannel->clientKmb.decryptBundle.iv[0] = 0;
pKernelChannel->clientKmb.decryptBundle.ivMask[2] = 0;
pKernelChannel->clientKmb.decryptBundle.ivMask[1] = 0;
pKernelChannel->clientKmb.decryptBundle.ivMask[0] = 0;
}
else
{
confComputeIncChannelCounter(&keyMaterialBundle->decryptBundle);
keyMaterialBundle->bIsWorkLaunch = NV_FALSE;
const NvBool bIvRotate = (ivOperation == CHANNEL_IV_OPERATION_ROTATE_ONLY) ||
(ivOperation == CHANNEL_IV_OPERATION_INCLUDE_AND_ROTATE);
const NvBool bRotateEncrypt = (rotateOperation == ROTATE_IV_ENCRYPT) ||
(rotateOperation == ROTATE_IV_ALL_VALID);
const NvBool bRotateDecrypt = (rotateOperation == ROTATE_IV_DECRYPT) ||
(rotateOperation == ROTATE_IV_ALL_VALID);
// Handle encryption IV rotation
if (bRotateEncrypt && bIvRotate)
{
confComputeIncChannelCounter(&keyMaterialBundle->encryptBundle);
}
// Handle decryption IV rotation
if (bRotateDecrypt && bIvRotate)
{
confComputeIncChannelCounter(&keyMaterialBundle->decryptBundle);
keyMaterialBundle->bIsWorkLaunch = NV_FALSE;
}
}
}
else
src/nvidia/src/kernel/gpu/dce_client/dce_client_rpc.c
+38 -26
View File
@@ -259,6 +259,7 @@ static NV_STATUS _dceRpcAllocateMemory
{
NvU32 *message_buffer;
NV_ASSERT_OR_RETURN(pRpc != NULL, NV_ERR_INVALID_ARGUMENT);
message_buffer = portMemAllocNonPaged(DCE_MAX_RPC_MSG_SIZE);
if (message_buffer == NULL)
{
@@ -420,8 +421,8 @@ NV_STATUS rpcRmApiControl_dce
NvU32 paramsSize
)
{
OBJGPU *pGpu = (OBJGPU*)pRmApi->pPrivateContext;
OBJRPC *pRpc = GPU_GET_RPC(pGpu);
OBJGPU *pGpu = NULL;
OBJRPC *pRpc = NULL;
rpc_generic_union *msg_data;
rpc_gsp_rm_control_v *rpc_params = NULL;
@@ -429,12 +430,11 @@ NV_STATUS rpcRmApiControl_dce
NV_PRINTF(LEVEL_INFO, "NVRM_RPC_DCE : Prepare and send RmApiControl RPC [cmd:0x%x]\n", cmd);
status = _dceRpcAllocateMemory(pRpc);
if (status != NV_OK)
{
NV_PRINTF(LEVEL_ERROR, "NVRM_RPC_DCE: Memory Allocation Failed\n");
goto done;
}
NV_ASSERT_OR_RETURN(pRmApi != NULL, NV_ERR_INVALID_ARGUMENT);
pGpu = (OBJGPU*)pRmApi->pPrivateContext;
NV_ASSERT_OR_RETURN(pGpu != NULL, NV_ERR_INVALID_STATE);
pRpc = GPU_GET_RPC(pGpu);
NV_ASSERT_OK_OR_RETURN(_dceRpcAllocateMemory(pRpc));
msg_data = _dceRpcGetMessageData(pRpc);
rpc_params = &msg_data->gsp_rm_control_v;
@@ -491,8 +491,8 @@ NV_STATUS rpcRmApiAlloc_dce
NvU32 allocParamSize
)
{
OBJGPU *pGpu = (OBJGPU*)pRmApi->pPrivateContext;
OBJRPC *pRpc = GPU_GET_RPC(pGpu);
OBJGPU *pGpu = NULL;
OBJRPC *pRpc = NULL;
rpc_generic_union *msg_data;
rpc_gsp_rm_alloc_v *rpc_params;
@@ -502,9 +502,11 @@ NV_STATUS rpcRmApiAlloc_dce
NV_PRINTF(LEVEL_INFO, "NVRM_RPC_DCE: Prepare and send RmApiAlloc RPC\n");
NV_ASSERT_OK_OR_GOTO(status,
_dceRpcAllocateMemory(pRpc),
done);
NV_ASSERT_OR_RETURN(pRmApi != NULL, NV_ERR_INVALID_ARGUMENT);
pGpu = (OBJGPU*)pRmApi->pPrivateContext;
NV_ASSERT_OR_RETURN(pGpu != NULL, NV_ERR_INVALID_STATE);
pRpc = GPU_GET_RPC(pGpu);
NV_ASSERT_OK_OR_RETURN(_dceRpcAllocateMemory(pRpc));
msg_data = _dceRpcGetMessageData(pRpc);
rpc_params = &msg_data->gsp_rm_alloc_v;
@@ -567,8 +569,8 @@ done:
NV_STATUS rpcRmApiFree_dce(RM_API *pRmApi, NvHandle hClient, NvHandle hObject)
{
OBJGPU *pGpu = (OBJGPU*)pRmApi->pPrivateContext;
OBJRPC *pRpc = GPU_GET_RPC(pGpu);
OBJGPU *pGpu = NULL;
OBJRPC *pRpc = NULL;
rpc_generic_union *msg_data;
NVOS00_PARAMETERS_v *rpc_params;
@@ -577,8 +579,11 @@ NV_STATUS rpcRmApiFree_dce(RM_API *pRmApi, NvHandle hClient, NvHandle hObject)
NV_PRINTF(LEVEL_INFO, "NVRM_RPC_DCE Free "
"RPC Called for hClient: 0x%x\n", hClient);
status = _dceRpcAllocateMemory(pRpc);
NV_ASSERT_OK_OR_RETURN(status);
NV_ASSERT_OR_RETURN(pRmApi != NULL, NV_ERR_INVALID_ARGUMENT);
pGpu = (OBJGPU*)pRmApi->pPrivateContext;
NV_ASSERT_OR_RETURN(pGpu != NULL, NV_ERR_INVALID_STATE);
pRpc = GPU_GET_RPC(pGpu);
NV_ASSERT_OK_OR_RETURN(_dceRpcAllocateMemory(pRpc));
msg_data = _dceRpcGetMessageData(pRpc);
rpc_params = &msg_data->free_v.params;
@@ -628,8 +633,8 @@ NV_STATUS rpcRmApiDupObject_dce
NvU32 flags
)
{
OBJGPU *pGpu = (OBJGPU*)pRmApi->pPrivateContext;
OBJRPC *pRpc = GPU_GET_RPC(pGpu);
OBJGPU *pGpu = NULL;
OBJRPC *pRpc = NULL;
rpc_generic_union *msg_data;
NVOS55_PARAMETERS_v03_00 *rpc_params = NULL;
@@ -639,8 +644,11 @@ NV_STATUS rpcRmApiDupObject_dce
"RPC Called for hClient: 0x%x\n", hClient);
status = _dceRpcAllocateMemory(pRpc);
NV_ASSERT_OK_OR_RETURN(status);
NV_ASSERT_OR_RETURN(pRmApi != NULL, NV_ERR_INVALID_ARGUMENT);
pGpu = (OBJGPU*)pRmApi->pPrivateContext;
NV_ASSERT_OR_RETURN(pGpu != NULL, NV_ERR_INVALID_STATE);
pRpc = GPU_GET_RPC(pGpu);
NV_ASSERT_OK_OR_RETURN(_dceRpcAllocateMemory(pRpc));
msg_data = _dceRpcGetMessageData(pRpc);
rpc_params = &msg_data->dup_object_v.params;
@@ -687,9 +695,9 @@ rpcDceRmInit_dce
NvBool bInit
)
{
OBJGPU *pGpu = (OBJGPU*)pRmApi->pPrivateContext;
OBJRPC *pRpc = GPU_GET_RPC(pGpu);
DceClient *pDceClientrm = GPU_GET_DCECLIENTRM(pGpu);
OBJGPU *pGpu = NULL;
OBJRPC *pRpc = NULL;
DceClient *pDceClientrm = NULL;
rpc_generic_union *msg_data;
NV_STATUS status = NV_ERR_NOT_SUPPORTED;
@@ -698,8 +706,12 @@ rpcDceRmInit_dce
NV_PRINTF(LEVEL_INFO, "NVRM_RPC_DCE RPC to trigger %s called\n",
bInit ? "RmInitAdapter" : "RmShutdownAdapter");
status = _dceRpcAllocateMemory(pRpc);
NV_ASSERT_OK_OR_RETURN(status);
NV_ASSERT_OR_RETURN(pRmApi != NULL, NV_ERR_INVALID_ARGUMENT);
pGpu = (OBJGPU*)pRmApi->pPrivateContext;
NV_ASSERT_OR_RETURN(pGpu != NULL, NV_ERR_INVALID_STATE);
pRpc = GPU_GET_RPC(pGpu);
pDceClientrm = GPU_GET_DCECLIENTRM(pGpu);
NV_ASSERT_OK_OR_RETURN(_dceRpcAllocateMemory(pRpc));
msg_data = _dceRpcGetMessageData(pRpc);
rpc_params = &msg_data->dce_rm_init_v;
src/nvidia/src/kernel/gpu/disp/kern_disp.c
+3 -9
View File
@@ -1100,10 +1100,7 @@ NV_STATUS kdispOptimizePerFrameOsCallbacks_IMPL
//
kdispServiceAwakenIntr_HAL(pGpu, pKernelDisplay, pThreadState);
if (!IS_GSP_CLIENT(pGpu))
{
exVblankServiceHeadMask = kdispGetDeferredVblankHeadMask(pKernelDisplay);
}
exVblankServiceHeadMask = kdispGetDeferredVblankHeadMask(pKernelDisplay);
for (head = 0; head < kdispGetNumHeads(pKernelDisplay); ++head)
{
@@ -1135,11 +1132,8 @@ NV_STATUS kdispOptimizePerFrameOsCallbacks_IMPL
VBLANKCALLBACK *pCallback = NULL;
NvBool dataValid = NV_FALSE;
if (!IS_GSP_CLIENT(pGpu))
{
// Keep track of which heads that we serviced
vblankServicedHeadMask |= NVBIT(head);
}
// Keep track of which heads that we serviced
vblankServicedHeadMask |= NVBIT(head);
// Clear the intr if we were asked to
if (clearIntr == NV_TRUE)
src/nvidia/src/kernel/gpu/fifo/kernel_channel.c
+26 -9
View File
@@ -753,7 +753,7 @@ kchannelConstruct_IMPL
pKernelChannel->bUseScrubKey = FLD_TEST_DRF(OS04, _FLAGS, _CHANNEL_SKIP_SCRUBBER, _TRUE, pChannelGpfifoParams->flags);
if (pKernelChannel->bCCSecureChannel)
{
ConfidentialCompute* pConfCompute = GPU_GET_CONF_COMPUTE(pGpu);
ConfidentialCompute *pConfCompute = GPU_GET_CONF_COMPUTE(pGpu);
// return early if gpu is not ready to accept work
if ((pConfCompute != NULL) && kchannelCheckIsUserMode(pKernelChannel)
@@ -778,8 +778,18 @@ kchannelConstruct_IMPL
goto cleanup;
}
}
status = kchannelDeriveAndRetrieveKmb_HAL(pGpu, pKernelChannel, &pKernelChannel->clientKmb);
NV_ASSERT_OR_GOTO(status == NV_OK, cleanup);
//
// Retrieve IV from keystore as it needs to be transmitted to GPU.
// On Hopper this will also retrieve the key and IV mask.
// On Blackwell and later the key and IV mask are retrieved after a successful control
// call to GSP-RM to ensure that the keystore and keymanager keyseeds stay in sync.
//
NV_ASSERT_OK_OR_GOTO(status,
confComputeKeyStoreRetrieveViaChannel_HAL(pConfCompute, pKernelChannel, ROTATE_IV_ALL_VALID,
CHANNEL_IV_OPERATION_INCLUDE_ONLY,
&pKernelChannel->clientKmb),
cleanup);
portMemCopy(pChannelGpfifoParams->encryptIv,
sizeof(pChannelGpfifoParams->encryptIv),
@@ -795,7 +805,6 @@ kchannelConstruct_IMPL
sizeof(pChannelGpfifoParams->hmacNonce),
pKernelChannel->clientKmb.hmacBundle.nonce,
sizeof(pKernelChannel->clientKmb.hmacBundle.nonce));
}
// Set TLS state and BAR0 window if we are working with Gr
@@ -937,6 +946,17 @@ kchannelConstruct_IMPL
bRpcAllocated = NV_TRUE;
}
if (pKernelChannel->bCCSecureChannel)
{
ConfidentialCompute *pConfCompute = GPU_GET_CONF_COMPUTE(pGpu);
NV_ASSERT_OK_OR_GOTO(status,
confComputeKeyStoreDeriveViaChannel_HAL(pConfCompute, pKernelChannel,
ROTATE_IV_ALL_VALID,
&pKernelChannel->clientKmb),
cleanup);
}
if (kfifoIsPerRunlistChramEnabled(pKernelFifo) ||
(gpuIsCCorApmFeatureEnabled(pGpu) || bMIGInUse))
{
@@ -4462,12 +4482,9 @@ NV_STATUS kchannelDeriveAndRetrieveKmb_KERNEL
)
{
ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu);
NV_ASSERT(pCC != NULL);
NV_ASSERT_OK_OR_RETURN(confComputeKeyStoreDeriveViaChannel_HAL(pCC, pKernelChannel, ROTATE_IV_ALL_VALID,
keyMaterialBundle));
return (confComputeKeyStoreRetrieveViaChannel_HAL(pCC, pKernelChannel, ROTATE_IV_ALL_VALID,
CHANNEL_IV_OPERATION_INCLUDE_ONLY, keyMaterialBundle));
}
@@ -4538,14 +4555,14 @@ kchannelCtrlCmdGetKmb_KERNEL
NV_ASSERT_OK_OR_RETURN(pRmApi->DupObject(pRmApi, hClient, hDevice,
&pKernelChannel->hEncryptStatsBuf,
hClient, pGetKmbParams->hMemory, 0));
NV_ASSERT_OK_OR_GOTO(status,
NV_ASSERT_OK_OR_GOTO(status,
clientGetResourceRef(pRsClient, pKernelChannel->hEncryptStatsBuf, &pResourceRef),
cleanup);
Memory *pMemory = dynamicCast(pResourceRef->pResource, Memory);
NV_ASSERT_OR_ELSE((pMemory != NULL) && (pMemory->pMemDesc != NULL),
status = NV_ERR_INVALID_ARGUMENT;
goto cleanup);
NV_ASSERT_OK_OR_GOTO(status,
NV_ASSERT_OK_OR_GOTO(status,
kchannelSetEncryptionStatsBuffer_HAL(pGpu, pKernelChannel, pMemory->pMemDesc, NV_TRUE),
cleanup);
}
src/nvidia/src/kernel/gpu/fifo/kernel_channel_group_api.c
+1 -1
View File
@@ -559,7 +559,7 @@ done:
if (rmStatus != NV_OK)
{
// Acquire the lock again for the cleanup path
NV_ASSERT_OK_OR_RETURN(rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_FIFO));
NV_ASSERT_OK_OR_RETURN(rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_FIFO));
bLockAcquired = NV_TRUE;
goto failed;
}
src/nvidia/src/kernel/gpu/gpu_timeout.c
+2
View File
@@ -111,6 +111,8 @@ timeoutRegistryOverride
data32 :
0);
pGpu->bug5203024OverrideTimeouts = bug5203024OverrideTimeouts;
NvBool bOverrideDefaultTimeout = (DRF_VAL(_REG_STR,
_RM_BUG5203024_OVERRIDE_TIMEOUT,
_FLAGS_SET_RM_DEFAULT_TIMEOUT,
src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c
+3
View File
@@ -2698,6 +2698,7 @@ kgspInitVgpuPartitionLogging_IMPL
char sourceName[SOURCE_NAME_MAX_LENGTH];
NvBool bPreserveLogBufferFull = NV_FALSE;
NvBool bMergeNvlog = NV_TRUE;
OBJTMR *pTmr = GPU_GET_TIMER(pGpu);
if (gfid > MAX_PARTITIONS_WITH_GFID)
{
@@ -2800,6 +2801,8 @@ kgspInitVgpuPartitionLogging_IMPL
*pPreserveLogBufferFull = bPreserveLogBufferFull;
libosLogUpdateTimerDelta(&pKernelGsp->logDecodeVgpuPartition[gfid - 1], pTmr->sysTimerOffsetNs);
exit:
if (nvStatus != NV_OK)
_kgspFreeLibosVgpuPartitionLoggingStructures(pGpu, pKernelGsp, gfid);
src/nvidia/src/kernel/gpu/mem_mgr/arch/blackwell/mem_mgr_gb10b_phys.c
+484
View File
@@ -0,0 +1,484 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "core/core.h"
#include "gpu/gpu.h"
#include "os/nv_memory_type.h"
#include "mem_mgr/system_mem.h"
#include "gpu/mem_mgr/mem_mgr.h"
#include "containers/eheap_old.h"
static NV_STATUS _memmgrSocGetScanoutCarveout
(
OBJGPU *pGpu,
NvU64 *pBase,
NvU64 *pSize
)
{
MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu);
NV_STATUS status;
NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO_PARAMS params;
NvU32 i;
portMemSet(&params, 0x0, sizeof(params));
status = memmgrGetCarveoutRegionInfo(pGpu, pMemoryManager, &params);
if (status != NV_OK)
{
return status;
}
*pBase = *pSize = 0;
for (i = 0; i < params.numCarveoutRegions; i++)
{
// On Linux, the complete display FRM will be managed by RM carveout code.
if (params.carveoutRegion[i].carveoutType ==
NV2080_CTRL_FB_GET_CARVEOUT_REGION_CARVEOUT_TYPE_DISPLAY_FRM)
{
*pBase = params.carveoutRegion[i].base;
*pSize = params.carveoutRegion[i].size;
break;
}
}
return NV_OK;
}
/**
* @brief Initializes FB regions
*
* This function is responsible for setting up a carveout if one is required.
* This is a different type of carveout from what has been done on MCP in the
* past. The main difference is that even though it will be treated as "video
* memory", all addresses will be fully resolved system memory addresses. This
* is done by setting up a reserved region of FB from 0 to the sysmem base of
* carveout as described in the picture below.
*
* dGPU Video Memory
* +-----------------------------|
* | Vidmem |
* +-----------------------------|
*
* @returns OK if success, ERROR otherwise
*/
NV_STATUS
memmgrInitZeroFbRegionsHal_GB10B
(
OBJGPU *pGpu,
MemoryManager *pMemoryManager
)
{
NV_STATUS status = NV_OK;
// Simulation won't have carveout support
if (IS_SIMULATION(pGpu))
{
NV_PRINTF(LEVEL_INFO, "Carveout support not available on simulation\n");
return NV_OK;
}
status = memmgrCreateScanoutCarveoutHeap(pGpu, pMemoryManager);
//
// Check if platform has carveout support configured, if not configured,
// return early with NV_OK. In this case, all allocations will happen
// in the system memory itself.
//
if (status == NV_ERR_NOT_SUPPORTED)
{
NV_PRINTF(LEVEL_INFO, "Carveout supported not configured on this platform\n");
return NV_OK;
}
if (status != NV_OK)
{
NV_PRINTF(LEVEL_ERROR, "Failed to create scanout carveout heap.\n");
return status;
}
return status;
}
NV_STATUS
memmgrCreateScanoutCarveoutHeap_GB10B
(
OBJGPU *pGpu,
MemoryManager *pMemoryManager
)
{
NvU64 base, size;
if (_memmgrSocGetScanoutCarveout(pGpu, &base, &size) != NV_OK) {
pGpu->setProperty(pGpu, PDB_PROP_GPU_ALLOC_ISO_SYS_MEM_FROM_CARVEOUT, NV_FALSE);
return NV_OK;
}
pMemoryManager->pScanoutHeap = (OBJEHEAP*)portMemAllocNonPaged(sizeof(OBJEHEAP));
if (pMemoryManager->pScanoutHeap == NULL)
{
return NV_ERR_NO_MEMORY;
}
constructObjEHeap(pMemoryManager->pScanoutHeap, base, base + size, 0, 0);
NV_PRINTF(LEVEL_INFO, "Created scanout carveout heap with base address=0x%llx and size=%llx\n", base, size);
return NV_OK;
}
NV_STATUS
memmgrDestroyScanoutCarveoutHeap_GB10B
(
OBJGPU *pGpu,
MemoryManager *pMemoryManager
)
{
if (pMemoryManager->pScanoutHeap)
{
pMemoryManager->pScanoutHeap->eheapDestruct(pMemoryManager->pScanoutHeap);
portMemFree(pMemoryManager->pScanoutHeap);
pMemoryManager->pScanoutHeap = NULL;
}
return NV_OK;
}
/**
* @brief Allocates memory from scanout carveout region
*
* This function request a free range (base address and size) first from
* scanout carveout heap and update a memory descriptor for that.
* The memory is already reserved, so we can set the physical address with
* memdescSetPte().
*
* @returns OK if success, ERROR otherwise
*/
NV_STATUS
memmgrAllocScanoutCarveoutRegionResources_GB10B
(
MemoryManager *pMemoryManager,
NV_MEMORY_ALLOCATION_PARAMS *pAllocData,
NvU32 heapOwner,
NvU32 *pHeapFlag,
MEMORY_DESCRIPTOR *pMemDesc
)
{
OBJEHEAP *pHeap = pMemoryManager->pScanoutHeap;
NvU64 alignment = pAllocData->alignment;
NvU64 offset = pAllocData->offset;
NvU64 size = pMemDesc->Size;
NV_STATUS status = NV_OK;
NV_CHECK_OR_RETURN(LEVEL_INFO, pHeap != NULL, NV_ERR_INVALID_STATE);
NV_ASSERT(memdescGetFlag(pMemDesc, MEMDESC_FLAGS_ALLOC_FROM_SCANOUT_CARVEOUT));
status = pHeap->eheapAlloc(pHeap, heapOwner, pHeapFlag,
&offset, &size, alignment, alignment,
NULL, NULL, NULL);
if (status != NV_OK) {
NV_PRINTF(LEVEL_ERROR, "EheapAlloc returns error 0x%0x\n", status);
return status;
}
memdescSetPte(pMemDesc, AT_CPU, 0, offset);
memdescSetContiguity(pMemDesc, AT_CPU, NV_TRUE);
pMemDesc->Size = size;
return NV_OK;
}
/**
* @brief Allocates memory from scanout carveout region
*
* This function request a free range (base address and size) first from
* scanout carveout heap and setup a memory descriptor for that.
* The memory is already reserved, so we can set the physical address with
* memdescSetPte().
*
* @returns OK if success, ERROR otherwise
*/
NV_STATUS
memmgrAllocFromScanoutCarveoutRegion_GB10B
(
POBJGPU pGpu,
MemoryManager *pMemoryManager,
NvU32 owner,
NV_MEMORY_ALLOCATION_PARAMS *pVidHeapAlloc,
NvU32 *pHeapFlag,
PMEMORY_DESCRIPTOR *ppMemDesc
)
{
MemorySystem *pMemorySystem = GPU_GET_MEMORY_SYSTEM(pGpu);
MEMORY_DESCRIPTOR *pMemDesc = NULL;
OBJEHEAP *pHeap = pMemoryManager->pScanoutHeap;
NvU64 offset = pVidHeapAlloc->offset;
NvU64 size = pVidHeapAlloc->size;
NV_STATUS status;
NV_CHECK_OR_RETURN(LEVEL_INFO, pMemorySystem != NULL, NV_ERR_INVALID_STATE);
NV_CHECK_OR_RETURN(LEVEL_INFO, pVidHeapAlloc != NULL, NV_ERR_INVALID_ARGUMENT);
NV_CHECK_OR_RETURN(LEVEL_INFO, pHeapFlag != NULL, NV_ERR_INVALID_ARGUMENT);
NV_CHECK_OR_RETURN(LEVEL_INFO, ppMemDesc != NULL, NV_ERR_INVALID_ARGUMENT);
status = memdescCreate(&pMemDesc, pGpu, size, 0, NV_MEMORY_CONTIGUOUS,
ADDR_SYSMEM, NV_MEMORY_UNCACHED,
MEMDESC_FLAGS_ALLOC_FROM_SCANOUT_CARVEOUT);
if (status != NV_OK)
{
NV_PRINTF(LEVEL_ERROR, "memdescCreate returns error 0x%0x\n", status);
DBG_BREAKPOINT();
pHeap->eheapFree(pHeap, offset);
return status;
}
memSetSysmemCacheAttrib(pGpu, pVidHeapAlloc, pMemDesc);
status = memmgrAllocScanoutCarveoutRegionResources(pMemoryManager,
pVidHeapAlloc,
owner,
pHeapFlag,
pMemDesc);
if (status != NV_OK) {
DBG_BREAKPOINT();
memdescDestroy(pMemDesc);
return status;
}
status = memdescAlloc(pMemDesc);
if (status != NV_OK)
{
NV_PRINTF(LEVEL_ERROR, "memdescAlloc returns error 0x%0x\n", status);
DBG_BREAKPOINT();
memdescDestroy(pMemDesc);
memmgrFreeScanoutCarveoutRegionResources(pMemoryManager, offset);
return status;
}
*ppMemDesc = pMemDesc;
pVidHeapAlloc->offset = memdescGetPte(pMemDesc, AT_CPU, 0);
pVidHeapAlloc->size = pMemDesc->Size;
return NV_OK;
}
/**
* @brief Frees memory from scanout carveout region
*
* This function performs free operation for the memory allocated at given base
* offset from scanout carveout region.
*
* @returns void
*/
void
memmgrFreeScanoutCarveoutRegionResources_GB10B
(
MemoryManager *pMemoryManager,
NvU64 base
)
{
OBJEHEAP *pHeap = pMemoryManager->pScanoutHeap;
NV_STATUS status;
EMEMBLOCK *pBlock;
NV_CHECK_OR_RETURN_VOID(LEVEL_INFO, pHeap != NULL);
pBlock = (EMEMBLOCK *)pHeap->eheapGetBlock(pHeap, base, 0);
if (pBlock == NULL)
{
NV_PRINTF(LEVEL_ERROR, "Not found allocation in carveout region");
return;
}
status = pHeap->eheapFree(pHeap, base);
if (status != NV_OK)
{
NV_PRINTF(LEVEL_ERROR, "Error in freeing eheap 0x%0x\n", status);
}
}
/**
* @brief Frees memory from scanout carveout region
*
* This function performs free operation for the memory allocated from scanout
* carveout region.
*
* @returns void
*/
void
memmgrFreeFromScanoutCarveoutRegion_GB10B
(
POBJGPU pGpu,
MemoryManager *pMemoryManager,
PMEMORY_DESCRIPTOR pMemDesc
)
{
OBJEHEAP *pEHeap = pMemoryManager->pScanoutHeap;
NvU64 base;
EMEMBLOCK *pBlock;
NV_CHECK_OR_RETURN_VOID(LEVEL_INFO, pMemDesc != NULL);
NV_CHECK_OR_RETURN_VOID(LEVEL_INFO, pEHeap != NULL);
base = memdescGetPte(pMemDesc, AT_CPU, 0);
pBlock = (EMEMBLOCK *)pEHeap->eheapGetBlock(pEHeap, base, 0);
NV_CHECK_OR_RETURN_VOID(LEVEL_INFO, pBlock != NULL);
//
// If reference count is zero then free the memory descriptor; otherwise
// decrease the reference count (increased by memCopyConstruct_IMPL()).
//
if (pBlock->refCount == 0)
{
memdescFree(pMemDesc);
memdescDestroy(pMemDesc);
}
else
{
memdescRemoveRef(pMemDesc);
}
memmgrFreeScanoutCarveoutRegionResources(pMemoryManager, base);
}
/**
* @brief Duplicate memory descriptor allocated from scanout carveout region.
*
* This function gets the heap block for the scanout carveout memory descriptor
* and increase the reference count.
*
* @returns OK if success, ERROR otherwise
*/
NV_STATUS
memmgrDuplicateFromScanoutCarveoutRegion_GB10B
(
POBJGPU pGpu,
MemoryManager *pMemoryManager,
PMEMORY_DESCRIPTOR pMemDesc
)
{
OBJEHEAP *pEHeap = pMemoryManager->pScanoutHeap;
NvU64 base;
EMEMBLOCK *pBlock;
NV_CHECK_OR_RETURN(LEVEL_INFO, pMemDesc != NULL, NV_ERR_INVALID_ARGUMENT);
NV_CHECK_OR_RETURN(LEVEL_INFO, pEHeap != NULL, NV_ERR_INVALID_STATE);
base = memdescGetPte(pMemDesc, AT_CPU, 0);
pBlock = (EMEMBLOCK *)pEHeap->eheapGetBlock(pEHeap, base, 0);
NV_CHECK_OR_RETURN(LEVEL_INFO, pBlock != NULL, NV_ERR_INVALID_STATE);
pBlock->refCount++;
return NV_OK;
}
/**
* @brief Return the carveout region information.
*
* @returns OK if success, ERROR otherwise
*/
NV_STATUS
memmgrGetCarveoutRegionInfo_KERNEL
(
OBJGPU *pGpu,
MemoryManager *pMemoryManager,
NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO_PARAMS *pParams
)
{
RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu);
return pRmApi->Control(pRmApi,
pGpu->hInternalClient,
pGpu->hInternalSubdevice,
NV2080_CTRL_CMD_FB_GET_CARVEOUT_REGION_INFO,
pParams,
sizeof(*pParams));
}
/*!
* Allocate console region in CPU-RM from UEFI carveout region.
*/
NV_STATUS
memmgrAllocateConsoleRegion_GB10B
(
OBJGPU *pGpu,
MemoryManager *pMemoryManager
)
{
NvU32 i;
NV_STATUS status;
NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO_PARAMS infoParams;
portMemSet(&infoParams, 0, sizeof(infoParams));
status = memmgrGetCarveoutRegionInfo(pGpu, pMemoryManager, &infoParams);
if (status != NV_OK)
{
return status;
}
// Once the console is reserved, we don't expect to reserve it again
NV_ASSERT_OR_RETURN(pMemoryManager->pReservedConsoleMemDesc == NULL,
NV_ERR_STATE_IN_USE);
for (i = 0; i < infoParams.numCarveoutRegions; i++)
{
const NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO *pRegion =
&infoParams.carveoutRegion[i];
if (pRegion->carveoutType ==
NV2080_CTRL_FB_GET_CARVEOUT_REGION_CARVEOUT_TYPE_UEFI)
{
status = memdescCreate(&pMemoryManager->pReservedConsoleMemDesc,
pGpu,
pRegion->size,
RM_PAGE_SIZE_64K,
NV_TRUE,
ADDR_SYSMEM,
NV_MEMORY_UNCACHED,
MEMDESC_FLAGS_SKIP_RESOURCE_COMPUTE |
MEMDESC_FLAGS_ALLOC_FROM_UEFI_CARVEOUT);
if (status != NV_OK)
{
return status;
}
memdescDescribe(pMemoryManager->pReservedConsoleMemDesc,
ADDR_SYSMEM,
pRegion->base,
pRegion->size);
memdescSetPageSize(pMemoryManager->pReservedConsoleMemDesc,
AT_CPU,
RM_PAGE_SIZE);
NV_PRINTF(LEVEL_INFO, "Allocating console region of size: %llx, at base : %llx \n ",
pRegion->size, pRegion->base);
break;
}
}
return NV_OK;
}
src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm107.c
+51
View File
@@ -2055,3 +2055,54 @@ memmgrPreInitReservedMemory_GM107
return status;
}
/*!
* Allocate console region in CPU-RM based on region table passed from Physical RM
*/
NV_STATUS
memmgrAllocateConsoleRegion_GM107
(
OBJGPU *pGpu,
MemoryManager *pMemoryManager
)
{
NV_STATUS status = NV_OK;
NvU32 consoleRegionId = 0x0;
NvU64 regionSize, base, limit;
if (pMemoryManager->Ram.ReservedConsoleDispMemSize > 0)
{
pMemoryManager->Ram.fbRegion[consoleRegionId].bLostOnSuspend = NV_FALSE;
pMemoryManager->Ram.fbRegion[consoleRegionId].bPreserveOnSuspend = NV_TRUE;
base = pMemoryManager->Ram.fbRegion[consoleRegionId].base;
limit = pMemoryManager->Ram.fbRegion[consoleRegionId].limit;
regionSize = limit - base + 1;
// Once the console is reserved, we don't expect to reserve it again
NV_ASSERT_OR_RETURN(pMemoryManager->pReservedConsoleMemDesc == NULL,
NV_ERR_STATE_IN_USE);
status = memdescCreate(&pMemoryManager->pReservedConsoleMemDesc, pGpu,
regionSize, RM_PAGE_SIZE_64K, NV_TRUE, ADDR_FBMEM,
NV_MEMORY_UNCACHED,
MEMDESC_FLAGS_SKIP_RESOURCE_COMPUTE);
if (status != NV_OK)
{
return status;
}
memdescDescribe(pMemoryManager->pReservedConsoleMemDesc, ADDR_FBMEM,
base, regionSize);
memdescSetPageSize(pMemoryManager->pReservedConsoleMemDesc,
AT_GPU, RM_PAGE_SIZE);
NV_PRINTF(LEVEL_INFO, "Allocating console region of size: %llx, at base : %llx \n ",
regionSize, base);
}
return status;
}
src/nvidia/src/kernel/gpu/mem_mgr/heap.c
-27
View File
@@ -532,26 +532,6 @@ NV_STATUS heapInitInternal_IMPL
//
if ((pMemoryManager->Ram.numFBRegions > 0) && (pHeap->bHasFbRegions))
{
FB_REGION_DESCRIPTOR consoleFbRegion;
portMemSet(&consoleFbRegion, 0, sizeof(consoleFbRegion));
if (heapType != HEAP_TYPE_PARTITION_LOCAL)
{
//
// If a region of FB is actively being used for console display memory
// on this GPU, mark it reserved in-place.
// In case of legacy SLI on Linux, console size is only known at StateInit
//
memmgrReserveConsoleRegion_HAL(pGpu, pMemoryManager, &consoleFbRegion);
status = memmgrAllocateConsoleRegion_HAL(pGpu, pMemoryManager, &consoleFbRegion);
if (status != NV_OK)
{
NV_PRINTF(LEVEL_WARNING, "Squashing the error status after failing to allocate console region, status: %x\n",
status);
status = NV_OK;
}
}
//
// Define PMA-managed regions
// This will be moved to memmgr once we refactor SMC partitions
@@ -739,13 +719,6 @@ heapDestruct_IMPL
} while (headptr_updated);
//
// Now that the console region is no longer reserved, free the console
// memdesc.
//
if (pHeap->heapType != HEAP_TYPE_PARTITION_LOCAL)
memmgrReleaseConsoleRegion(pGpu, pMemoryManager);
//
// Free the heap structure, if we freed everything
// (the first block represents the entire free space of the heap).
src/nvidia/src/kernel/gpu/mem_mgr/mem_desc.c
+10 -1
View File
@@ -4339,7 +4339,11 @@ memdescSetCustomHeap
MEMDESC_CUSTOM_HEAP heap
)
{
NV_ASSERT(0);
if (heap == MEMDESC_CUSTOM_HEAP_ACR)
pMemDesc->_flags |= MEMDESC_FLAGS_CUSTOM_HEAP_ACR;
if (heap == MEMDESC_CUSTOM_HEAP_SCANOUT_CARVEOUT)
pMemDesc->_flags |= MEMDESC_FLAGS_ALLOC_FROM_SCANOUT_CARVEOUT;
}
/*!
@@ -4356,6 +4360,11 @@ memdescGetCustomHeap
PMEMORY_DESCRIPTOR pMemDesc
)
{
if (!!(pMemDesc->_flags & MEMDESC_FLAGS_CUSTOM_HEAP_ACR))
return MEMDESC_CUSTOM_HEAP_ACR;
if (!!(pMemDesc->_flags & MEMDESC_FLAGS_ALLOC_FROM_SCANOUT_CARVEOUT))
return MEMDESC_CUSTOM_HEAP_SCANOUT_CARVEOUT;
return MEMDESC_CUSTOM_HEAP_NONE;
}
src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c
+29 -56
View File
@@ -113,6 +113,10 @@ memmgrDestruct_IMPL
{
NvU32 i;
OBJGPU *pGpu = ENG_GET_GPU(pMemoryManager);
memmgrDestroyScanoutCarveoutHeap_HAL(pGpu, pMemoryManager);
for (i = 0; i < NUM_FBSR_TYPES; i++)
{
objDelete(pMemoryManager->pFbsr[i]);
@@ -648,6 +652,16 @@ memmgrStateInitLocked_IMPL
memmgrPreSchedulingDisableHandler, NULL));
}
//
// If a region of FB or system memory is actively being used for console
// display memory on this GPU, mark it reserved in-place.
// In case of legacy SLI on Linux, console size is only known at StateInit
//
memmgrReserveConsoleRegion_HAL(pGpu, pMemoryManager);
NV_ASSERT_OK_OR_RETURN(memmgrAllocateConsoleRegion_HAL(pGpu, pMemoryManager));
//
// Allocate framebuffer heap. All memory must be allocated from here to keep the world
// consistent (N.B. the heap size has been reduced by the amount of instance memory).
@@ -945,6 +959,8 @@ memmgrStateDestroy_IMPL
pMemoryManager->pHeap = NULL;
}
memmgrReleaseConsoleRegion(pGpu, pMemoryManager);
// RMCONFIG: only if FBSR engine is enabled
if (RMCFG_MODULE_FBSR)
{
@@ -1987,59 +2003,6 @@ memmgrSetPlatformPmaSupport_IMPL
return (NV_OK);
}
/*!
* Allocate console region in CPU-RM based on region table passed from Physical RM
*/
NV_STATUS
memmgrAllocateConsoleRegion_IMPL
(
OBJGPU *pGpu,
MemoryManager *pMemoryManager,
FB_REGION_DESCRIPTOR *pConsoleFbRegion
)
{
NV_STATUS status = NV_OK;
NvU32 consoleRegionId = 0x0;
NvU64 regionSize;
if (pMemoryManager->Ram.ReservedConsoleDispMemSize > 0)
{
pMemoryManager->Ram.fbRegion[consoleRegionId].bLostOnSuspend = NV_FALSE;
pMemoryManager->Ram.fbRegion[consoleRegionId].bPreserveOnSuspend = NV_TRUE;
pConsoleFbRegion->base = pMemoryManager->Ram.fbRegion[consoleRegionId].base;
pConsoleFbRegion->limit = pMemoryManager->Ram.fbRegion[consoleRegionId].limit;
regionSize = pConsoleFbRegion->limit - pConsoleFbRegion->base + 1;
// Once the console is reserved, we don't expect to reserve it again
NV_ASSERT_OR_RETURN(pMemoryManager->Ram.pReservedConsoleMemDesc == NULL,
NV_ERR_STATE_IN_USE);
status = memdescCreate(&pMemoryManager->Ram.pReservedConsoleMemDesc, pGpu,
regionSize, RM_PAGE_SIZE_64K, NV_TRUE, ADDR_FBMEM,
NV_MEMORY_UNCACHED,
MEMDESC_FLAGS_SKIP_RESOURCE_COMPUTE);
if (status != NV_OK)
{
pConsoleFbRegion->base = pConsoleFbRegion->limit = 0;
return status;
}
memdescDescribe(pMemoryManager->Ram.pReservedConsoleMemDesc, ADDR_FBMEM,
pConsoleFbRegion->base, regionSize);
memdescSetPageSize(pMemoryManager->Ram.pReservedConsoleMemDesc,
AT_GPU, RM_PAGE_SIZE);
NV_PRINTF(LEVEL_INFO, "Allocating console region of size: %llx, at base : %llx \n ",
regionSize, pConsoleFbRegion->base);
}
return status;
}
void
memmgrReleaseConsoleRegion_IMPL
(
@@ -2047,8 +2010,8 @@ memmgrReleaseConsoleRegion_IMPL
MemoryManager *pMemoryManager
)
{
memdescDestroy(pMemoryManager->Ram.pReservedConsoleMemDesc);
pMemoryManager->Ram.pReservedConsoleMemDesc = NULL;
memdescDestroy(pMemoryManager->pReservedConsoleMemDesc);
pMemoryManager->pReservedConsoleMemDesc = NULL;
}
PMEMORY_DESCRIPTOR
@@ -2058,7 +2021,7 @@ memmgrGetReservedConsoleMemDesc_IMPL
MemoryManager *pMemoryManager
)
{
return pMemoryManager->Ram.pReservedConsoleMemDesc;
return pMemoryManager->pReservedConsoleMemDesc;
}
/*!
@@ -3426,6 +3389,16 @@ memmgrInitFbRegions_IMPL
}
//
// The carveout needs support from firmware side which is not
// configured in all the platforms.
//
if (memmgrInitZeroFbRegionsHal_HAL(pGpu, pMemoryManager) != NV_OK)
{
NV_PRINTF(LEVEL_INFO,
"Failed to setup carveout. Carevout functionality is disabled\n");
}
return NV_OK;
}
src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_ctrl.c
-22
View File
@@ -768,25 +768,3 @@ subdeviceCtrlCmdGbGetSemaphoreSurfaceLayout_IMPL
return NV_OK;
}
//
// subdeviceCtrlCmdFbGetCarveoutRegionInfo
//
// Lock Requirements:
// Assert that API and GPUs lock held on entry
//
NV_STATUS
subdeviceCtrlCmdFbGetCarveoutRegionInfo_IMPL
(
Subdevice *pSubdevice,
NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO_PARAMS *pParams
)
{
OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice);
MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu);
NV_ASSERT_OR_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner(), NV_ERR_INVALID_LOCK_STATE);
pParams->numCarveoutRegions = 0;
return memmgrGetCarveoutRegionInfo(pGpu, pMemoryManager, pParams);
}
src/nvidia/src/kernel/gpu/mem_mgr/mem_utils.c
+12
View File
@@ -1694,6 +1694,18 @@ memUtilsAllocMemDesc
{
NvU64 memDescFlags = MEMDESC_FLAGS_SKIP_RESOURCE_COMPUTE;
if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_SOC_SDM))
{
if (FLD_TEST_DRF(OS32, _ATTR2, _USE_SCANOUT_CARVEOUT, _TRUE, pFbAllocInfo->retAttr2))
{
memDescFlags |= MEMDESC_FLAGS_ALLOC_FROM_SCANOUT_CARVEOUT;
}
if (pGpu->getProperty(pGpu, PDB_PROP_GPU_ALLOC_ISO_SYS_MEM_FROM_CARVEOUT) &&
FLD_TEST_DRF(OS32, _ATTR2, _ISO, _YES, pFbAllocInfo->retAttr2))
{
memDescFlags |= MEMDESC_FLAGS_ALLOC_FROM_SCANOUT_CARVEOUT;
}
}
if (FLD_TEST_DRF(OS32, _ATTR2, _USE_EGM, _TRUE, pFbAllocInfo->retAttr2))
{
memDescFlags |= MEMDESC_FLAGS_ALLOC_FROM_EGM;
src/nvidia/src/kernel/gpu/mig_mgr/kernel_mig_manager.c
+2 -2
View File
@@ -1089,7 +1089,7 @@ static NV_STATUS _kmigmgrHandlePreSchedulingDisableCallback
swizzId = pKernelMIGGpuInstance->swizzId;
// Shouldn't be any valid gpu instances
NV_PRINTF(LEVEL_ERROR,
NV_PRINTF(LEVEL_INFO,
"Invalidating valid gpu instance with swizzId = %d\n",
swizzId);
@@ -1105,7 +1105,7 @@ static NV_STATUS _kmigmgrHandlePreSchedulingDisableCallback
continue;
// Shouldn't be any valid compute instances
NV_PRINTF(LEVEL_ERROR,
NV_PRINTF(LEVEL_INFO,
"Invalidating valid compute instance with id = %d\n",
CIIdx);
src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c
+44 -1
View File
@@ -39,6 +39,7 @@
#include "gpu/bif/kernel_bif.h"
#include "gpu/bus/kern_bus.h"
#include "gpu/gsp/gsp_static_config.h"
#include "gpu/gsp/kernel_gsp.h"
#include "gpu/disp/kern_disp.h"
#include "disp/nvfbc_session.h"
#include "gpu/mmu/kern_gmmu.h"
@@ -613,6 +614,30 @@ subdeviceCtrlCmdGpuGetCachedInfo_IMPL
return getGpuInfos(pSubdevice, pGpuInfoParams, NV_FALSE);
}
NV_STATUS
subdeviceCtrlCmdGpuForceGspUnload_IMPL
(
Subdevice *pSubdevice,
NV2080_CTRL_GPU_FORCE_GSP_UNLOAD_PARAMS *pGpuInfoParams
)
{
NV_STATUS rmStatus = NV_OK;
OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice);
KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu);
NV_CHECK_OR_RETURN(LEVEL_INFO, !IS_MIG_IN_USE(pGpu), NV_ERR_NOT_SUPPORTED);
NV_CHECK_OR_RETURN(LEVEL_INFO, IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu), NV_ERR_NOT_SUPPORTED);
// Call gsp unload now.
rmStatus = kgspUnloadRm(pGpu, pKernelGsp, KGSP_UNLOAD_MODE_NORMAL, GPU_STATE_FLAGS_FAST_UNLOAD);
pKernelGsp->bFatalError = NV_TRUE;
return rmStatus;;
}
static OBJHWBC *
getBridgeObject(OBJHWBC *pHWBC, NvU32 hwbcId)
{
@@ -3439,6 +3464,18 @@ subdeviceCtrlCmdGetGpuFabricProbeInfo_IMPL
healthMask |= FLD_SET_DRF(2080, _CTRL_GPU_FABRIC_HEALTH_MASK,
_INCORRECT_CONFIGURATION, _INSUFFICIENT_NVLINKS, healthMask);
}
else if (FLD_TEST_DRF(LINK, _INBAND_FABRIC_HEALTH_MASK, _INCORRECT_CONFIGURATION,
_INCOMPATIBLE_GPU_FW, mask))
{
healthMask |= FLD_SET_DRF(2080, _CTRL_GPU_FABRIC_HEALTH_MASK,
_INCORRECT_CONFIGURATION, _INCOMPATIBLE_GPU_FW, healthMask);
}
else if (FLD_TEST_DRF(LINK, _INBAND_FABRIC_HEALTH_MASK, _INCORRECT_CONFIGURATION,
_INVALID_LOCATION, mask))
{
healthMask |= FLD_SET_DRF(2080, _CTRL_GPU_FABRIC_HEALTH_MASK,
_INCORRECT_CONFIGURATION, _INVALID_LOCATION, healthMask);
}
else if (FLD_TEST_DRF(LINK, _INBAND_FABRIC_HEALTH_MASK, _INCORRECT_CONFIGURATION,
_NOT_SUPPORTED, mask))
{
@@ -3467,23 +3504,29 @@ subdeviceCtrlCmdGetGpuFabricProbeInfo_IMPL
{
healthMask |= FLD_SET_DRF(2080, _CTRL_GPU_FABRIC_HEALTH_MASK, _ACCESS_TIMEOUT_RECOVERY,
_TRUE, healthMask);
mask |= FLD_SET_DRF(LINK, _INBAND_FABRIC_HEALTH_MASK,
_ACCESS_TIMEOUT_RECOVERY, _TRUE, mask);
}
else
{
healthMask |= FLD_SET_DRF(2080, _CTRL_GPU_FABRIC_HEALTH_MASK, _ACCESS_TIMEOUT_RECOVERY,
_FALSE, healthMask);
mask |= FLD_SET_DRF(LINK, _INBAND_FABRIC_HEALTH_MASK,
_ACCESS_TIMEOUT_RECOVERY, _FALSE, mask);
}
}
else
{
healthMask |= FLD_SET_DRF(2080, _CTRL_GPU_FABRIC_HEALTH_MASK, _ACCESS_TIMEOUT_RECOVERY,
_NOT_SUPPORTED, healthMask);
mask |= FLD_SET_DRF(LINK, _INBAND_FABRIC_HEALTH_MASK,
_ACCESS_TIMEOUT_RECOVERY, _NOT_SUPPORTED, mask);
}
pParams->fabricHealthMask = healthMask;
pParams->fabricHealthSummary =
_convertGpuFabricProbeHealthSummary(nvlinkGetFabricHealthSummary(healthMask));
_convertGpuFabricProbeHealthSummary(nvlinkGetFabricHealthSummary(mask));
return NV_OK;
}
src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c
+3
View File
@@ -4254,6 +4254,9 @@ gpumgrUnregisterRmCapsForMIGGI_IMPL(NvU64 gpuDomainBusDevice)
pGPUInstanceSave->bValid = NV_FALSE;
}
}
// Reset during teardown as static info not restored since boot
pTopologySave->bVgpuRestoredFromStaticInfo = NV_FALSE;
}
void
src/nvidia/src/kernel/mem_mgr/console_mem.c
+17 -3
View File
@@ -31,6 +31,7 @@
#include "gpu/bus/kern_bus.h"
#include "class/cl0040.h" // NV01_MEMORY_LOCAL_USER
#include "class/cl003e.h" // NV01_MEMORY_SYSTEM
NV_STATUS
conmemConstruct_IMPL
@@ -45,6 +46,7 @@ conmemConstruct_IMPL
OBJGPU *pGpu = pMemory->pGpu;
MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu);
MEMORY_DESCRIPTOR *pMemDesc = memmgrGetReservedConsoleMemDesc(pGpu, pMemoryManager);
NvU32 memClassId;
NV_ASSERT_OR_RETURN(RMCFG_FEATURE_KERNEL_RM, NV_ERR_NOT_SUPPORTED);
@@ -57,16 +59,28 @@ conmemConstruct_IMPL
return NV_ERR_INVALID_ARGUMENT;
}
switch (pMemDesc->_addressSpace)
{
case ADDR_SYSMEM:
memClassId = NV01_MEMORY_SYSTEM;
break;
case ADDR_FBMEM:
memClassId = NV01_MEMORY_LOCAL_USER;
break;
default:
return NV_ERR_NOT_SUPPORTED;
}
NV_ASSERT(pMemDesc->Allocated == 0);
memdescAddRef(pMemDesc);
pMemDesc->DupCount++;
//
// NV01_MEMORY_FRAMEBUFFER_CONSOLE is just a way to get at the reserved
// framebuffer console memDesc rather than allocating a new one. Otherwise,
// it's treated as normal memory.
// video memory or system memory console memDesc rather than allocating
// a new one. Otherwise, it's treated as normal memory.
//
status = memConstructCommon(pMemory, NV01_MEMORY_LOCAL_USER, 0, pMemDesc,
status = memConstructCommon(pMemory, memClassId, 0, pMemDesc,
0, NULL, 0, 0, 0, 0, NVOS32_MEM_TAG_NONE,
(HWRESOURCE_INFO *)NULL);
if (status != NV_OK)
src/nvidia/src/kernel/mem_mgr/system_mem.c
+45 -1
View File
@@ -175,6 +175,16 @@ sysmemConstruct_IMPL
// Copy-construction has already been done by the base Memory class
if (RS_IS_COPY_CTOR(pParams))
{
Memory *pMemorySrc = dynamicCast(pParams->pSrcRef->pResource, Memory);
MEMORY_DESCRIPTOR *pMemDesc = pMemorySrc->pMemDesc;
NV_STATUS status = NV_ERR_INVALID_ARGUMENT;
if (memdescGetCustomHeap(pMemDesc) == MEMDESC_CUSTOM_HEAP_SCANOUT_CARVEOUT) {
status = memmgrDuplicateFromScanoutCarveoutRegion(pGpu,
GPU_GET_MEMORY_MANAGER(pGpu),
pMemDesc);
return status;
}
return NV_OK;
}
@@ -305,6 +315,21 @@ sysmemConstruct_IMPL
AT_GPU, pageSizeAttr),
failed_destroy_memdesc);
if (memdescGetFlag(pMemDesc, MEMDESC_FLAGS_ALLOC_FROM_SCANOUT_CARVEOUT))
{
NvU32 heapFlag = NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_DOWN;
rmStatus = memmgrAllocScanoutCarveoutRegionResources(GPU_GET_MEMORY_MANAGER(pGpu),
pAllocData,
pAllocRequest->hClient,
&heapFlag,
pMemDesc);
NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_ERROR, rmStatus, failed_destroy_memdesc);
sizeOut = pMemDesc->Size;
pAllocData->limit = sizeOut - 1;
}
memdescTagAlloc(rmStatus, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_132, pMemDesc);
if (rmStatus != NV_OK)
{
@@ -324,7 +349,7 @@ sysmemConstruct_IMPL
}
else
{
NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_ERROR, rmStatus, failed_destroy_memdesc);
NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_ERROR, rmStatus, failed_free_scanout_carveout);
}
}
else
@@ -484,6 +509,11 @@ failed_destruct_common:
memDestructCommon(pMemory);
failed_free_memdesc:
memdescFree(pMemDesc);
failed_free_scanout_carveout:
if (memdescGetFlag(pMemDesc, MEMDESC_FLAGS_ALLOC_FROM_SCANOUT_CARVEOUT)) {
memmgrFreeScanoutCarveoutRegionResources(GPU_GET_MEMORY_MANAGER(pGpu),
memdescGetPte(pMemDesc, AT_CPU, 0));
}
failed_destroy_memdesc:
memdescDestroy(pMemDesc);
@@ -792,3 +822,17 @@ failed:
return status;
}
void sysmemDestruct_IMPL(SystemMemory *pSystemMemory)
{
Memory *pMemory = staticCast(pSystemMemory, Memory);
OBJGPU *pGpu = pMemory->pGpu;
MEMORY_DESCRIPTOR *pMemDesc = pMemory->pMemDesc;
if ((pMemDesc != NULL) &&
memdescGetFlag(pMemDesc, MEMDESC_FLAGS_ALLOC_FROM_SCANOUT_CARVEOUT))
{
memmgrFreeScanoutCarveoutRegionResources(GPU_GET_MEMORY_MANAGER(pGpu),
memdescGetPte(pMemDesc, AT_CPU, 0));
}
}
src/nvidia/src/kernel/mem_mgr/video_mem.c
+47
View File
@@ -486,6 +486,10 @@ vidmemCopyConstruct
switch (memdescGetCustomHeap(pMemDesc))
{
case MEMDESC_CUSTOM_HEAP_SCANOUT_CARVEOUT:
status = memmgrDuplicateFromScanoutCarveoutRegion(pGpu,
GPU_GET_MEMORY_MANAGER(pGpu), pMemDesc);
break;
case MEMDESC_CUSTOM_HEAP_NONE:
SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY)
MEMORY_DESCRIPTOR *pSrcMemDesc = memdescGetMemDescFromGpu(pMemorySrc->pMemDesc, pGpu);
@@ -650,6 +654,7 @@ vidmemConstruct_IMPL
bIsPmaAlloc = memmgrIsPmaInitialized(pMemoryManager) &&
!bSubheap &&
!bRsvdHeap &&
!FLD_TEST_DRF(OS32, _ATTR2, _USE_SCANOUT_CARVEOUT, _TRUE, attr2) &&
!(pAllocData->flags & NVOS32_ALLOC_FLAGS_WPR1) &&
!(pAllocData->flags & NVOS32_ALLOC_FLAGS_WPR2) &&
(!(pAllocData->flags & NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE) ||
@@ -718,6 +723,7 @@ vidmemConstruct_IMPL
// Don't allow FB allocations if FB is broken unless it is a virtual allocation or running in L2 cache only mode
if (pGpu->getProperty(pGpu, PDB_PROP_GPU_BROKEN_FB) &&
!FLD_TEST_DRF(OS32, _ATTR2, _USE_SCANOUT_CARVEOUT, _TRUE, pAllocData->attr2) &&
!gpuIsCacheOnlyModeEnabled(pGpu))
{
NV_ASSERT_FAILED("Video memory requested despite BROKEN FB");
@@ -874,6 +880,7 @@ vidmemConstruct_IMPL
SLI_LOOP_END;
}
if (!memdescGetFlag(pTempMemDesc, MEMDESC_FLAGS_ALLOC_FROM_SCANOUT_CARVEOUT))
{
//
// Video memory is always locally transparently cached. It does not require
@@ -1193,6 +1200,11 @@ vidmemDestruct_IMPL
}
}
else if (customHeap == MEMDESC_CUSTOM_HEAP_SCANOUT_CARVEOUT)
{
MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu);
memmgrFreeFromScanoutCarveoutRegion(pGpu, pMemoryManager, pMemDesc);
}
}
NV_STATUS
@@ -1270,6 +1282,39 @@ vidmemAllocResources
goto failed;
}
if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_SOC_SDM))
{
if (FLD_TEST_DRF(OS32, _ATTR2, _USE_SCANOUT_CARVEOUT, _TRUE, pVidHeapAlloc->attr2))
{
NvU32 heapFlag = NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_DOWN;
status = memmgrAllocFromScanoutCarveoutRegion(pGpu,
pMemoryManager,
pFbAllocInfo->hClient,
pVidHeapAlloc,
&heapFlag,
&pAllocRequest->pMemDesc);
if (status == NV_OK)
{
pMemDesc = pAllocRequest->pMemDesc;
pMemDesc->pHeap = (Heap *)pMemoryManager->pScanoutHeap;
memdescSetCustomHeap(pMemDesc, MEMDESC_CUSTOM_HEAP_SCANOUT_CARVEOUT);
// Force the format to whatever is required by client.
memdescSetPteKind(pMemDesc, pFbAllocInfo->format);
NV_PRINTF(LEVEL_INFO, "Allocated surface in scanout region\n");
}
else
{
NV_PRINTF(LEVEL_WARNING,
"Failed to allocate surface in scanout region\n");
goto failed;
}
goto pre_alloc_done;
}
}
// Prior to this change, heap was silently ignoring non-contig Vidmem allocation requests.
// With this change to allow non-contig vidmem allocation, I was getting a DVS Extended Sanity failures & regression on Windows.
// It seems Windows is making some allocations with non-contig flag, but was expecting contig allocation.
@@ -1448,6 +1493,8 @@ vidmemAllocResources
pHwResource->ctagOffset = pFbAllocInfo->ctagOffset;
}
pre_alloc_done:
pVidHeapAlloc->offset = pFbAllocInfo->offset;
if (pAllocRequest->pHwResource != NULL)
src/nvidia/src/kernel/vgpu/rpc.c
+4
View File
@@ -1497,6 +1497,9 @@ NV_STATUS vgpuGspSetupBuffers(OBJGPU *pGpu)
return NV_ERR_NOT_SUPPORTED;
}
// Modifying the DMA address size to the value supported by the hardware
osDmaSetAddressSize(pGpu->pOsGpuInfo, gpuarchGetSystemPhysAddrWidth_HAL(gpuGetArch(pGpu)));
rpcSendMessage_FNPTR(pVGpu->pRpc) = _rpcSendMessage_VGPUGSP;
rpcRecvPoll_FNPTR(pVGpu->pRpc) = _rpcRecvPoll_VGPUGSP;
@@ -10597,6 +10600,7 @@ NV_STATUS rpcGspSetSystemInfo_v17_00
rpcInfo->bIsPrimary = pGpu->getProperty(pGpu, PDB_PROP_GPU_PRIMARY_DEVICE);
rpcInfo->bS0ixSupport = pSys->getProperty(pSys, PDB_PROP_SYS_SUPPORTS_S0IX);
#if defined(NV_UNIX) && !RMCFG_FEATURE_MODS_FEATURES
rpcInfo->isGridBuild = os_is_grid_supported();
#endif
src/nvidia/srcs.mk
+1
View File
@@ -608,6 +608,7 @@ SRCS += src/kernel/gpu/mem_mgr/arch/ampere/fbsr_ga100.c
SRCS += src/kernel/gpu/mem_mgr/arch/ampere/mem_mgr_ga100.c
SRCS += src/kernel/gpu/mem_mgr/arch/ampere/mem_mgr_ga102.c
SRCS += src/kernel/gpu/mem_mgr/arch/blackwell/mem_mgr_gb100.c
SRCS += src/kernel/gpu/mem_mgr/arch/blackwell/mem_mgr_gb10b_phys.c
SRCS += src/kernel/gpu/mem_mgr/arch/blackwell/mem_mgr_gb202.c
SRCS += src/kernel/gpu/mem_mgr/arch/blackwell/mem_mgr_gb202_base.c
SRCS += src/kernel/gpu/mem_mgr/arch/blackwell/mem_mgr_gb20b.c
version.mk
+2 -2
View File
@@ -1,5 +1,5 @@
NVIDIA_VERSION = 580.65.06
NVIDIA_NVID_VERSION = 580.65.06
NVIDIA_VERSION = 580.76.05
NVIDIA_NVID_VERSION = 580.76.05
NVIDIA_NVID_EXTRA =
# This file.