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580.95.05

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This commit is contained in:
Maneet Singh
2025-09-30 12:52:14 -07:00
parent 87c0b12473
commit 2b436058a6
147 changed files with 56986 additions and 55176 deletions
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README.md
+827 -819
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File diff suppressed because it is too large Load Diff
kernel-open/Kbuild
+1 -1
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@@ -79,7 +79,7 @@ ccflags-y += -I$(src)/common/inc
ccflags-y += -I$(src)
ccflags-y += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-format-extra-args
ccflags-y += -D__KERNEL__ -DMODULE -DNVRM
ccflags-y += -DNV_VERSION_STRING=\"580.82.09\"
ccflags-y += -DNV_VERSION_STRING=\"580.95.05\"
# Include and link Tegra out-of-tree modules.
ifneq ($(wildcard /usr/src/nvidia/nvidia-oot),)
kernel-open/common/inc/nv-gpu-info.h
+2
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@@ -32,6 +32,8 @@ typedef struct {
NvU8 bus, slot, function;
} pci_info;
NvBool needs_numa_setup;
/*
* opaque OS-specific pointer; on Linux, this is a pointer to the
* 'struct device' for the GPU.
kernel-open/common/inc/nv-linux.h
+2 -2
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@@ -1711,12 +1711,12 @@ static inline void nv_mutex_destroy(struct mutex *lock)
mutex_destroy(lock);
}
static inline NvBool nv_platform_supports_numa(nv_linux_state_t *nvl)
static inline NvBool nv_platform_supports_numa(const nv_linux_state_t *nvl)
{
return nvl->numa_info.node_id != NUMA_NO_NODE;
}
static inline int nv_get_numa_status(nv_linux_state_t *nvl)
static inline int nv_get_numa_status(const nv_linux_state_t *nvl)
{
if (!nv_platform_supports_numa(nvl))
{
kernel-open/common/inc/nv.h
+2 -2
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@@ -588,8 +588,8 @@ typedef struct nv_state_t
/* Console is managed by drm drivers or NVKMS */
NvBool client_managed_console;
/* Bool to check if power management is supported */
NvBool is_pm_supported;
/* Bool to check if power management is unsupported */
NvBool is_pm_unsupported;
} nv_state_t;
#define NVFP_TYPE_NONE 0x0
kernel-open/common/inc/nv_uvm_types.h
+3
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@@ -685,6 +685,9 @@ typedef struct UvmGpuInfo_tag
// GPU supports Non-PASID ATS capability
NvBool nonPasidAtsSupport;
// GPU setup in CDMM mode
NvBool cdmmEnabled;
} UvmGpuInfo;
typedef struct UvmGpuFbInfo_tag
kernel-open/common/inc/nvkms-api-types.h
+3 -1
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@@ -667,7 +667,9 @@ enum NvKmsInputTf {
enum NvKmsOutputColorimetry {
NVKMS_OUTPUT_COLORIMETRY_DEFAULT = 0,
NVKMS_OUTPUT_COLORIMETRY_BT2100 = 1,
NVKMS_OUTPUT_COLORIMETRY_BT601 = 1,
NVKMS_OUTPUT_COLORIMETRY_BT709 = 2,
NVKMS_OUTPUT_COLORIMETRY_BT2100 = 3,
};
enum NvKmsOutputTf {
kernel-open/conftest.sh
+16
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@@ -4856,6 +4856,22 @@ compile_test() {
compile_check_conftest "$CODE" "NV_DRM_CONNECTOR_HELPER_FUNCS_MODE_VALID_HAS_CONST_MODE_ARG" "" "types"
;;
memory_device_coherent_present)
#
# Determine if MEMORY_DEVICE_COHERENT support is present or not
#
# Added by commit f25cbb7a95a2 ("mm: add zone device coherent type
# memory support") in v6.0.
#
CODE="
#include <linux/mm.h>
int memory_device_coherent = MEMORY_DEVICE_COHERENT;
"
compile_check_conftest "$CODE" "NV_MEMORY_DEVICE_COHERENT_PRESENT" "" "types"
;;
# When adding a new conftest entry, please use the correct format for
# specifying the relevant upstream Linux kernel commit. Please
# avoid specifying -rc kernels, and only use SHAs that actually exist
kernel-open/nvidia-drm/nvidia-drm-connector.c
+8
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@@ -445,6 +445,14 @@ __nv_drm_connector_atomic_check(struct drm_connector *connector,
req_config->modeSetConfig.colorimetry =
NVKMS_OUTPUT_COLORIMETRY_DEFAULT;
break;
case DRM_MODE_COLORIMETRY_BT601_YCC:
req_config->modeSetConfig.colorimetry =
NVKMS_OUTPUT_COLORIMETRY_BT601;
break;
case DRM_MODE_COLORIMETRY_BT709_YCC:
req_config->modeSetConfig.colorimetry =
NVKMS_OUTPUT_COLORIMETRY_BT709;
break;
case DRM_MODE_COLORIMETRY_BT2020_RGB:
case DRM_MODE_COLORIMETRY_BT2020_YCC:
// Ignore RGB/YCC
kernel-open/nvidia-drm/nvidia-drm-drv.c
+11 -2
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@@ -691,7 +691,16 @@ static int nv_drm_dev_load(struct drm_device *dev)
pDevice = nvKms->allocateDevice(&allocateDeviceParams);
if (pDevice == NULL) {
NV_DRM_DEV_LOG_ERR(nv_dev, "Failed to allocate NvKmsKapiDevice");
if (nv_dev->gpu_info.needs_numa_setup) {
/*
* RM init from a kernel-mode driver may fail on GPUs that require
* NUMA setup. Just notify about that specifically rather than
* producing a scary-looking error.
*/
NV_DRM_DEV_LOG_INFO(nv_dev, "NUMA was not set up yet; ignoring this device");
} else {
NV_DRM_DEV_LOG_ERR(nv_dev, "Failed to allocate NvKmsKapiDevice");
}
return -ENODEV;
}
@@ -787,6 +796,7 @@ static int nv_drm_dev_load(struct drm_device *dev)
}
#endif
nvKms->freeDevice(nv_dev->pDevice);
NV_DRM_DEV_LOG_ERR(nv_dev, "Failed to create DRM properties");
return -ENODEV;
}
@@ -1994,7 +2004,6 @@ void nv_drm_register_drm_device(const struct NvKmsKapiGpuInfo *gpu_info)
/* Load DRM device before registering it */
if (nv_drm_dev_load(dev) != 0) {
NV_DRM_DEV_LOG_ERR(nv_dev, "Failed to load device");
goto failed_drm_load;
}
kernel-open/nvidia-modeset/nvidia-modeset-linux.c
+9
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@@ -114,6 +114,10 @@ MODULE_PARM_DESC(fail_alloc_core_channel, "Control testing for hardware core cha
static int fail_alloc_core_channel_method = -1;
module_param_named(fail_alloc_core_channel, fail_alloc_core_channel_method, int, 0400);
MODULE_PARM_DESC(debug, "Enable debug logging");
static int debug = 0;
module_param_named(debug, debug, int, 0600);
#if NVKMS_CONFIG_FILE_SUPPORTED
/* This parameter is used to find the dpy override conf file */
#define NVKMS_CONF_FILE_SPECIFIED (nvkms_conf != NULL)
@@ -190,6 +194,11 @@ NvBool nvkms_enable_overlay_layers(void)
return enable_overlay_layers;
}
NvBool nvkms_debug_logging(void)
{
return debug != 0;
}
NvBool nvkms_kernel_supports_syncpts(void)
{
/*
kernel-open/nvidia-modeset/nvidia-modeset-os-interface.h
+1
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@@ -119,6 +119,7 @@ NvBool nvkms_vblank_sem_control(void);
NvBool nvkms_opportunistic_display_sync(void);
enum NvKmsDebugForceColorSpace nvkms_debug_force_color_space(void);
NvBool nvkms_enable_overlay_layers(void);
NvBool nvkms_debug_logging(void);
void nvkms_call_rm (void *ops);
void* nvkms_alloc (size_t size,
kernel-open/nvidia-uvm/nvidia-uvm.Kbuild
+1
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@@ -67,6 +67,7 @@ NV_CONFTEST_TYPE_COMPILE_TESTS += mpol_preferred_many_present
NV_CONFTEST_TYPE_COMPILE_TESTS += mmu_interval_notifier
NV_CONFTEST_TYPE_COMPILE_TESTS += sg_dma_page_iter
NV_CONFTEST_TYPE_COMPILE_TESTS += struct_page_has_zone_device_data
NV_CONFTEST_TYPE_COMPILE_TESTS += memory_device_coherent_present
NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_int_active_memcg
NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_migrate_vma_setup
kernel-open/nvidia-uvm/uvm_ats_faults.c
+1 -1
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@@ -143,7 +143,7 @@ static void ats_batch_select_residency(uvm_gpu_va_space_t *gpu_va_space,
{
uvm_gpu_t *gpu = gpu_va_space->gpu;
int residency;
bool cdmm_enabled = gpu->mem_info.cdmm_enabled;
bool cdmm_enabled = gpu->parent->cdmm_enabled;
if (gpu->parent->is_integrated_gpu || cdmm_enabled) {
residency = gpu->parent->closest_cpu_numa_node;
kernel-open/nvidia-uvm/uvm_gpu.c
+16 -15
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@@ -150,13 +150,8 @@ static NV_STATUS get_gpu_caps(uvm_gpu_t *gpu)
gpu->mem_info.numa.enabled = true;
gpu->mem_info.numa.node_id = gpu_caps.numaNodeId;
gpu->mem_info.cdmm_enabled = false;
}
else {
// TODO: Bug 5273146: Use RM control call to detect CDMM mode.
if (uvm_parent_gpu_is_coherent(gpu->parent))
gpu->mem_info.cdmm_enabled = true;
gpu->mem_info.numa.node_id = NUMA_NO_NODE;
}
@@ -248,16 +243,15 @@ static NV_STATUS alloc_and_init_address_space(uvm_gpu_t *gpu)
return NV_OK;
}
int uvm_device_p2p_static_bar(uvm_gpu_t *gpu)
int uvm_device_p2p_static_bar(uvm_parent_gpu_t *parent_gpu)
{
return nv_bar_index_to_os_bar_index(gpu->parent->pci_dev, NV_GPU_BAR_INDEX_FB);
return nv_bar_index_to_os_bar_index(parent_gpu->pci_dev, NV_GPU_BAR_INDEX_FB);
}
static NV_STATUS get_gpu_fb_info(uvm_gpu_t *gpu)
{
NV_STATUS status;
UvmGpuFbInfo fb_info = {0};
unsigned long pci_bar1_addr = pci_resource_start(gpu->parent->pci_dev, uvm_device_p2p_static_bar(gpu));
status = uvm_rm_locked_call(nvUvmInterfaceGetFbInfo(uvm_gpu_device_handle(gpu), &fb_info));
if (status != NV_OK)
@@ -270,9 +264,6 @@ static NV_STATUS get_gpu_fb_info(uvm_gpu_t *gpu)
}
gpu->mem_info.max_vidmem_page_size = fb_info.maxVidmemPageSize;
gpu->mem_info.static_bar1_start = pci_bar1_addr + fb_info.staticBar1StartOffset;
gpu->mem_info.static_bar1_size = fb_info.staticBar1Size;
gpu->mem_info.static_bar1_write_combined = fb_info.bStaticBar1WriteCombined;
return NV_OK;
}
@@ -1443,8 +1434,16 @@ static NV_STATUS init_parent_gpu(uvm_parent_gpu_t *parent_gpu,
if (status != NV_OK)
return status;
if (!fb_info.bZeroFb)
if (!fb_info.bZeroFb) {
unsigned long pci_bar1_addr = pci_resource_start(parent_gpu->pci_dev, uvm_device_p2p_static_bar(parent_gpu));
parent_gpu->max_allocatable_address = fb_info.maxAllocatableAddress;
parent_gpu->static_bar1_start = pci_bar1_addr + fb_info.staticBar1StartOffset;
parent_gpu->static_bar1_size = fb_info.staticBar1Size;
parent_gpu->static_bar1_write_combined = fb_info.bStaticBar1WriteCombined;
}
parent_gpu->cdmm_enabled = gpu_info->cdmmEnabled;
parent_gpu->virt_mode = gpu_info->virtMode;
if (parent_gpu->virt_mode == UVM_VIRT_MODE_LEGACY) {
@@ -1493,6 +1492,8 @@ static NV_STATUS init_parent_gpu(uvm_parent_gpu_t *parent_gpu,
return status;
}
uvm_pmm_gpu_device_p2p_init(parent_gpu);
status = uvm_ats_add_gpu(parent_gpu);
if (status != NV_OK) {
UVM_ERR_PRINT("uvm_ats_add_gpu failed: %s, GPU %s\n",
@@ -1597,7 +1598,7 @@ static NV_STATUS init_gpu(uvm_gpu_t *gpu, const UvmGpuInfo *gpu_info)
return status;
}
uvm_pmm_gpu_device_p2p_init(gpu);
uvm_mutex_init(&gpu->device_p2p_lock, UVM_LOCK_ORDER_GLOBAL);
status = init_semaphore_pools(gpu);
if (status != NV_OK) {
@@ -1731,6 +1732,8 @@ static void deinit_parent_gpu(uvm_parent_gpu_t *parent_gpu)
// Return ownership to RM
uvm_parent_gpu_deinit_isr(parent_gpu);
uvm_pmm_gpu_device_p2p_deinit(parent_gpu);
uvm_pmm_devmem_deinit(parent_gpu);
uvm_ats_remove_gpu(parent_gpu);
@@ -1786,8 +1789,6 @@ static void deinit_gpu(uvm_gpu_t *gpu)
deinit_semaphore_pools(gpu);
uvm_pmm_gpu_device_p2p_deinit(gpu);
uvm_pmm_gpu_deinit(&gpu->pmm);
if (gpu->rm_address_space != 0)
kernel-open/nvidia-uvm/uvm_gpu.h
+20 -20
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@@ -711,21 +711,6 @@ struct uvm_gpu_struct
int node_id;
} numa;
// Coherent Driver-based Memory Management (CDMM) is a mode that allows
// coherent GPU memory to be managed by the driver and not the OS. This
// is done by the driver not onlining the memory as NUMA nodes. Having
// the field provides the most flexibility and is sync with the numa
// properties above. CDMM as a property applies to the entire system.
bool cdmm_enabled;
// Physical address of the start of statically mapped fb memory in BAR1
NvU64 static_bar1_start;
// Size of statically mapped fb memory in BAR1.
NvU64 static_bar1_size;
// Whether or not RM has iomapped the region write combined.
NvBool static_bar1_write_combined;
} mem_info;
struct
@@ -941,9 +926,6 @@ struct uvm_gpu_struct
// Force pushbuffer's GPU VA to be >= 1TB; used only for testing purposes.
bool uvm_test_force_upper_pushbuffer_segment;
// Have we initialised device p2p pages.
bool device_p2p_initialised;
// Used to protect allocation of p2p_mem and assignment of the page
// zone_device_data fields.
uvm_mutex_t device_p2p_lock;
@@ -1014,10 +996,28 @@ struct uvm_parent_gpu_struct
// Total amount of physical memory available on the parent GPU.
NvU64 max_allocatable_address;
#if UVM_IS_CONFIG_HMM()
#if UVM_IS_CONFIG_HMM() || defined(NV_MEMORY_DEVICE_COHERENT_PRESENT)
uvm_pmm_gpu_devmem_t *devmem;
#endif
// Physical address of the start of statically mapped fb memory in BAR1
NvU64 static_bar1_start;
// Size of statically mapped fb memory in BAR1.
NvU64 static_bar1_size;
// Whether or not RM has iomapped the region write combined.
NvBool static_bar1_write_combined;
// Have we initialised device p2p pages.
bool device_p2p_initialised;
// Coherent Driver-based Memory Management (CDMM) is a mode that allows
// coherent GPU memory to be managed by the driver and not the OS. This
// is done by the driver not onlining the memory as NUMA nodes. CDMM as a
// property applies to the entire system.
bool cdmm_enabled;
// The physical address range addressable by the GPU
//
// The GPU has its NV_PFB_XV_UPPER_ADDR register set by RM to
@@ -1867,6 +1867,6 @@ typedef enum
} uvm_gpu_buffer_flush_mode_t;
// PCIe BAR containing static framebuffer memory mappings for PCIe P2P
int uvm_device_p2p_static_bar(uvm_gpu_t *gpu);
int uvm_device_p2p_static_bar(uvm_parent_gpu_t *gpu);
#endif // __UVM_GPU_H__
kernel-open/nvidia-uvm/uvm_gpu_access_counters.c
+1 -1
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@@ -1576,7 +1576,7 @@ static NV_STATUS service_notifications_batch(uvm_gpu_va_space_t *gpu_va_space,
}
}
else if (uvm_ats_can_service_faults(gpu_va_space, mm)) {
if (!gpu_va_space->gpu->mem_info.cdmm_enabled) {
if (!gpu_va_space->gpu->parent->cdmm_enabled) {
status = service_notification_ats(gpu_va_space, mm, access_counters, index, out_index);
}
else {
kernel-open/nvidia-uvm/uvm_linux.h
+6
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@@ -85,6 +85,12 @@
#define UVM_THREAD_AFFINITY_SUPPORTED() 1
#if defined(CONFIG_ZONE_DEVICE) && defined(NV_MEMORY_DEVICE_COHERENT_PRESENT)
#define UVM_CDMM_PAGES_SUPPORTED() 1
#else
#define UVM_CDMM_PAGES_SUPPORTED() 0
#endif
#if defined(CONFIG_HMM_MIRROR) && defined(CONFIG_DEVICE_PRIVATE) && defined(NV_MIGRATE_DEVICE_RANGE_PRESENT)
#define UVM_IS_CONFIG_HMM() 1
#else
kernel-open/nvidia-uvm/uvm_migrate.c
+1 -1
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@@ -1020,7 +1020,7 @@ NV_STATUS uvm_api_migrate(UVM_MIGRATE_PARAMS *params, struct file *filp)
.fail_on_unresolved_sto_errors = false,
};
if (dest_gpu && dest_gpu->mem_info.cdmm_enabled) {
if (dest_gpu && dest_gpu->parent->cdmm_enabled) {
uvm_migrate_args.dst_id = UVM_ID_CPU;
uvm_migrate_args.dst_node_id = dest_gpu->parent->closest_cpu_numa_node;
uvm_migrate_args.populate_on_cpu_alloc_failures = true;
kernel-open/nvidia-uvm/uvm_mmu.c
+2 -2
View File
@@ -295,7 +295,7 @@ static void *uvm_mmu_page_table_cpu_map(uvm_gpu_t *gpu, uvm_mmu_page_table_alloc
{
// CDMM implies there are no struct pages corresponding to the
// GPU memory physical address.
if (gpu->mem_info.cdmm_enabled) {
if (gpu->parent->cdmm_enabled) {
NvU64 addr = uvm_gpu_chunk_to_sys_addr(&gpu->pmm, phys_alloc->handle.chunk);
// Using cached access for coherent systems, there should be no conflicts
// for the vidmem region
@@ -312,7 +312,7 @@ static void *uvm_mmu_page_table_cpu_map(uvm_gpu_t *gpu, uvm_mmu_page_table_alloc
static void uvm_mmu_page_table_cpu_unmap(uvm_gpu_t *gpu, uvm_mmu_page_table_alloc_t *phys_alloc, void *ptr)
{
if (gpu->mem_info.cdmm_enabled)
if (gpu->parent->cdmm_enabled)
nv_iounmap(ptr, PAGE_SIZE);
else
kunmap(uvm_mmu_page_table_page(gpu, phys_alloc));
kernel-open/nvidia-uvm/uvm_pmm_gpu.c
+146 -63
View File
@@ -3246,11 +3246,117 @@ err:
return NULL;
}
unsigned long uvm_pmm_gpu_devmem_get_pfn(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk)
{
uvm_gpu_t *gpu = uvm_pmm_to_gpu(pmm);
unsigned long devmem_start = gpu->parent->devmem->pagemap.range.start;
return (devmem_start + chunk->address) >> PAGE_SHIFT;
}
#else // UVM_IS_CONFIG_HMM()
static void *devmem_alloc_pagemap(unsigned long size) { return NULL; }
static void *devmem_reuse_pagemap(unsigned long size) { return NULL; }
#endif // UVM_IS_CONFIG_HMM()
#if (UVM_CDMM_PAGES_SUPPORTED() || defined(CONFIG_PCI_P2PDMA)) && defined(NV_STRUCT_PAGE_HAS_ZONE_DEVICE_DATA)
static void device_p2p_page_free_wake(struct nv_kref *ref)
{
uvm_device_p2p_mem_t *p2p_mem = container_of(ref, uvm_device_p2p_mem_t, refcount);
wake_up(&p2p_mem->waitq);
}
static void device_p2p_page_free(struct page *page)
{
uvm_device_p2p_mem_t *p2p_mem = page->zone_device_data;
page->zone_device_data = NULL;
nv_kref_put(&p2p_mem->refcount, device_p2p_page_free_wake);
}
#endif
#if UVM_CDMM_PAGES_SUPPORTED()
static void device_coherent_page_free(struct page *page)
{
device_p2p_page_free(page);
}
static const struct dev_pagemap_ops uvm_device_coherent_pgmap_ops =
{
.page_free = device_coherent_page_free,
};
static NV_STATUS uvm_pmm_cdmm_init(uvm_parent_gpu_t *parent_gpu)
{
uvm_pmm_gpu_devmem_t *devmem;
void *ptr;
NV_STATUS status;
UVM_ASSERT(!uvm_hmm_is_enabled_system_wide());
list_for_each_entry(devmem, &g_uvm_global.devmem_ranges.list, list_node) {
if (devmem->pagemap.range.start == parent_gpu->system_bus.memory_window_start) {
UVM_ASSERT(devmem->pagemap.type == MEMORY_DEVICE_COHERENT);
UVM_ASSERT(devmem->pagemap.range.end ==
SUBSECTION_ALIGN_UP(parent_gpu->system_bus.memory_window_end >> PAGE_SHIFT) << PAGE_SHIFT);
list_del(&devmem->list_node);
parent_gpu->devmem = devmem;
parent_gpu->device_p2p_initialised = true;
return NV_OK;
}
}
devmem = kzalloc(sizeof(*devmem), GFP_KERNEL);
if (!devmem)
goto err;
devmem->size = parent_gpu->system_bus.memory_window_end - parent_gpu->system_bus.memory_window_start;
devmem->pagemap.type = MEMORY_DEVICE_COHERENT;
devmem->pagemap.range.start = parent_gpu->system_bus.memory_window_start;
devmem->pagemap.range.end = SUBSECTION_ALIGN_UP(parent_gpu->system_bus.memory_window_end >> PAGE_SHIFT) << PAGE_SHIFT;
devmem->pagemap.nr_range = 1;
devmem->pagemap.ops = &uvm_device_coherent_pgmap_ops;
devmem->pagemap.owner = &g_uvm_global;
// Numa node ID doesn't matter for ZONE_DEVICE coherent pages.
ptr = memremap_pages(&devmem->pagemap, NUMA_NO_NODE);
if (IS_ERR(ptr)) {
UVM_ERR_PRINT("memremap_pages() err %ld\n", PTR_ERR(ptr));
status = errno_to_nv_status(PTR_ERR(ptr));
goto err_free;
}
parent_gpu->devmem = devmem;
parent_gpu->device_p2p_initialised = true;
return NV_OK;
err_free:
kfree(devmem);
err:
return NV_ERR_NOT_SUPPORTED;
}
static void uvm_pmm_cdmm_deinit(uvm_parent_gpu_t *parent_gpu)
{
parent_gpu->device_p2p_initialised = false;
list_add_tail(&parent_gpu->devmem->list_node, &g_uvm_global.devmem_ranges.list);
parent_gpu->devmem = NULL;
}
#else // UVM_CDMM_PAGES_SUPPORTED
static NV_STATUS uvm_pmm_cdmm_init(uvm_parent_gpu_t *parent_gpu) { return NV_OK; }
static void uvm_pmm_cdmm_deinit(uvm_parent_gpu_t *parent_gpu) {}
#endif // UVM_CDMM_PAGES_SUPPORTED
#if UVM_IS_CONFIG_HMM() || UVM_CDMM_PAGES_SUPPORTED()
NV_STATUS uvm_pmm_devmem_init(uvm_parent_gpu_t *gpu)
{
// Create a DEVICE_PRIVATE page for every GPU page available on the parent.
unsigned long size = gpu->max_allocatable_address;
if (gpu->cdmm_enabled)
return uvm_pmm_cdmm_init(gpu);
if (!uvm_hmm_is_enabled_system_wide()) {
gpu->devmem = NULL;
return NV_OK;
@@ -3268,6 +3374,11 @@ NV_STATUS uvm_pmm_devmem_init(uvm_parent_gpu_t *gpu)
void uvm_pmm_devmem_deinit(uvm_parent_gpu_t *gpu)
{
if (gpu->cdmm_enabled && gpu->devmem) {
uvm_pmm_cdmm_deinit(gpu);
return;
}
if (!gpu->devmem)
return;
@@ -3282,31 +3393,18 @@ void uvm_pmm_devmem_exit(void)
list_for_each_entry_safe(devmem, devmem_next, &g_uvm_global.devmem_ranges.list, list_node) {
list_del(&devmem->list_node);
memunmap_pages(&devmem->pagemap);
release_mem_region(devmem->pagemap.range.start, range_len(&devmem->pagemap.range));
if (devmem->pagemap.type == MEMORY_DEVICE_PRIVATE)
release_mem_region(devmem->pagemap.range.start, range_len(&devmem->pagemap.range));
kfree(devmem);
}
}
unsigned long uvm_pmm_gpu_devmem_get_pfn(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk)
{
uvm_gpu_t *gpu = uvm_pmm_to_gpu(pmm);
unsigned long devmem_start = gpu->parent->devmem->pagemap.range.start;
return (devmem_start + chunk->address) >> PAGE_SHIFT;
}
#endif // UVM_IS_CONFIG_HMM()
#else
NV_STATUS uvm_pmm_devmem_init(uvm_parent_gpu_t *gpu) { return NV_OK; }
void uvm_pmm_devmem_deinit(uvm_parent_gpu_t *gpu) {}
void uvm_pmm_devmem_exit(void) {}
#endif
#if !UVM_IS_CONFIG_HMM()
NV_STATUS uvm_pmm_devmem_init(uvm_parent_gpu_t *gpu)
{
return NV_OK;
}
void uvm_pmm_devmem_deinit(uvm_parent_gpu_t *gpu)
{
}
static bool uvm_pmm_gpu_check_orphan_pages(uvm_pmm_gpu_t *pmm)
{
return true;
@@ -3318,41 +3416,32 @@ static bool uvm_pmm_gpu_check_orphan_pages(uvm_pmm_gpu_t *pmm)
// TODO: Bug 5303506: ARM64: P2PDMA pages cannot be accessed from the CPU on
// ARM
#if defined(CONFIG_PCI_P2PDMA) && defined(NV_STRUCT_PAGE_HAS_ZONE_DEVICE_DATA) && !defined(NVCPU_AARCH64)
static void device_p2p_page_free_wake(struct nv_kref *ref)
{
uvm_device_p2p_mem_t *p2p_mem = container_of(ref, uvm_device_p2p_mem_t, refcount);
wake_up(&p2p_mem->waitq);
}
static void device_p2p_page_free(struct page *page)
{
uvm_device_p2p_mem_t *p2p_mem = page->zone_device_data;
page->zone_device_data = NULL;
nv_kref_put(&p2p_mem->refcount, device_p2p_page_free_wake);
}
static const struct dev_pagemap_ops uvm_device_p2p_pgmap_ops =
{
.page_free = device_p2p_page_free,
};
void uvm_pmm_gpu_device_p2p_init(uvm_gpu_t *gpu)
void uvm_pmm_gpu_device_p2p_init(uvm_parent_gpu_t *parent_gpu)
{
unsigned long pci_start_pfn = pci_resource_start(gpu->parent->pci_dev,
uvm_device_p2p_static_bar(gpu)) >> PAGE_SHIFT;
unsigned long pci_end_pfn = pci_start_pfn + (gpu->mem_info.static_bar1_size >> PAGE_SHIFT);
unsigned long pci_start_pfn = pci_resource_start(parent_gpu->pci_dev,
uvm_device_p2p_static_bar(parent_gpu)) >> PAGE_SHIFT;
unsigned long pci_end_pfn = pci_start_pfn + (parent_gpu->static_bar1_size >> PAGE_SHIFT);
struct page *p2p_page;
gpu->device_p2p_initialised = false;
uvm_mutex_init(&gpu->device_p2p_lock, UVM_LOCK_ORDER_GLOBAL);
if (uvm_parent_gpu_is_coherent(parent_gpu)) {
// P2PDMA support with CDMM enabled requires special
// MEMORY_DEVICE_COHERENT pages to have been allocated which will have
// also set the p2p initialised state if successful.
if (parent_gpu->cdmm_enabled)
return;
if (uvm_parent_gpu_is_coherent(gpu->parent)) {
// A coherent system uses normal struct pages.
gpu->device_p2p_initialised = true;
parent_gpu->device_p2p_initialised = true;
return;
}
parent_gpu->device_p2p_initialised = false;
// RM sets static_bar1_size when it has created a contiguous BAR mapping
// large enough to cover all of GPU memory that will be allocated to
// userspace buffers. This is required to support the P2PDMA feature to
@@ -3364,10 +3453,10 @@ void uvm_pmm_gpu_device_p2p_init(uvm_gpu_t *gpu)
// can be disabled by setting the RmForceDisableIomapWC regkey which allows
// creation of the P2PDMA pages.
// TODO: Bug 5044562: P2PDMA pages require the PCIe BAR to be mapped UC
if (!gpu->mem_info.static_bar1_size || gpu->mem_info.static_bar1_write_combined)
if (!parent_gpu->static_bar1_size || parent_gpu->static_bar1_write_combined)
return;
if (pci_p2pdma_add_resource(gpu->parent->pci_dev, uvm_device_p2p_static_bar(gpu), 0, 0)) {
if (pci_p2pdma_add_resource(parent_gpu->pci_dev, uvm_device_p2p_static_bar(parent_gpu), 0, 0)) {
UVM_ERR_PRINT("Unable to initialse PCI P2PDMA pages\n");
return;
}
@@ -3383,46 +3472,40 @@ void uvm_pmm_gpu_device_p2p_init(uvm_gpu_t *gpu)
for (; page_to_pfn(p2p_page) < pci_end_pfn; p2p_page++)
p2p_page->zone_device_data = NULL;
gpu->device_p2p_initialised = true;
parent_gpu->device_p2p_initialised = true;
}
void uvm_pmm_gpu_device_p2p_deinit(uvm_gpu_t *gpu)
void uvm_pmm_gpu_device_p2p_deinit(uvm_parent_gpu_t *parent_gpu)
{
unsigned long pci_start_pfn = pci_resource_start(gpu->parent->pci_dev,
uvm_device_p2p_static_bar(gpu)) >> PAGE_SHIFT;
unsigned long pci_start_pfn = pci_resource_start(parent_gpu->pci_dev,
uvm_device_p2p_static_bar(parent_gpu)) >> PAGE_SHIFT;
struct page *p2p_page;
if (gpu->device_p2p_initialised && !uvm_parent_gpu_is_coherent(gpu->parent)) {
if (parent_gpu->device_p2p_initialised && !uvm_parent_gpu_is_coherent(parent_gpu)) {
p2p_page = pfn_to_page(pci_start_pfn);
devm_memunmap_pages(&gpu->parent->pci_dev->dev, page_pgmap(p2p_page));
devm_memunmap_pages(&parent_gpu->pci_dev->dev, page_pgmap(p2p_page));
}
gpu->device_p2p_initialised = false;
parent_gpu->device_p2p_initialised = false;
}
#else // CONFIG_PCI_P2PDMA
// Coherent platforms can do P2PDMA without CONFIG_PCI_P2PDMA
void uvm_pmm_gpu_device_p2p_init(uvm_gpu_t *gpu)
void uvm_pmm_gpu_device_p2p_init(uvm_parent_gpu_t *parent_gpu)
{
gpu->device_p2p_initialised = false;
uvm_mutex_init(&gpu->device_p2p_lock, UVM_LOCK_ORDER_GLOBAL);
if (uvm_parent_gpu_is_coherent(gpu->parent)) {
// CDMM implies that there are no struct pages corresponding to
// the GPU memory. P2PDMA struct pages which are required for
// device P2P mappings are not currently supported on ARM.
if (gpu->mem_info.cdmm_enabled)
if (uvm_parent_gpu_is_coherent(parent_gpu)) {
if (parent_gpu->cdmm_enabled)
return;
// A coherent system uses normal struct pages.
gpu->device_p2p_initialised = true;
parent_gpu->device_p2p_initialised = true;
return;
}
}
void uvm_pmm_gpu_device_p2p_deinit(uvm_gpu_t *gpu)
void uvm_pmm_gpu_device_p2p_deinit(uvm_parent_gpu_t *parent_gpu)
{
gpu->device_p2p_initialised = false;
parent_gpu->device_p2p_initialised = false;
}
#endif // CONFIG_PCI_P2PDMA
kernel-open/nvidia-uvm/uvm_pmm_gpu.h
+11 -15
View File
@@ -190,8 +190,7 @@ typedef uvm_chunk_size_t uvm_chunk_sizes_mask_t;
typedef struct uvm_pmm_gpu_chunk_suballoc_struct uvm_pmm_gpu_chunk_suballoc_t;
#if UVM_IS_CONFIG_HMM()
#if UVM_IS_CONFIG_HMM() || defined(NV_MEMORY_DEVICE_COHERENT_PRESENT)
typedef struct
{
// For g_uvm_global.devmem_ranges
@@ -205,7 +204,9 @@ typedef struct
struct dev_pagemap pagemap;
} uvm_pmm_gpu_devmem_t;
#endif
#if UVM_IS_CONFIG_HMM()
typedef struct uvm_pmm_gpu_struct uvm_pmm_gpu_t;
// Return the GPU chunk for a given device private struct page.
@@ -219,19 +220,18 @@ uvm_gpu_id_t uvm_pmm_devmem_page_to_gpu_id(struct page *page);
// Return the PFN of the device private struct page for the given GPU chunk.
unsigned long uvm_pmm_gpu_devmem_get_pfn(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk);
#endif
// Allocate and initialise struct page data in the kernel to support HMM.
NV_STATUS uvm_pmm_devmem_init(uvm_parent_gpu_t *gpu);
void uvm_pmm_devmem_deinit(uvm_parent_gpu_t *parent_gpu);
void uvm_pmm_gpu_device_p2p_init(uvm_parent_gpu_t *gpu);
void uvm_pmm_gpu_device_p2p_deinit(uvm_parent_gpu_t *gpu);
// Free unused ZONE_DEVICE pages.
void uvm_pmm_devmem_exit(void);
#else
static inline void uvm_pmm_devmem_exit(void)
{
}
#endif
void uvm_pmm_gpu_device_p2p_init(uvm_gpu_t *gpu);
void uvm_pmm_gpu_device_p2p_deinit(uvm_gpu_t *gpu);
struct uvm_gpu_chunk_struct
{
// Physical address of GPU chunk. This may be removed to save memory
@@ -627,10 +627,6 @@ static uvm_chunk_size_t uvm_chunk_find_prev_size(uvm_chunk_sizes_mask_t chunk_si
// retained, and it's up to the caller to release them.
NvU32 uvm_pmm_gpu_phys_to_virt(uvm_pmm_gpu_t *pmm, NvU64 phys_addr, NvU64 region_size, uvm_reverse_map_t *out_mappings);
// Allocate and initialise struct page data in the kernel to support HMM.
NV_STATUS uvm_pmm_devmem_init(uvm_parent_gpu_t *gpu);
void uvm_pmm_devmem_deinit(uvm_parent_gpu_t *parent_gpu);
// Iterates over every size in the input mask from smallest to largest
#define for_each_chunk_size(__size, __chunk_sizes) \
for ((__size) = (__chunk_sizes) ? uvm_chunk_find_first_size(__chunk_sizes) : \
kernel-open/nvidia-uvm/uvm_va_range_device_p2p.c
+41 -17
View File
@@ -47,6 +47,11 @@ void uvm_va_range_device_p2p_exit(void)
kmem_cache_destroy_safe(&g_uvm_va_range_device_p2p_cache);
}
static bool device_p2p_uses_zone_device(uvm_parent_gpu_t *gpu)
{
return !uvm_parent_gpu_is_coherent(gpu) || gpu->cdmm_enabled;
}
static NvU64 p2p_mem_page_count(uvm_device_p2p_mem_t *p2p_mem)
{
return (p2p_mem->pfn_count * p2p_mem->page_size) >> PAGE_SHIFT;
@@ -74,9 +79,11 @@ void uvm_va_range_free_device_p2p_mem(uvm_device_p2p_mem_t *p2p_mem)
NvU64 i;
uvm_gpu_t *gpu = p2p_mem->gpu;
// In the coherent case we don't hold references on the page because RM does
// via the duplicated handle.
if (!uvm_parent_gpu_is_coherent(gpu->parent)) {
// If normal, non-zone-device pages are used for providing device p2p
// functionality RM will already hold a reference on the page via the
// duplicated handle. Therefore UVM skipped taking a reference on the page
// so don't need to return one.
if (device_p2p_uses_zone_device(gpu->parent)) {
uvm_mutex_lock(&gpu->device_p2p_lock);
// It's possible that another range has been setup for the handle since
@@ -128,13 +135,13 @@ static void deinit_device_p2p_mem(uvm_device_p2p_mem_t *p2p_mem, struct list_hea
// scheduling work which may not happen holding the va_space lock. Coherent
// systems don't need to take the lock because the p2p_mem objects are not
// shared between multiple va_ranges.
if (!uvm_parent_gpu_is_coherent(p2p_mem->gpu->parent))
if (device_p2p_uses_zone_device(p2p_mem->gpu->parent))
uvm_mutex_lock_nested(&p2p_mem->gpu->device_p2p_lock);
p2p_mem->deferred_free_list = deferred_free_list;
nv_kref_put(&p2p_mem->va_range_count, put_device_p2p_mem);
if (!uvm_parent_gpu_is_coherent(p2p_mem->gpu->parent))
if (device_p2p_uses_zone_device(p2p_mem->gpu->parent))
uvm_mutex_unlock_nested(&p2p_mem->gpu->device_p2p_lock);
}
@@ -225,6 +232,8 @@ static NV_STATUS get_gpu_pfns(uvm_gpu_t *gpu,
// start address or system memory start address and right shifting by
// PAGE_SHIFT.
for (i = 0; i < ext_mapping_info.numWrittenPhysAddrs; i++)
// MEMORY_DEVICE_COHERENT pages are in the system memory window so are
// the same as normal struct pages for the purposes of calculating pfn.
if (uvm_parent_gpu_is_coherent(gpu->parent)) {
NvU64 last_pfn = gpu->parent->system_bus.memory_window_end >> PAGE_SHIFT;
@@ -234,9 +243,9 @@ static NV_STATUS get_gpu_pfns(uvm_gpu_t *gpu,
return NV_ERR_INVALID_ADDRESS;
}
else {
NvU64 last_pfn = ((gpu->mem_info.static_bar1_start + gpu->mem_info.static_bar1_size) >> PAGE_SHIFT) - 1;
NvU64 last_pfn = ((gpu->parent->static_bar1_start + gpu->parent->static_bar1_size) >> PAGE_SHIFT) - 1;
pfns[i] = (gpu->mem_info.static_bar1_start + pfns[i]) >> PAGE_SHIFT;
pfns[i] = (gpu->parent->static_bar1_start + pfns[i]) >> PAGE_SHIFT;
UVM_ASSERT(pfns[i] <= last_pfn);
if (pfns[i] > last_pfn)
return NV_ERR_INVALID_ADDRESS;
@@ -253,27 +262,26 @@ static bool pci_p2pdma_page_free(struct page *page) {
// page->zone_device_data does not exist in kernels versions older than v5.3
// which don't support CONFIG_PCI_P2PDMA. Therefore we need these accessor
// functions to ensure compilation succeeeds on older kernels.
static void pci_p2pdma_page_set_zone_device_data(struct page *page, void *zone_device_data)
static void page_set_zone_device_data(struct page *page, void *zone_device_data)
{
page->zone_device_data = zone_device_data;
}
static void *pci_p2pdma_page_get_zone_device_data(struct page *page)
static void *page_get_zone_device_data(struct page *page)
{
return page->zone_device_data;
}
#else
static bool pci_p2pdma_page_free(struct page *page) {
UVM_ASSERT(0);
return false;
}
static void pci_p2pdma_page_set_zone_device_data(struct page *page, void *zone_device_data)
static void page_set_zone_device_data(struct page *page, void *zone_device_data)
{
UVM_ASSERT(0);
}
static void *pci_p2pdma_page_get_zone_device_data(struct page *page)
static void *page_get_zone_device_data(struct page *page)
{
UVM_ASSERT(0);
return NULL;
@@ -335,7 +343,7 @@ static NV_STATUS alloc_device_p2p_mem(uvm_gpu_t *gpu,
for (i = 0; i < p2p_mem_page_count(p2p_mem); i++) {
struct page *page = p2p_mem_get_page(p2p_mem, i);
if (!pci_p2pdma_page_free(page)) {
if (!gpu->parent->cdmm_enabled && !pci_p2pdma_page_free(page)) {
UVM_ASSERT(0);
// This will leak the RM handle because we don't release it.
@@ -345,7 +353,23 @@ static NV_STATUS alloc_device_p2p_mem(uvm_gpu_t *gpu,
return NV_ERR_INVALID_ARGUMENT;
}
pci_p2pdma_page_set_zone_device_data(page, p2p_mem);
page_set_zone_device_data(page, p2p_mem);
#if UVM_CDMM_PAGES_SUPPORTED()
// RM doesn't use DEVICE_COHERENT pages and therefore won't already hold
// a reference to them, so take one now if using DEVICE_COHERENT pages.
if (gpu->parent->cdmm_enabled) {
get_page(page);
get_dev_pagemap(page_to_pfn(page), NULL);
}
#else
// CDMM P2PDMA will never be enabled for this case
if (gpu->parent->cdmm_enabled) {
UVM_ASSERT(0);
break;
}
#endif
nv_kref_get(&p2p_mem->refcount);
}
@@ -400,7 +424,7 @@ static NV_STATUS alloc_pci_device_p2p(uvm_gpu_t *gpu,
// also ensures if we don't find a p2p_mem object that we don't race with
// some other thread assigning or clearing zone_device_data.
uvm_mutex_lock(&gpu->device_p2p_lock);
p2p_mem = pci_p2pdma_page_get_zone_device_data(pfn_to_page(pfn));
p2p_mem = page_get_zone_device_data(pfn_to_page(pfn));
if (!p2p_mem) {
// We have not previously allocated p2pdma pages for this RM handle so do
// so now.
@@ -513,12 +537,12 @@ NV_STATUS uvm_api_alloc_device_p2p(UVM_ALLOC_DEVICE_P2P_PARAMS *params, struct f
if (!gpu)
return NV_ERR_INVALID_DEVICE;
if (!gpu->device_p2p_initialised) {
if (!gpu->parent->device_p2p_initialised) {
status = NV_ERR_NOT_SUPPORTED;
goto out_release;
}
if (uvm_parent_gpu_is_coherent(gpu->parent)) {
if (uvm_parent_gpu_is_coherent(gpu->parent) && !device_p2p_uses_zone_device(gpu->parent)) {
status = alloc_coherent_device_p2p(gpu, params->hClient, params->hMemory, &p2p_mem);
if (status != NV_OK)
goto out_release;
kernel-open/nvidia-uvm/uvm_va_space.c
+1 -1
View File
@@ -940,7 +940,7 @@ NV_STATUS uvm_va_space_register_gpu(uvm_va_space_t *va_space,
*numa_enabled = NV_TRUE;
*numa_node_id = (NvS32)uvm_gpu_numa_node(gpu);
}
else if (gpu->parent->is_integrated_gpu || gpu->mem_info.cdmm_enabled) {
else if (gpu->parent->is_integrated_gpu || gpu->parent->cdmm_enabled) {
*numa_enabled = NV_FALSE;
*numa_node_id = (NvS32)gpu->parent->closest_cpu_numa_node;
}
kernel-open/nvidia/nv-modeset-interface.c
+5
View File
@@ -83,6 +83,7 @@ static NvU32 nvidia_modeset_enumerate_gpus(nv_gpu_info_t *gpu_info)
for (nvl = nv_linux_devices; nvl != NULL; nvl = nvl->next)
{
nv_state_t *nv = NV_STATE_PTR(nvl);
int numa_status = nv_get_numa_status(nvl);
/*
* The gpu_info[] array has NV_MAX_GPUS elements. Fail if there
@@ -102,6 +103,10 @@ static NvU32 nvidia_modeset_enumerate_gpus(nv_gpu_info_t *gpu_info)
gpu_info[count].pci_info.slot = nv->pci_info.slot;
gpu_info[count].pci_info.function = nv->pci_info.function;
gpu_info->needs_numa_setup =
numa_status != NV_IOCTL_NUMA_STATUS_DISABLED &&
numa_status != NV_IOCTL_NUMA_STATUS_ONLINE;
gpu_info[count].os_device_ptr = nvl->dev;
count++;
kernel-open/nvidia/nv.c
+24 -6
View File
@@ -2458,6 +2458,12 @@ nvidia_ioctl(
{
nv_ioctl_wait_open_complete_t *params = arg_copy;
if (arg_size != sizeof(nv_ioctl_wait_open_complete_t))
{
status = -EINVAL;
goto done_early;
}
params->rc = nvlfp->open_rc;
params->adapterStatus = nvlfp->adapter_status;
goto done_early;
@@ -2538,8 +2544,12 @@ nvidia_ioctl(
goto done;
}
/* atomically check and alloc attached_gpus */
down(&nvl->ldata_lock);
if (nvlfp->num_attached_gpus != 0)
{
up(&nvl->ldata_lock);
status = -EINVAL;
goto done;
}
@@ -2547,12 +2557,15 @@ nvidia_ioctl(
NV_KMALLOC(nvlfp->attached_gpus, arg_size);
if (nvlfp->attached_gpus == NULL)
{
up(&nvl->ldata_lock);
status = -ENOMEM;
goto done;
}
memcpy(nvlfp->attached_gpus, arg_copy, arg_size);
nvlfp->num_attached_gpus = num_arg_gpus;
up(&nvl->ldata_lock);
for (i = 0; i < nvlfp->num_attached_gpus; i++)
{
if (nvlfp->attached_gpus[i] == 0)
@@ -2568,9 +2581,14 @@ nvidia_ioctl(
nvidia_dev_put(nvlfp->attached_gpus[i], sp);
}
/* atomically free attached_gpus */
down(&nvl->ldata_lock);
NV_KFREE(nvlfp->attached_gpus, arg_size);
nvlfp->num_attached_gpus = 0;
up(&nvl->ldata_lock);
status = -EINVAL;
break;
}
@@ -4504,18 +4522,18 @@ nvidia_suspend(
down(&nvl->ldata_lock);
if (!nv->is_pm_supported)
{
status = NV_ERR_NOT_SUPPORTED;
goto done;
}
if (((nv->flags & NV_FLAG_OPEN) == 0) &&
((nv->flags & NV_FLAG_PERSISTENT_SW_STATE) == 0))
{
goto done;
}
if (nv->is_pm_unsupported)
{
status = NV_ERR_NOT_SUPPORTED;
goto done;
}
if ((nv->flags & NV_FLAG_SUSPENDED) != 0)
{
nvl->suspend_count++;
src/common/displayport/inc/dp_connectorimpl.h
+8
View File
@@ -259,6 +259,12 @@ namespace DisplayPort
// Flag to check if the system is UEFI.
bool bIsUefiSystem;
//
// Flag to ensure we take into account that
// Displayport++ supports HDMI as well.
//
bool bHDMIOnDPPlusPlus;
bool bSkipResetLinkStateDuringPlug;
// Flag to check if LT should be skipped.
@@ -342,6 +348,8 @@ namespace DisplayPort
//
NvU32 LT2FecLatencyMs;
bool bIgnoreCapsAndForceHighestLc;
// On eDP, do not cache the source OUI if it reads 0. See bug 4793112
bool bSkipZeroOuiCache;
src/common/displayport/inc/dp_hostimp.h
+5 -1
View File
@@ -39,7 +39,11 @@ extern "C" void dpFree(void * ptr);
extern "C" void dpDebugBreakpoint();
// Note: dpPrint() implementations are expected to append a newline themselves.
extern "C" void dpPrint(const char * formatter, ...);
extern "C" void dpPrintf(DP_LOG_LEVEL severity, const char * formatter, ...);
extern "C" void dpPrintf(DP_LOG_LEVEL severity, const char * formatter, ...)
#if defined(__GNUC__)
__attribute__ ((format (printf, 2, 3)))
#endif
;
extern "C" void dpTraceEvent(NV_DP_TRACING_EVENT event,
NV_DP_TRACING_PRIORITY priority, NvU32 numArgs, ...);
src/common/displayport/inc/dp_linkconfig.h
+2
View File
@@ -42,6 +42,8 @@ extern NvU32 bSupportInternalUhbrOnFpga;
namespace DisplayPort
{
typedef NvU64 LinkRate;
#define LinkRate_fmtx NvU64_fmtx
#define LinkRate_fmtu NvU64_fmtu
class LinkRates : virtual public Object
{
src/common/displayport/inc/dp_printf.h
-4
View File
@@ -43,10 +43,6 @@ typedef enum
DP_FATAL,
} DP_LOG_LEVEL;
#if defined(_DEBUG) || defined(DEBUG)
#define DP_PRINTF(severity, format, ...) dpPrintf(severity, format, ##__VA_ARGS__)
#else
#define DP_PRINTF(severity, format, ...)
#endif // _DEBUG || DEBUG
#endif // INCLUDED_DP_PRINTF_H
src/common/displayport/inc/dp_regkeydatabase.h
+7
View File
@@ -103,6 +103,11 @@
// This regkey forces devID to be exposed to vendors via DPCD 0x309 for DSC-enabled SKUs.
#define NV_DP_REGKEY_EXPOSE_DSC_DEVID_WAR "DP_DSC_DEVID_WAR"
// This regkey ensures DPLib takes into account Displayport++ supports HDMI.
#define NV_DP_REGKEY_HDMI_ON_DP_PLUS_PLUS "HDMI_ON_DP_PLUS_PLUS"
#define NV_DP_REGKEY_IGNORE_CAPS_AND_FORCE_HIGHEST_LC "DP_IGNORE_CAPS_AND_FORCE_HIGHEST_LC_WAR"
//
// Data Base used to store all the regkey values.
// The actual data base is declared statically in dp_evoadapter.cpp.
@@ -146,6 +151,8 @@ struct DP_REGKEY_DATABASE
bool bEnable5147205Fix;
bool bForceHeadShutdown;
bool bEnableDevId;
bool bHDMIOnDPPlusPlus;
bool bIgnoreCapsAndForceHighestLc;
};
extern struct DP_REGKEY_DATABASE dpRegkeyDatabase;
src/common/displayport/src/dp_configcaps2x.cpp
+1 -1
View File
@@ -616,7 +616,7 @@ void DPCDHALImpl2x::overrideCableIdCap(LinkRate linkRate, bool bEnable)
caps2x.rxCableCaps .bUHBR_10GSupported = bEnable;
break;
default:
DP_PRINTF(DP_ERROR, "DPHAL> Invalid link rate (%d) to override.", linkRate);
DP_PRINTF(DP_ERROR, "DPHAL> Invalid link rate (%" LinkRate_fmtu ") to override.", linkRate);
}
}
src/common/displayport/src/dp_connectorimpl.cpp
+38 -21
View File
@@ -196,7 +196,9 @@ void ConnectorImpl::applyRegkeyOverrides(const DP_REGKEY_DATABASE& dpRegkeyDatab
this->bSkipZeroOuiCache = dpRegkeyDatabase.bSkipZeroOuiCache;
this->bForceHeadShutdownFromRegkey = dpRegkeyDatabase.bForceHeadShutdown;
this->bEnableDevId = dpRegkeyDatabase.bEnableDevId;
this->bIgnoreCapsAndForceHighestLc = dpRegkeyDatabase.bIgnoreCapsAndForceHighestLc;
this->bDisableEffBppSST8b10b = dpRegkeyDatabase.bDisableEffBppSST8b10b;
this->bHDMIOnDPPlusPlus = dpRegkeyDatabase.bHDMIOnDPPlusPlus;
}
void ConnectorImpl::setPolicyModesetOrderMitigation(bool enabled)
@@ -410,7 +412,16 @@ void ConnectorImpl::processNewDevice(const DiscoveryManager::Device & device,
{
case DISPLAY_PORT:
case DISPLAY_PORT_PLUSPLUS: // DP port that supports DP and TMDS
connector = connectorDisplayPort;
if (bHDMIOnDPPlusPlus &&
existingDev &&
existingDev->connectorType == connectorHDMI)
{
connector = connectorHDMI;
}
else
{
connector = connectorDisplayPort;
}
break;
case ANALOG_VGA:
@@ -2531,11 +2542,11 @@ void ConnectorImpl::fireEventsInternal()
if (dev->complianceDeviceEdidReadTest)
{
// the zombie event will be hidden for DD/OS
DP_PRINTF(DP_WARNING, "DPCONN> Compliance: Device Internal Zombie? : %d 0x%x", dev->shadow.zombie ? 1 : 0, dev);
DP_PRINTF(DP_WARNING, "DPCONN> Compliance: Device Internal Zombie? : %d %p", dev->shadow.zombie ? 1 : 0, dev);
return;
}
bMitigateZombie = false;
DP_PRINTF(DP_WARNING, "DPCONN> Zombie? : %d 0x%x", dev->shadow.zombie ? 1 : 0, dev);
DP_PRINTF(DP_WARNING, "DPCONN> Zombie? : %d %p", dev->shadow.zombie ? 1 : 0, dev);
sink->notifyZombieStateChange(dev, dev->shadow.zombie);
}
@@ -2600,7 +2611,7 @@ void ConnectorImpl::fireEventsInternal()
{
// If yes, then we need to report this lost device first.
_device->shadow.plugged = false;
DP_PRINTF(DP_WARNING, "DPCONN> Lost device 0x%x", _device);
DP_PRINTF(DP_WARNING, "DPCONN> Lost device %p", _device);
sink->lostDevice(_device);
DP_ASSERT(!_device->activeGroup && "DD didn't remove panel from group");
delete _device;
@@ -3253,7 +3264,7 @@ bool ConnectorImpl::notifyAttachBegin(Group * target, // Gr
}
}
DP_PRINTF(DP_NOTICE, "DPCONN> Notify Attach Begin (Head %d, pclk %d raster %d x %d %d bpp)",
DP_PRINTF(DP_NOTICE, "DPCONN> Notify Attach Begin (Head %d, pclk %" NvU64_fmtu " raster %d x %d %d bpp)",
modesetParams.headIndex, pixelClockHz, rasterWidth, rasterHeight, depth);
NV_DPTRACE_INFO(NOTIFY_ATTACH_BEGIN, modesetParams.headIndex, pixelClockHz, rasterWidth, rasterHeight,
depth, bEnableDsc, bEnableFEC);
@@ -4202,7 +4213,7 @@ bool ConnectorImpl::allocateDpTunnelBw(NvU64 bandwidth)
return false;
}
DP_PRINTF(DP_INFO, "Estimated BW: %d Mbps, Requested BW: %d Mbps",
DP_PRINTF(DP_INFO, "Estimated BW: %" NvU64_fmtu " Mbps, Requested BW: %" NvU64_fmtu " Mbps",
((NvU64) estimatedBw * 1000) / (NvU64) granularityMultiplier,
bandwidth / (1000 * 1000));
@@ -4242,7 +4253,7 @@ bool ConnectorImpl::allocateDpTunnelBw(NvU64 bandwidth)
return false;
}
DP_PRINTF(DP_INFO, "Failed to get requested BW, requesting updated Estimated BW: %d\n",
DP_PRINTF(DP_INFO, "Failed to get requested BW, requesting updated Estimated BW: %" NvU64_fmtu "\n",
((NvU64) estimatedBw * 1000) / (NvU64) granularityMultiplier);
requestBw = estimatedBw;
@@ -4262,7 +4273,7 @@ bool ConnectorImpl::allocateDpTunnelBw(NvU64 bandwidth)
// Convert this back to bps and record the allocated BW
this->allocatedDpTunnelBw = ((NvU64) requestBw * 1000 * 1000 * 1000) / (NvU64) granularityMultiplier;
this->allocatedDpTunnelBwShadow = 0;
DP_PRINTF(DP_INFO, "Allocated BW: %d Mbps", this->allocatedDpTunnelBw / (1000 * 1000));
DP_PRINTF(DP_INFO, "Allocated BW: %" NvU64_fmtu " Mbps", this->allocatedDpTunnelBw / (1000 * 1000));
}
return requestStatus;
@@ -4278,7 +4289,7 @@ bool ConnectorImpl::allocateMaxDpTunnelBw()
NvU64 bandwidth = getMaxTunnelBw();
if (!allocateDpTunnelBw(bandwidth))
{
DP_PRINTF(DP_ERROR, "Failed to allocate DP Tunnel BW. Requested BW: %d Mbps",
DP_PRINTF(DP_ERROR, "Failed to allocate DP Tunnel BW. Requested BW: %" NvU64_fmtu " Mbps",
bandwidth / (1000 * 1000));
return false;
}
@@ -4553,7 +4564,7 @@ void ConnectorImpl::assessLink(LinkTrainingType trainType)
else
{
DP_PRINTF(DP_WARNING,
"DP> assessLink(): Failed to reach max link configuration (%d x %d).",
"DP> assessLink(): Failed to reach max link configuration (%d x %" LinkRate_fmtu ").",
lConfig.lanes, lConfig.peakRate);
}
}
@@ -5627,13 +5638,13 @@ bool ConnectorImpl::validateLinkConfiguration(const LinkConfiguration & lConfig)
{
if (!IS_VALID_LINKBW_10M(linkRate10M))
{
DP_PRINTF(DP_ERROR, "DPCONN> Requested link rate=%d is not valid", linkRate10M);
DP_PRINTF(DP_ERROR, "DPCONN> Requested link rate=%" NvU64_fmtu " is not valid", linkRate10M);
return false;
}
if (linkRate10M > hal->getMaxLinkRate())
{
DP_PRINTF(DP_ERROR, "DPCONN> Requested link rate=%d is larger than sinkMaxLinkRate=%d",
DP_PRINTF(DP_ERROR, "DPCONN> Requested link rate=%" NvU64_fmtu " is larger than sinkMaxLinkRate=%" NvU64_fmtu,
linkRate10M, hal->getMaxLinkRate());
return false;
}
@@ -5644,7 +5655,7 @@ bool ConnectorImpl::validateLinkConfiguration(const LinkConfiguration & lConfig)
NvU32 i;
if (!hal->isIndexedLinkrateEnabled())
{
DP_PRINTF(DP_ERROR, "DPCONN> Indexed Link Rate=%d is Not Enabled in Sink", linkRate10M);
DP_PRINTF(DP_ERROR, "DPCONN> Indexed Link Rate=%" NvU64_fmtu " is Not Enabled in Sink", linkRate10M);
return false;
}
@@ -5659,14 +5670,14 @@ bool ConnectorImpl::validateLinkConfiguration(const LinkConfiguration & lConfig)
break;
if (ilrTable[i] == 0)
{
DP_PRINTF(DP_ERROR, "DPCONN> Indexed Link Rate=%d is Not Found", linkRate10M);
DP_PRINTF(DP_ERROR, "DPCONN> Indexed Link Rate=%" NvU64_fmtu " is Not Found", linkRate10M);
return false;
}
}
if (i == NV0073_CTRL_DP_MAX_INDEXED_LINK_RATES)
{
DP_PRINTF(DP_ERROR, "DPCONN> Indexed Link Rate=%d is Not Found", linkRate10M);
DP_PRINTF(DP_ERROR, "DPCONN> Indexed Link Rate=%" NvU64_fmtu " is Not Found", linkRate10M);
return false;
}
}
@@ -5687,6 +5698,12 @@ bool ConnectorImpl::train(const LinkConfiguration & lConfig, bool force,
return false;
}
if (this->bIgnoreCapsAndForceHighestLc)
{
force = true;
hal->setPowerState(PowerStateD3);
}
//
// Cancel pending HDCP authentication callbacks if have or may interrupt
// active link training that violates spec.
@@ -6702,19 +6719,19 @@ bool ConnectorImpl::updateDpTunnelBwAllocation()
connectorTunnelBw += devMaxModeBwRequired;
}
DP_PRINTF(DP_INFO, "Required Connector Tunnel BW: %d Mbps", connectorTunnelBw / (1000 * 1000));
DP_PRINTF(DP_INFO, "Required Connector Tunnel BW: %" NvU64_fmtu " Mbps", connectorTunnelBw / (1000 * 1000));
NvU64 maxTunnelBw = getMaxTunnelBw();
if (connectorTunnelBw > maxTunnelBw)
{
DP_PRINTF(DP_INFO, "Requested connector tunnel BW is larger than max Tunnel BW of %d Mbps. Overriding Max Tunnel BW\n",
DP_PRINTF(DP_INFO, "Requested connector tunnel BW is larger than max Tunnel BW of %" NvU64_fmtu " Mbps. Overriding Max Tunnel BW\n",
maxTunnelBw / (1000 * 1000));
connectorTunnelBw = maxTunnelBw;
}
if (!allocateDpTunnelBw(connectorTunnelBw))
{
DP_PRINTF(DP_ERROR, "Failed to allocate Dp Tunnel BW: %d Mbps", connectorTunnelBw / (1000 * 1000));
DP_PRINTF(DP_ERROR, "Failed to allocate Dp Tunnel BW: %" NvU64_fmtu " Mbps", connectorTunnelBw / (1000 * 1000));
return false;
}
return true;
@@ -7537,7 +7554,7 @@ bool ConnectorImpl::setPreferredLinkConfig(LinkConfiguration & lc, bool commit,
if (!validateLinkConfiguration(lc))
{
DP_PRINTF(DP_ERROR, "Client requested bad LinkConfiguration. peakRate=%d, lanes=%d, bIs128b132ChannelCoding=%d",
DP_PRINTF(DP_ERROR, "Client requested bad LinkConfiguration. peakRate=%" LinkRate_fmtu ", lanes=%d, bIs128b132ChannelCoding=%d",
lc.peakRate, lc.lanes, lc.bIs128b132bChannelCoding);
return false;
}
@@ -8166,7 +8183,7 @@ bool ConnectorImpl::handleTestLinkTrainRequest()
DP_ASSERT(0 && "Compliance: no group attached");
}
DP_PRINTF(DP_NOTICE, "DP> Compliance: LT on IRQ request: 0x%x, %d.", requestedRate, requestedLanes);
DP_PRINTF(DP_NOTICE, "DP> Compliance: LT on IRQ request: 0x%" LinkRate_fmtx ", %d.", requestedRate, requestedLanes);
// now see whether the current resolution is supported on the requested link config
LinkConfiguration lc(&linkPolicy, requestedLanes, requestedRate,
hal->getEnhancedFraming(),
@@ -8180,7 +8197,7 @@ bool ConnectorImpl::handleTestLinkTrainRequest()
{
if (willLinkSupportModeSST(lc, groupAttached->lastModesetInfo))
{
DP_PRINTF(DP_NOTICE, "DP> Compliance: Executing LT on IRQ: 0x%x, %d.", requestedRate, requestedLanes);
DP_PRINTF(DP_NOTICE, "DP> Compliance: Executing LT on IRQ: 0x%" LinkRate_fmtx ", %d.", requestedRate, requestedLanes);
// we need to force the requirement irrespective of whether is supported or not.
if (!enableFlush())
{
src/common/displayport/src/dp_connectorimpl2x.cpp
+9 -9
View File
@@ -247,13 +247,13 @@ bool ConnectorImpl2x::validateLinkConfiguration(const LinkConfiguration &lConfig
{
if (!IS_VALID_DP2_X_LINKBW(linkRate10M))
{
DP_PRINTF(DP_ERROR, "DP2xCONN> Requested link rate=%d is not valid", linkRate10M);
DP_PRINTF(DP_ERROR, "DP2xCONN> Requested link rate=%" NvU64_fmtu " is not valid", linkRate10M);
return false;
}
if (lConfig.peakRate > hal->getMaxLinkRate())
{
DP_PRINTF(DP_ERROR, "DP2xCONN> Requested link rate=%d is larger than sinkMaxLinkRate=%d",
DP_PRINTF(DP_ERROR, "DP2xCONN> Requested link rate=%" NvU64_fmtu " is larger than sinkMaxLinkRate=%" LinkRate_fmtu,
linkRate10M, hal->getMaxLinkRate());
return false;
}
@@ -264,7 +264,7 @@ bool ConnectorImpl2x::validateLinkConfiguration(const LinkConfiguration &lConfig
NvU32 i;
if (!hal->isIndexedLinkrateEnabled())
{
DP_PRINTF(DP_ERROR, "DP2xCONN> Indexed Link Rate=%d is Not Enabled in Sink", linkRate10M);
DP_PRINTF(DP_ERROR, "DP2xCONN> Indexed Link Rate=%" NvU64_fmtu " is Not Enabled in Sink", linkRate10M);
return false;
}
@@ -279,13 +279,13 @@ bool ConnectorImpl2x::validateLinkConfiguration(const LinkConfiguration &lConfig
break;
if (ilrTable[i] == 0)
{
DP_PRINTF(DP_ERROR, "DP2xCONN> Indexed Link Rate=%d is Not Found", linkRate10M);
DP_PRINTF(DP_ERROR, "DP2xCONN> Indexed Link Rate=%" NvU64_fmtu " is Not Found", linkRate10M);
return false;
}
}
if (i == NV0073_CTRL_DP_MAX_INDEXED_LINK_RATES)
{
DP_PRINTF(DP_ERROR, "DP2xCONN> Indexed Link Rate=%d is Not Found", linkRate10M);
DP_PRINTF(DP_ERROR, "DP2xCONN> Indexed Link Rate=%" NvU64_fmtu " is Not Found", linkRate10M);
return false;
}
}
@@ -657,7 +657,7 @@ bool ConnectorImpl2x::notifyAttachBegin(Group *target, const DpModesetParams &mo
}
}
DP_PRINTF(DP_NOTICE, "DP2xCONN> Notify Attach Begin (Head %d, pclk %d (KHz) raster %d x %d %d bpp)",
DP_PRINTF(DP_NOTICE, "DP2xCONN> Notify Attach Begin (Head %d, pclk %" NvU64_fmtu " (KHz) raster %d x %d %d bpp)",
modesetParams.headIndex, (pixelClockHz/1000), rasterWidth, rasterHeight, depth);
NV_DPTRACE_INFO(NOTIFY_ATTACH_BEGIN, modesetParams.headIndex, pixelClockHz, rasterWidth, rasterHeight,
depth, bEnableDsc, bEnableFEC);
@@ -1763,7 +1763,7 @@ bool ConnectorImpl2x::handleTestLinkTrainRequest()
DP_ASSERT(0 && "Compliance: no group attached");
}
DP_PRINTF(DP_NOTICE, "DP> Compliance: LT on IRQ request: 0x%x, %d.", requestedRate, requestedLanes);
DP_PRINTF(DP_NOTICE, "DP> Compliance: LT on IRQ request: 0x%" LinkRate_fmtx ", %d.", requestedRate, requestedLanes);
// now see whether the current resolution is supported on the requested link config
LinkConfiguration lc(&linkPolicy, requestedLanes, requestedRate, hal->getEnhancedFraming(),
false, // MST
@@ -1776,7 +1776,7 @@ bool ConnectorImpl2x::handleTestLinkTrainRequest()
{
if (willLinkSupportMode(lc, groupAttached->lastModesetInfo, groupAttached->headIndex, NULL, NULL))
{
DP_PRINTF(DP_NOTICE, "DP> Compliance: Executing LT on IRQ: 0x%x, %d.", requestedRate, requestedLanes);
DP_PRINTF(DP_NOTICE, "DP> Compliance: Executing LT on IRQ: 0x%" LinkRate_fmtx ", %d.", requestedRate, requestedLanes);
// we need to force the requirement irrespective of whether is supported or not.
if (!enableFlush())
{
@@ -1801,7 +1801,7 @@ bool ConnectorImpl2x::handleTestLinkTrainRequest()
}
else // linkconfig is not supporting bandwidth. Simply return NACK
{
DP_PRINTF(DP_ERROR, "DP> Compliance: IMP failed with requested link configuration: 0x%x, %d.",
DP_PRINTF(DP_ERROR, "DP> Compliance: IMP failed with requested link configuration: 0x%" LinkRate_fmtx ", %d.",
requestedRate, requestedLanes);
hal->setTestResponse(false);
return false;
src/common/displayport/src/dp_deviceimpl.cpp
+1 -1
View File
@@ -3333,7 +3333,7 @@ bool DeviceImpl::setModeList(DisplayPort::DpModesetParams *modeList, unsigned nu
connector->endCompoundQuery();
}
DP_PRINTF(DP_INFO, "Computed Max mode BW: %d Mbps", maxModeBwRequired / (1000 * 1000));
DP_PRINTF(DP_INFO, "Computed Max mode BW: %" NvU64_fmtu " Mbps", maxModeBwRequired / (1000 * 1000));
connector->updateDpTunnelBwAllocation();
src/common/displayport/src/dp_evoadapter.cpp
+3 -1
View File
@@ -107,7 +107,9 @@ const struct
{NV_DP_REGKEY_SKIP_ZERO_OUI_CACHE, &dpRegkeyDatabase.bSkipZeroOuiCache, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_ENABLE_FIX_FOR_5147205, &dpRegkeyDatabase.bEnable5147205Fix, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_FORCE_HEAD_SHUTDOWN, &dpRegkeyDatabase.bForceHeadShutdown, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_EXPOSE_DSC_DEVID_WAR, &dpRegkeyDatabase.bEnableDevId, DP_REG_VAL_BOOL}
{NV_DP_REGKEY_EXPOSE_DSC_DEVID_WAR, &dpRegkeyDatabase.bEnableDevId, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_HDMI_ON_DP_PLUS_PLUS, &dpRegkeyDatabase.bHDMIOnDPPlusPlus, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_IGNORE_CAPS_AND_FORCE_HIGHEST_LC, &dpRegkeyDatabase.bIgnoreCapsAndForceHighestLc, DP_REG_VAL_BOOL}
};
EvoMainLink::EvoMainLink(EvoInterface * provider, Timer * timer) :
src/common/inc/nvBldVer.h
+10 -10
View File
@@ -36,25 +36,25 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r581_07
#define NV_BUILD_BRANCH r581_36
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r581_07
#define NV_PUBLIC_BRANCH r581_36
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r580/r581_07-228"
#define NV_BUILD_CHANGELIST_NUM (36467788)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r580/r581_36-271"
#define NV_BUILD_CHANGELIST_NUM (36580581)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r580/r581_07-228"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36467788)
#define NV_BUILD_NAME "rel/gpu_drv/r580/r581_36-271"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36580581)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r581_07-5"
#define NV_BUILD_CHANGELIST_NUM (36456855)
#define NV_BUILD_BRANCH_VERSION "r581_36-3"
#define NV_BUILD_CHANGELIST_NUM (36570941)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "581.19"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36456855)
#define NV_BUILD_NAME "581.42"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36570941)
#define NV_BUILD_BRANCH_BASE_VERSION R580
#endif
// End buildmeister python edited section
src/common/inc/nvUnixVersion.h
+1 -1
View File
@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "580.82.09"
#define NV_VERSION_STRING "580.95.05"
#else
src/common/modeset/hdmipacket/nvhdmi_frlInterface.h
+30
View File
@@ -199,6 +199,7 @@ typedef struct tagHDMI_FRL_CONFIG
* *
* Calls RM to get DSC related src side caps. Performs physical link training to determine if *
* sink reported max FRL rate can actually be supported on the physical link *
* This API is deprecated. Instead, use NvHdmi_AssessLinkCapabilities2(). *
*************************************************************************************************/
NVHDMIPKT_RESULT
NvHdmi_AssessLinkCapabilities(NvHdmiPkt_Handle libHandle,
@@ -208,6 +209,35 @@ NvHdmi_AssessLinkCapabilities(NvHdmiPkt_Handle libHandle,
HDMI_SRC_CAPS *pSrcCaps,
HDMI_SINK_CAPS *pSinkCaps);
/************************************************************************************************
* NvHdmi_AssessLinkCapabilities2: *
* *
* Input parameters: *
* subDevice - Sub Device ID. *
* displayId - Display ID. *
* pSinkEdid - EDID of sink *
* bPerformLinkTrainingToAssess - Perform link training to determin max supported link rate. *
* bIsDisplayActive - Is the given displayId actively attached to head. *
* currFRLRate - If the given displayId is active then provide current FRL link rate. *
* *
* Output parameters: *
* pSrcCaps - src capabilities - DSC caps *
* pSinkCaps - sink capabilities - actual caps calculated from link training *
* *
* Calls RM to get DSC related src side caps. Performs physical link training to determine if *
* sink reported max FRL rate can actually be supported on the physical link *
*************************************************************************************************/
NVHDMIPKT_RESULT
NvHdmi_AssessLinkCapabilities2(NvHdmiPkt_Handle libHandle,
NvU32 subDevice,
NvU32 displayId,
NVT_EDID_INFO const * const pSinkEdid,
const NvBool bPerformLinkTrainingToAssess,
const NvBool bIsDisplayActive,
const HDMI_FRL_DATA_RATE currFRLRate,
HDMI_SRC_CAPS *pSrcCaps,
HDMI_SINK_CAPS *pSinkCaps);
/************************************************************************************************
* NvHdmi_QueryFRLConfig: *
* *
src/common/modeset/hdmipacket/nvhdmipkt.c
+28 -1
View File
@@ -384,6 +384,28 @@ NvHdmi_AssessLinkCapabilities(NvHdmiPkt_Handle libHandle,
NVT_EDID_INFO const * const pSinkEdid,
HDMI_SRC_CAPS *pSrcCaps,
HDMI_SINK_CAPS *pSinkCaps)
{
return NvHdmi_AssessLinkCapabilities2(libHandle,
subDevice,
displayId,
pSinkEdid,
NV_FALSE /* bPerformLinkTrainingToAssess */,
NV_FALSE /* bIsDisplayActive */,
HDMI_FRL_DATA_RATE_NONE /* currFRLRate */,
pSrcCaps,
pSinkCaps);
}
NVHDMIPKT_RESULT
NvHdmi_AssessLinkCapabilities2(NvHdmiPkt_Handle libHandle,
NvU32 subDevice,
NvU32 displayId,
NVT_EDID_INFO const * const pSinkEdid,
const NvBool bPerformLinkTrainingToAssess,
const NvBool bIsDisplayActive,
const HDMI_FRL_DATA_RATE currFRLRate,
HDMI_SRC_CAPS *pSrcCaps,
HDMI_SINK_CAPS *pSinkCaps)
{
if (libHandle == NVHDMIPKT_INVALID_HANDLE)
{
@@ -402,9 +424,13 @@ NvHdmi_AssessLinkCapabilities(NvHdmiPkt_Handle libHandle,
subDevice,
displayId,
pSinkEdid,
bPerformLinkTrainingToAssess,
bIsDisplayActive,
currFRLRate,
pSrcCaps,
pSinkCaps);
}
/*
* NvHdmi_QueryFRLConfig
*/
@@ -686,8 +712,9 @@ NvHdmiPkt_InitializeLibrary(NvU32 const hwClass,
pClass->callback.checkTimeout = pCallbacks->checkTimeout;
#endif
#if defined (DEBUG)
pClass->callback.print = pCallbacks->print;
#if defined (DEBUG)
pClass->callback.assert = pCallbacks->assert;
#endif
src/common/modeset/hdmipacket/nvhdmipkt_0073.c
+8 -5
View File
@@ -308,12 +308,15 @@ hdmiWriteDummyPacketCtrl(NVHDMIPKT_CLASS* pThis,
}
NVHDMIPKT_RESULT
hdmiAssessLinkCapabilitiesDummy(NVHDMIPKT_CLASS *pThis,
NvU32 subDevice,
NvU32 displayId,
hdmiAssessLinkCapabilitiesDummy(NVHDMIPKT_CLASS *pThis,
NvU32 subDevice,
NvU32 displayId,
NVT_EDID_INFO const * const pSinkEdid,
HDMI_SRC_CAPS *pSrcCaps,
HDMI_SINK_CAPS *pSinkCaps)
const NvBool bPerformLinkTrainingToAssess,
const NvBool bIsDisplayActive,
HDMI_FRL_DATA_RATE currFRLRate,
HDMI_SRC_CAPS *pSrcCaps,
HDMI_SINK_CAPS *pSinkCaps)
{
NvHdmiPkt_Print(pThis, "ERROR - Dummy function hdmiAssessLinkCapabilitiesDummy called. "
"Should never be called.");
src/common/modeset/hdmipacket/nvhdmipkt_C671.c
+193 -66
View File
@@ -171,6 +171,168 @@ static void populateAudioCaps(NVT_EDID_CEA861_INFO const * const p861ExtBlock,
}
}
static NVHDMIPKT_RESULT SetFRLLinkRate(NVHDMIPKT_CLASS *pThis,
const NvU32 subDevice,
const NvU32 displayId,
const NvBool bFakeLt,
const NvBool bLinkAssessmentOnly,
const NvU32 frlRate)
{
NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_LINK_CONFIG_PARAMS params = {0};
NVMISC_MEMSET(&params, 0, sizeof(params));
params.subDeviceInstance = subDevice;
params.displayId = displayId;
params.data = frlRate;
params.bFakeLt = bFakeLt;
params.bLinkAssessmentOnly = bLinkAssessmentOnly;
#if NVHDMIPKT_RM_CALLS_INTERNAL
if (CALL_DISP_RM(NvRmControl)(pThis->clientHandles.hClient,
pThis->clientHandles.hDisplay,
NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_FRL_CONFIG,
&params,
sizeof(params)) != NVOS_STATUS_SUCCESS)
#else // !NVHDMIPKT_RM_CALLS_INTERNAL
NvBool bSuccess = pThis->callback.rmDispControl2(pThis->cbHandle,
params.subDeviceInstance,
NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_FRL_CONFIG,
&params,
sizeof(params));
if (bSuccess == NV_FALSE)
#endif // NVHDMIPKT_RM_CALLS_INTERNAL
{
NvHdmiPkt_Print(pThis, "ERROR - RM call to set HDMI FRL failed.");
NvHdmiPkt_Assert(0);
return NVHDMIPKT_FAIL;
}
return NVHDMIPKT_SUCCESS;
}
static NVHDMIPKT_RESULT
SetFRLFlushMode(NVHDMIPKT_CLASS *pThis,
const NvU32 subDevice,
const NvU32 displayId,
const NvU32 bEnable)
{
NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_FLUSH_MODE_PARAMS params = {0};
NVMISC_MEMSET(&params, 0, sizeof(params));
params.subDeviceInstance = subDevice;
params.displayId = displayId;
params.bEnable = bEnable;
#if NVHDMIPKT_RM_CALLS_INTERNAL
if (CALL_DISP_RM(NvRmControl)(pThis->clientHandles.hClient,
pThis->clientHandles.hDisplay,
NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_FRL_FLUSH_MODE,
&params,
sizeof(params)) != NVOS_STATUS_SUCCESS)
#else // !NVHDMIPKT_RM_CALLS_INTERNAL
NvBool bSuccess = pThis->callback.rmDispControl2(pThis->cbHandle,
params.subDeviceInstance,
NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_FRL_FLUSH_MODE,
&params,
sizeof(params));
if (bSuccess == NV_FALSE)
#endif // NVHDMIPKT_RM_CALLS_INTERNAL
{
NvHdmiPkt_Print(pThis, "ERROR - RM call to set HDMI FRL Flush Mode failed.");
NvHdmiPkt_Assert(0);
return NVHDMIPKT_FAIL;
}
return NVHDMIPKT_SUCCESS;
}
static NVHDMIPKT_RESULT
performLinkTraningToAssessFRLLink(NVHDMIPKT_CLASS *pThis,
NvU32 subDevice,
NvU32 displayId,
const NvBool bIsDisplayActive,
const HDMI_FRL_DATA_RATE currFRLRate,
NvU32 *pMaxFRLRate)
{
const NvU32 nv0073currFRLRate =
translateFRLRateToNv0073SetHdmiFrlConfig(currFRLRate);
NVHDMIPKT_RESULT ret = NVHDMIPKT_SUCCESS;
NvU32 maxFRLRate = *pMaxFRLRate;
if (bIsDisplayActive) {
ret = SetFRLFlushMode(pThis, subDevice, displayId,
NV_TRUE /* bEnable */);
if (ret != NVHDMIPKT_SUCCESS)
{
NvHdmiPkt_Assert(0);
return ret;
}
}
while(maxFRLRate != NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_NONE)
{
// If the display is active and the maximum link rate matches the link
// rate required for the current mode timings, avoid marking the set
// link configuration call as an assessment only. This prevents
// re-training after the assessment.
const NvBool bLinkAssessmentOnly =
bIsDisplayActive ? (nv0073currFRLRate != maxFRLRate) : NV_TRUE;
if (SetFRLLinkRate(pThis, subDevice, displayId,
NV_FALSE /* bFakeLt */, bLinkAssessmentOnly,
maxFRLRate) == NVHDMIPKT_SUCCESS)
{
break;
}
maxFRLRate--;
}
if (bIsDisplayActive)
{
// If the displayId is currently attached to the head, restore the FRL
// link rate to prevent the display engine from hanging.
if (nv0073currFRLRate != maxFRLRate)
{
const NvBool bFakeLt = (nv0073currFRLRate > maxFRLRate);
if (SetFRLLinkRate(pThis, subDevice, displayId,
bFakeLt, NV_FALSE /* bLinkAssessmentOnly */,
currFRLRate) != NVHDMIPKT_SUCCESS)
{
if (!bFakeLt) {
if (SetFRLLinkRate(pThis, subDevice, displayId,
NV_TRUE, NV_FALSE /* bLinkAssessmentOnly */,
currFRLRate) != NVHDMIPKT_SUCCESS) {
NvHdmiPkt_Assert(0);
}
}
}
}
ret = SetFRLFlushMode(pThis, subDevice, displayId,
NV_FALSE /* bEnable */);
if (ret != NVHDMIPKT_SUCCESS)
{
NvHdmiPkt_Assert(0);
}
}
else
{
NVHDMIPKT_RESULT ret = hdmiClearFRLConfigC671(pThis, subDevice,
displayId);
if (ret != NVHDMIPKT_SUCCESS)
{
NvHdmiPkt_Assert(0);
}
}
*pMaxFRLRate = maxFRLRate;
return NVHDMIPKT_SUCCESS;
}
/*
* hdmiAssessLinkCapabilities
*
@@ -181,12 +343,15 @@ static void populateAudioCaps(NVT_EDID_CEA861_INFO const * const p861ExtBlock,
* but for now, no incentive to do so. In future move it out to better place as need arises
*/
static NVHDMIPKT_RESULT
hdmiAssessLinkCapabilitiesC671(NVHDMIPKT_CLASS *pThis,
NvU32 subDevice,
NvU32 displayId,
hdmiAssessLinkCapabilitiesC671(NVHDMIPKT_CLASS *pThis,
NvU32 subDevice,
NvU32 displayId,
NVT_EDID_INFO const * const pSinkEdid,
HDMI_SRC_CAPS *pSrcCaps,
HDMI_SINK_CAPS *pSinkCaps)
const NvBool bPerformLinkTrainingToAssess,
const NvBool bIsDisplayActive,
const HDMI_FRL_DATA_RATE currFRLRate,
HDMI_SRC_CAPS *pSrcCaps,
HDMI_SINK_CAPS *pSinkCaps)
{
// Read DSC caps from RM - gpu caps for DSC are same across DP and HDMI FRL (HDMI 2.1+)
@@ -264,11 +429,25 @@ hdmiAssessLinkCapabilitiesC671(NVHDMIPKT_CLASS *pThis,
populateAudioCaps(&pSinkEdid->ext861, pSinkCaps);
populateAudioCaps(&pSinkEdid->ext861_2, pSinkCaps);
NvU32 setFRLRate = pSinkEdid->hdmiForumInfo.max_FRL_Rate;
NvU32 maxFRLRate = pSinkEdid->hdmiForumInfo.max_FRL_Rate;
pSinkCaps->linkMaxFRLRate = translateFRLCapToFRLDataRate(setFRLRate);
if (bPerformLinkTrainingToAssess) {
NVHDMIPKT_RESULT ret = performLinkTraningToAssessFRLLink(pThis,
subDevice,
displayId,
bIsDisplayActive,
currFRLRate,
&maxFRLRate);
if (ret != NVHDMIPKT_SUCCESS) {
pSinkCaps->linkMaxFRLRate = HDMI_FRL_DATA_RATE_NONE;
pSinkCaps->linkMaxFRLRateDSC = HDMI_FRL_DATA_RATE_NONE;
return ret;
}
}
pSinkCaps->linkMaxFRLRate = translateFRLCapToFRLDataRate(maxFRLRate);
pSinkCaps->linkMaxFRLRateDSC = (pSrcCaps->dscCaps.dscCapable &&
(pSinkEdid->hdmiForumInfo.dsc_Max_FRL_Rate > setFRLRate)) ?
(pSinkEdid->hdmiForumInfo.dsc_Max_FRL_Rate > maxFRLRate)) ?
pSinkCaps->linkMaxFRLRate :
translateFRLCapToFRLDataRate(pSinkEdid->hdmiForumInfo.dsc_Max_FRL_Rate);
@@ -1238,36 +1417,9 @@ hdmiSetFRLConfigC671(NVHDMIPKT_CLASS *pThis,
NvBool bFakeLt,
HDMI_FRL_CONFIG *pFRLConfig)
{
NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_LINK_CONFIG_PARAMS params = {0};
NVMISC_MEMSET(&params, 0, sizeof(params));
params.subDeviceInstance = subDevice;
params.displayId = displayId;
params.data = translateFRLRateToNv0073SetHdmiFrlConfig(pFRLConfig->frlRate);
params.bFakeLt = bFakeLt;
#if NVHDMIPKT_RM_CALLS_INTERNAL
if (CALL_DISP_RM(NvRmControl)(pThis->clientHandles.hClient,
pThis->clientHandles.hDisplay,
NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_FRL_CONFIG,
&params,
sizeof(params)) != NVOS_STATUS_SUCCESS)
#else // !NVHDMIPKT_RM_CALLS_INTERNAL
NvBool bSuccess = pThis->callback.rmDispControl2(pThis->cbHandle,
params.subDeviceInstance,
NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_FRL_CONFIG,
&params,
sizeof(params));
if (bSuccess == NV_FALSE)
#endif // NVHDMIPKT_RM_CALLS_INTERNAL
{
NvHdmiPkt_Print(pThis, "ERROR - RM call to set HDMI FRL failed.");
NvHdmiPkt_Assert(0);
return NVHDMIPKT_FAIL;
}
return NVHDMIPKT_SUCCESS;
return SetFRLLinkRate(pThis, subDevice, displayId, bFakeLt,
NV_FALSE /* bLinkAssessmentOnly */,
translateFRLRateToNv0073SetHdmiFrlConfig(pFRLConfig->frlRate));
}
/*
@@ -1278,34 +1430,9 @@ hdmiClearFRLConfigC671(NVHDMIPKT_CLASS *pThis,
NvU32 subDevice,
NvU32 displayId)
{
NVHDMIPKT_RESULT result = NVHDMIPKT_SUCCESS;
NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_LINK_CONFIG_PARAMS params = {0};
NVMISC_MEMSET(&params, 0, sizeof(params));
params.subDeviceInstance = subDevice;
params.displayId = displayId;
params.data = NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_NONE;
#if NVHDMIPKT_RM_CALLS_INTERNAL
if (CALL_DISP_RM(NvRmControl)(pThis->clientHandles.hClient,
pThis->clientHandles.hDisplay,
NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_FRL_CONFIG,
&params,
sizeof(params)) != NVOS_STATUS_SUCCESS)
#else // !NVHDMIPKT_RM_CALLS_INTERNAL
NvBool bSuccess = pThis->callback.rmDispControl2(pThis->cbHandle,
params.subDeviceInstance,
NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_FRL_CONFIG,
&params,
sizeof(params));
if (bSuccess == NV_FALSE)
#endif // NVHDMIPKT_RM_CALLS_INTERNAL
{
NvHdmiPkt_Print(pThis, "WARNING - RM call to reset HDMI FRL failed.");
result = NVHDMIPKT_FAIL;
}
return result;
return SetFRLLinkRate(pThis, subDevice, displayId,
NV_FALSE, NV_FALSE /* bLinkAssessmentOnly */,
NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_NONE);
}
static NVHDMIPKT_RESULT
src/common/modeset/hdmipacket/nvhdmipkt_class.h
+8 -5
View File
@@ -170,12 +170,15 @@ struct tagNVHDMIPKT_CLASS
// capacity required for target timing.
//
NVHDMIPKT_RESULT
(*hdmiAssessLinkCapabilities) (NVHDMIPKT_CLASS *pThis,
NvU32 subDevice,
NvU32 displayId,
(*hdmiAssessLinkCapabilities) (NVHDMIPKT_CLASS *pThis,
NvU32 subDevice,
NvU32 displayId,
NVT_EDID_INFO const * const pSinkEdid,
HDMI_SRC_CAPS *pSrcCaps,
HDMI_SINK_CAPS *pSinkCaps);
const NvBool bPerformLinkTrainingToAssess,
const NvBool bIsDisplayActive,
HDMI_FRL_DATA_RATE currFRLRate,
HDMI_SRC_CAPS *pSrcCaps,
HDMI_SINK_CAPS *pSinkCaps);
NVHDMIPKT_RESULT
(*hdmiQueryFRLConfig) (NVHDMIPKT_CLASS *pThis,
HDMI_VIDEO_TRANSPORT_INFO const * const pVidTransInfo,
src/common/modeset/hdmipacket/nvhdmipkt_common.h
+8 -9
View File
@@ -65,7 +65,6 @@ struct tagNVHDMIPKT_MEM_MAP
};
// HDMIPKT print define
#if defined (DEBUG)
#define NvHdmiPkt_Print(_p, ...) \
do { \
if ((_p)->callback.print) \
@@ -73,9 +72,6 @@ struct tagNVHDMIPKT_MEM_MAP
(_p)->callback.print((_p)->cbHandle, "HdmiPacketLibrary: " __VA_ARGS__); \
} \
} while(0)
#else
#define NvHdmiPkt_Print(_p, ...) /* nothing */
#endif
// HDMIPKT assert define
@@ -95,12 +91,15 @@ struct tagNVHDMIPKT_MEM_MAP
// Prototypes for common functions shared across implementations.
extern void hdmiWriteDummyPacket(NVHDMIPKT_CLASS*, NvU32*, NvU32, NvU32, NvU8 const *const);
extern NVHDMIPKT_RESULT hdmiAssessLinkCapabilitiesDummy(NVHDMIPKT_CLASS *pThis,
NvU32 subDevice,
NvU32 displayId,
extern NVHDMIPKT_RESULT hdmiAssessLinkCapabilitiesDummy(NVHDMIPKT_CLASS *pThis,
NvU32 subDevice,
NvU32 displayId,
NVT_EDID_INFO const * const pSinkEdid,
HDMI_SRC_CAPS *pSrcCaps,
HDMI_SINK_CAPS *pSinkCaps);
const NvBool bPerformLinkTrainingToAssess,
const NvBool bIsDisplayActive,
HDMI_FRL_DATA_RATE currFRLRate,
HDMI_SRC_CAPS *pSrcCaps,
HDMI_SINK_CAPS *pSinkCaps);
extern NVHDMIPKT_RESULT hdmiQueryFRLConfigDummy(NVHDMIPKT_CLASS *pThis,
HDMI_VIDEO_TRANSPORT_INFO const * const pVidTransInfo,
HDMI_QUERY_FRL_CLIENT_CONTROL const * const pClientCtrl,
src/common/sdk/nvidia/inc/class/cl0050.h
+18 -12
View File
@@ -45,31 +45,37 @@ typedef struct NV0050_ALLOCATION_PARAMETERS {
// Whether the CeUtils will allocate everything with RM client or external client
#define NV0050_CEUTILS_FLAGS_EXTERNAL 0:0
#define NV0050_CEUTILS_FLAGS_EXTERNAL_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_EXTERNAL_TRUE (0x00000001)
#define NV0050_CEUTILS_FLAGS_EXTERNAL_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_EXTERNAL_TRUE (0x00000001)
// Whether CeUtils will use virtual copy
#define NV0050_CEUTILS_FLAGS_VIRTUAL_MODE 1:1
#define NV0050_CEUTILS_FLAGS_VIRTUAL_MODE_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_VIRTUAL_MODE_TRUE (0x00000001)
#define NV0050_CEUTILS_FLAGS_VIRTUAL_MODE_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_VIRTUAL_MODE_TRUE (0x00000001)
// Whether the CeUtils is using fifo lite mode. Has to be internal
#define NV0050_CEUTILS_FLAGS_FIFO_LITE 2:2
#define NV0050_CEUTILS_FLAGS_FIFO_LITE_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_FIFO_LITE_TRUE (0x00000001)
#define NV0050_CEUTILS_FLAGS_FIFO_LITE_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_FIFO_LITE_TRUE (0x00000001)
// Whether the CeUtils will use BAR1 or BAR2 for data copy
#define NV0050_CEUTILS_FLAGS_NO_BAR1_USE 3:3
#define NV0050_CEUTILS_FLAGS_NO_BAR1_USE_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_NO_BAR1_USE_TRUE (0x00000001)
#define NV0050_CEUTILS_FLAGS_NO_BAR1_USE_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_NO_BAR1_USE_TRUE (0x00000001)
// Force a specific CE engine to be used be setting forceCeId
#define NV0050_CEUTILS_FLAGS_FORCE_CE_ID 4:4
#define NV0050_CEUTILS_FLAGS_FORCE_CE_ID_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_FORCE_CE_ID_TRUE (0x00000001)
#define NV0050_CEUTILS_FLAGS_FORCE_CE_ID_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_FORCE_CE_ID_TRUE (0x00000001)
// Use a CC secure channel
#define NV0050_CEUTILS_FLAGS_CC_SECURE 5:5
#define NV0050_CEUTILS_FLAGS_CC_SECURE_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_CC_SECURE_TRUE (0x00000001)
#define NV0050_CEUTILS_FLAGS_CC_SECURE_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_CC_SECURE_TRUE (0x00000001)
// Enable callbacks at work completion
#define NV0050_CEUTILS_FLAGS_ENABLE_COMPLETION_CB 6:6
#define NV0050_CEUTILS_FLAGS_ENABLE_COMPLETION_CB_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_ENABLE_COMPLETION_CB_TRUE (0x00000001)
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h
+211
View File
@@ -1672,4 +1672,215 @@ typedef struct NV0073_CTRL_DFP_SET_FORCE_BLACK_PIXELS_PARAMS {
NvBool bForceBlack;
} NV0073_CTRL_DFP_SET_FORCE_BLACK_PIXELS_PARAMS;
/*
* NV0073_CTRL_CMD_DFP_GET_DISP_PHY_INFO
*
* Return a high-level DISP PHY description that is independent of raw register
* encodings. Tools or firmware can use the information to reason about link
* routing and data-rate policy, etc.
*
* Parameters
* subDeviceInstance (in)
* Sub-device instance within NV04_DISPLAY_COMMON.
*
* edpClkSrc (out) enum NV0073_CTRL_DFP_DISP_PHY_EDP_CLK_SRC
* edpPllFreq (out) enum NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_SEL
*
* padLink[4] (out) One entry per DP Pad-Link (DP0...DP3):
* sorSel enum NV0073_CTRL_DFP_DISP_PHY_DP_SOR_SEL
* mode enum NV0073_CTRL_DFP_DISP_PHY_TYPEC_MODE
* cableOrient enum NV0073_CTRL_DFP_DISP_PHY_CABLE_ORIENT
* modeStatusDone NvBool (Alt-mode exit / entry finished)
* safeMode enum NV0073_CTRL_DFP_DISP_PHY_TYPEC_SAFE_MODE
*
* tpllForceVal enum NV0073_CTRL_DFP_DISP_PHY_TPLL_FORCE_VAL
* tpllForceEn NvBool (DA_XTP_LN_TPLL_SEL[16])
* pllPwrSeqEn NvBool (DP_PHY_DIG_PLL_CTL_0[0])
* pllPwrSeqState enum NV0073_CTRL_DFP_DISP_PHY_PLL_PWR_STATE
* bitRateSel enum NV0073_CTRL_DFP_DISP_PHY_DP_BIT_RATE_SEL
* pdCableIdA NV0073_CTRL_DFP_DISP_PHY_PD_CABLE_ID_A_INFO
* structured view of TOP_TYPEC_IPMUX_PD_CABLE_ID_A
* (DP-rate capability, pin sets, UHBR13.5 support,
* active component type, DP-AM version, ...)
*
* pdCableIdB NV0073_CTRL_DFP_DISP_PHY_PD_CABLE_ID_B_INFO
* structured view of TOP_TYPEC_IPMUX_PD_CABLE_ID_B
* (VCONN source indication)
*
* Status values
* NV_OK
* NV_ERR_INVALID_ARGUMENT invalid subDeviceInstance
* NV_ERR_NOT_SUPPORTED device doesn't have a display
*/
#define NV0073_CTRL_DFP_DISP_DP_PADLINK_COUNT 4U
// eDP clock source selection (EDP_PHY_DIG_MISC[3:0])
typedef enum NV0073_CTRL_DFP_DISP_PHY_EDP_CLK_SRC {
NV0073_CTRL_DFP_DISP_PHY_EDP_CLK_SRC_NONE = 0,
NV0073_CTRL_DFP_DISP_PHY_EDP_CLK_SRC_SOR0 = 1,
NV0073_CTRL_DFP_DISP_PHY_EDP_CLK_SRC_SOR1 = 2,
NV0073_CTRL_DFP_DISP_PHY_EDP_CLK_SRC_SOR2 = 4,
NV0073_CTRL_DFP_DISP_PHY_EDP_CLK_SRC_SOR3 = 8,
} NV0073_CTRL_DFP_DISP_PHY_EDP_CLK_SRC;
// eDP PLL frequency selector (EDP_PHY_DIG_BIT_RATE[3:0])
typedef enum NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_SEL {
NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_1_62GHZ = 1,
NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_2_16GHZ = 2,
NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_2_43GHZ = 3,
NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_2_70GHZ = 4,
NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_3_24GHZ = 5,
NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_4_32GHZ = 6,
NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_5_40GHZ = 7,
NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_6_75GHZ = 8,
NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_8_10GHZ = 9,
} NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_SEL;
// DP bit-rate selector (DP_PHY_DIG_BIT_RATE[2:0])
typedef enum NV0073_CTRL_DFP_DISP_PHY_DP_BIT_RATE_SEL {
NV0073_CTRL_DFP_DISP_PHY_DP_BIT_RATE_1_62GHZ = 0,
NV0073_CTRL_DFP_DISP_PHY_DP_BIT_RATE_2_70GHZ = 1,
NV0073_CTRL_DFP_DISP_PHY_DP_BIT_RATE_5_40GHZ = 2,
NV0073_CTRL_DFP_DISP_PHY_DP_BIT_RATE_8_10GHZ = 3,
NV0073_CTRL_DFP_DISP_PHY_DP_BIT_RATE_10_00GHZ = 4,
NV0073_CTRL_DFP_DISP_PHY_DP_BIT_RATE_13_50GHZ = 5,
NV0073_CTRL_DFP_DISP_PHY_DP_BIT_RATE_20_00GHZ = 6,
} NV0073_CTRL_DFP_DISP_PHY_DP_BIT_RATE_SEL;
// DP_PHY_DIG_MISC[3:0]
typedef enum NV0073_CTRL_DFP_DISP_PHY_DP_SOR_SEL {
NV0073_CTRL_DFP_DISP_PHY_DP_SOR_SEL_NONE = 0,
NV0073_CTRL_DFP_DISP_PHY_DP_SOR_SEL_SOR0 = 1,
NV0073_CTRL_DFP_DISP_PHY_DP_SOR_SEL_SOR1 = 2,
NV0073_CTRL_DFP_DISP_PHY_DP_SOR_SEL_SOR2 = 3,
NV0073_CTRL_DFP_DISP_PHY_DP_SOR_SEL_SOR3 = 4,
} NV0073_CTRL_DFP_DISP_PHY_DP_SOR_SEL;
// Type-C mux operating mode (TOP_TYPEC_IPMUX_CTRL[1:0])
typedef enum NV0073_CTRL_DFP_DISP_PHY_TYPEC_MODE {
NV0073_CTRL_DFP_DISP_PHY_TYPEC_MODE_USB4_2T2R = 0,
NV0073_CTRL_DFP_DISP_PHY_TYPEC_MODE_USB3_2T2R = 1,
NV0073_CTRL_DFP_DISP_PHY_TYPEC_MODE_DP_4T = 2,
NV0073_CTRL_DFP_DISP_PHY_TYPEC_MODE_DP_2T_USB3_1T1R = 3,
} NV0073_CTRL_DFP_DISP_PHY_TYPEC_MODE;
// Cable orientation (TOP_TYPEC_IPMUX_CTRL[2])
typedef enum NV0073_CTRL_DFP_DISP_PHY_CABLE_ORIENT {
NV0073_CTRL_DFP_DISP_PHY_ORIENT_UNFLIPPED = 0,
NV0073_CTRL_DFP_DISP_PHY_ORIENT_FLIPPED = 1,
} NV0073_CTRL_DFP_DISP_PHY_CABLE_ORIENT;
// Safe-mode control (TOP_TYPEC_IPMUX_CTRL[3])
typedef enum NV0073_CTRL_DFP_DISP_PHY_TYPEC_SAFE_MODE {
NV0073_CTRL_DFP_DISP_PHY_TYPEC_SAFE_MODE_ENABLED = 0, // IP-MUX held in Safe-Mode
NV0073_CTRL_DFP_DISP_PHY_TYPEC_SAFE_MODE_ALT = 1, // Safe-Mode disabled so Alt-Mode allowed
} NV0073_CTRL_DFP_DISP_PHY_TYPEC_SAFE_MODE;
// TPLL force-value codes (DA_XTP_LN_TPLL_SEL[15:8])
typedef enum NV0073_CTRL_DFP_DISP_PHY_TPLL_FORCE_VAL {
NV0073_CTRL_DFP_DISP_PHY_TPLL_FORCE_RBR_UHBR13_5 = 57, // RBR / UHBR13.5
NV0073_CTRL_DFP_DISP_PHY_TPLL_FORCE_HBR_HBR2 = 89, // HBR / HBR2
NV0073_CTRL_DFP_DISP_PHY_TPLL_FORCE_HBR3 = 121, // HBR3
NV0073_CTRL_DFP_DISP_PHY_TPLL_FORCE_UHBR10_UHBR20 = 26, // UHBR10 / UHBR20
} NV0073_CTRL_DFP_DISP_PHY_TPLL_FORCE_VAL;
// PLL power-sequence state (DP_PHY_DIG_PLL_CTL_0[2:1])
typedef enum NV0073_CTRL_DFP_DISP_PHY_PLL_PWR_STATE {
NV0073_CTRL_DFP_DISP_PHY_PLL_STATE_PD = 0,
NV0073_CTRL_DFP_DISP_PHY_PLL_STATE_BIAS_ON = 1,
NV0073_CTRL_DFP_DISP_PHY_PLL_STATE_PLL_ON = 2,
NV0073_CTRL_DFP_DISP_PHY_PLL_STATE_LANE_ON = 3,
} NV0073_CTRL_DFP_DISP_PHY_PLL_PWR_STATE;
// Supported DisplayPort data-rate capability (bits 5:2)
typedef enum NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DP_PROT {
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DP_PROT_NONE = 0,
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DP_PROT_UPTO_HBR3 = 1,
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DP_PROT_UHBR10_0 = 2,
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DP_PROT_UPTO_UHBR10_0 = 3,
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DP_PROT_UHBR20_0 = 4,
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DP_PROT_UPTO_HBR3_UHBR20_0 = 5,
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DP_PROT_UHBR10_0_UHBR20_0 = 6,
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DP_PROT_UPTO_UHBR20_0 = 7,
} NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DP_PROT;
// SRC / SINK pin-sets advertised by the cable (bits 15:8 / 23:16)
typedef enum NV0073_CTRL_DFP_DISP_PHY_PD_CBL_PIN_CAP {
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_PIN_CD = 12,
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_PIN_E = 16,
} NV0073_CTRL_DFP_DISP_PHY_PD_CBL_PIN_CAP;
// UHBR13.5 support is Boolean, using NvBool
// Active-component type (bits 29:28)
typedef enum NV0073_CTRL_DFP_DISP_PHY_PD_CBL_ACTIVE_COMP {
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_ACTIVE_PASSIVE = 0,
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_ACTIVE_RETIMER = 1,
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_ACTIVE_REDRIVER = 2,
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_ACTIVE_OPTICAL = 3,
} NV0073_CTRL_DFP_DISP_PHY_PD_CBL_ACTIVE_COMP;
// DP Alt-Mode version supported by the cable (bits 31:30)
typedef enum NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DPAM_VERS {
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DPAM_VERS_UPTO_2_0 = 0,
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DPAM_VERS_2_1_OR_LATER = 1,
} NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DPAM_VERS;
// VCONN source indication (Cable-ID-B bit 0)
typedef enum NV0073_CTRL_DFP_DISP_PHY_PD_CBL_VCONN_SRC {
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_VCONN_SRC_DPTX = 0,
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_VCONN_SRC_DPRX = 1,
} NV0073_CTRL_DFP_DISP_PHY_PD_CBL_VCONN_SRC;
typedef struct NV0073_CTRL_DFP_DISP_PHY_PD_CABLE_ID_A_INFO {
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DP_PROT dpProt;
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_PIN_CAP srcPinSet;
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_PIN_CAP sinkPinSet;
NvBool bUhbr13_5; // bit 26
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_ACTIVE_COMP activeComp; // bits 29:28
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DPAM_VERS dpamVers; // bits 31:30
} NV0073_CTRL_DFP_DISP_PHY_PD_CABLE_ID_A_INFO;
typedef struct NV0073_CTRL_DFP_DISP_PHY_PD_CABLE_ID_B_INFO {
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_VCONN_SRC vconnSrc; // bit 0
} NV0073_CTRL_DFP_DISP_PHY_PD_CABLE_ID_B_INFO;
typedef struct NV0073_CTRL_DFP_DISP_PHY_PADLINK_INFO {
// SOR routing
NV0073_CTRL_DFP_DISP_PHY_DP_SOR_SEL sorSel;
// Type-C mux status
NV0073_CTRL_DFP_DISP_PHY_TYPEC_MODE mode; // USB4_2T2R, etc
NV0073_CTRL_DFP_DISP_PHY_CABLE_ORIENT cableOrient;
NvBool bModeStatusDone; // Type-C IP-MUX has finished its mode-change power-down / power-up sequence when entering or exiting an alternate mode
NV0073_CTRL_DFP_DISP_PHY_TYPEC_SAFE_MODE safeMode;
// Data-rate / PLL settings
NV0073_CTRL_DFP_DISP_PHY_TPLL_FORCE_VAL tpllForceVal;
NvBool bTpllForceEn; // 0 = let hardware pick the appropriate TPLL settings automatically, 1 = force the TPLL to use tpllForceVal.
NvBool bPllPwrSeqEn; // 0 = normal automatic power-sequencer operation, 1 = override; the PHY obeys the explicit power state given in pllPwrSeqState.
NV0073_CTRL_DFP_DISP_PHY_PLL_PWR_STATE pllPwrSeqState;
NV0073_CTRL_DFP_DISP_PHY_DP_BIT_RATE_SEL bitRateSel;
// USB-PD cable identification
NV0073_CTRL_DFP_DISP_PHY_PD_CABLE_ID_A_INFO pdCableIdA;
NV0073_CTRL_DFP_DISP_PHY_PD_CABLE_ID_B_INFO pdCableIdB;
} NV0073_CTRL_DFP_DISP_PHY_PADLINK_INFO;
#define NV0073_CTRL_CMD_DFP_GET_DISP_PHY_INFO (0x731180U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_GET_DISP_PHY_INFO_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_DFP_GET_DISP_PHY_INFO_PARAMS_MESSAGE_ID (0x80U)
typedef struct NV0073_CTRL_DFP_GET_DISP_PHY_INFO_PARAMS {
NvU32 subDeviceInstance;
// eDP-wide settings
NV0073_CTRL_DFP_DISP_PHY_EDP_CLK_SRC edpClkSrc;
NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_SEL edpPllFreq;
// Per-Pad-Link (DP0...DP3) information
NV0073_CTRL_DFP_DISP_PHY_PADLINK_INFO padLink[NV0073_CTRL_DFP_DISP_DP_PADLINK_COUNT];
} NV0073_CTRL_DFP_GET_DISP_PHY_INFO_PARAMS;
/* _ctrl0073dfp_h_ */
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h
+46 -7
View File
@@ -1351,6 +1351,10 @@ typedef struct NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_PARAMS {
* bLtSkipped
* The flag returned indicating whether link training is skipped or not.
* TRUE if link training is skipped due to the link config is not changed.
* bLinkAssessmentOnly
* The flag as input to this command. It indicates that the client is doing
* link training only for the link assessment, no FRL video transmission is
* intended.
*
* Possible status values returned include:
* NV_OK -
@@ -1374,16 +1378,51 @@ typedef struct NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_LINK_CONFIG_PARAMS {
NvU32 data;
NvBool bFakeLt;
NvBool bLtSkipped;
NvBool bLinkAssessmentOnly;
} NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_LINK_CONFIG_PARAMS;
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE 2:0
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_NONE (0x00000000U)
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_3LANES_3G (0x00000001U)
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_3LANES_6G (0x00000002U)
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_6G (0x00000003U)
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_8G (0x00000004U)
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_10G (0x00000005U)
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_12G (0x00000006U)
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_NONE (0x00000000U)
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_3LANES_3G (0x00000001U)
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_3LANES_6G (0x00000002U)
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_6G (0x00000003U)
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_8G (0x00000004U)
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_10G (0x00000005U)
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_12G (0x00000006U)
/*
* NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_FRL_FLUSH_MODE
*
* This command is used to enable flush mode on given HDMI displayId in
* preparation for FRL link training. The flush mode can be enabled only if HDMI
* display is active and driven by FRL protocol. If display is not active then
* this control command does nothing.
*
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed.
* displayID
* This parameter specifies the displayID for the display output resource to
* configure.
* bEnable
* This parameter is an inputto this command.
*
* Possible status values returned include:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* If any argument is invalid for this control call, NV_ERR_INVALID_ARGUMENT
* status will be returned.
*/
#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_FRL_FLUSH_MODE (0x73029bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_FLUSH_MODE_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_FLUSH_MODE_PARAMS_MESSAGE_ID (0x9BU)
typedef struct NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_FLUSH_MODE_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvBool bEnable;
} NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_FLUSH_MODE_PARAMS;
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080msenc.h
+2 -2
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2004-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -68,7 +68,7 @@ typedef struct NV0080_CTRL_MSENC_GET_CAPS_PARAMS {
/* size in bytes of MSENC caps table */
#define NV0080_CTRL_MSENC_CAPS_TBL_SIZE 4
#define NV0080_CTRL_MSENC_CAPS_TBL_SIZE 5
/*
* NV0080_CTRL_CMD_MSENC_GET_CAPS_V2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h
+3
View File
@@ -430,6 +430,8 @@ typedef enum NV2080_CTRL_CE_LCE_TYPE {
*
* [in] lceType
* LCE type. Should be one of NV2080_CTRL_CE_LCE_TYPE_* values.
* [in] metadataForLceType
* Metadata for LCE type.
* [out] numPces
* Number of PCEs supported per LCE
* [out] numLces
@@ -450,6 +452,7 @@ typedef enum NV2080_CTRL_CE_LCE_TYPE {
typedef struct NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS {
NV2080_CTRL_CE_LCE_TYPE lceType;
NvU32 metadataForLceType;
NvU32 numPces;
NvU32 numLces;
NvU32 supportedPceMask;
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h
+27
View File
@@ -3714,5 +3714,32 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PPRM_PARAMS {
} NV2080_CTRL_NVLINK_PRM_ACCESS_PPRM_PARAMS;
/*
* NV2080_CTRL_NVLINK_SAVE_NODE_HOSTNAME
* NV2080_CTRL_NVLINK_GET_SAVED_NODE_HOSTNAME
*
* These commands store/retrieve a 64 char null-terminated ASCII string which is
* treated by the NVLINK firmware as the node's hostname for fabric reporting
* purposes.
*/
typedef struct NV2080_CTRL_NVLINK_NODE_HOSTNAME {
NvU8 name[64];
} NV2080_CTRL_NVLINK_NODE_HOSTNAME;
#define NV2080_CTRL_NVLINK_SAVE_NODE_HOSTNAME_PARAMS_MESSAGE_ID (0x9AU)
typedef struct NV2080_CTRL_NVLINK_SAVE_NODE_HOSTNAME_PARAMS {
NV2080_CTRL_NVLINK_NODE_HOSTNAME hostname;
} NV2080_CTRL_NVLINK_SAVE_NODE_HOSTNAME_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_SAVE_NODE_HOSTNAME (0x2080309aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SAVE_NODE_HOSTNAME_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_GET_SAVED_NODE_HOSTNAME_PARAMS_MESSAGE_ID (0x9BU)
typedef struct NV2080_CTRL_NVLINK_GET_SAVED_NODE_HOSTNAME_PARAMS {
NV2080_CTRL_NVLINK_NODE_HOSTNAME hostname;
} NV2080_CTRL_NVLINK_GET_SAVED_NODE_HOSTNAME_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_GET_SAVED_NODE_HOSTNAME (0x2080309bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_SAVED_NODE_HOSTNAME_PARAMS_MESSAGE_ID" */
/* _ctrl2080nvlink_h_ */
src/common/sdk/nvidia/inc/ctrl/ctrla081.h
+1
View File
@@ -113,6 +113,7 @@ typedef struct NVA081_CTRL_VGPU_INFO {
NvU32 encoderCapacity;
NV_DECLARE_ALIGNED(NvU64 bar1Length, 8);
NvU32 frlEnable;
NvU16 vgpuSsvid;
NvU8 adapterName[NV2080_GPU_MAX_NAME_STRING_LENGTH];
NvU16 adapterName_Unicode[NV2080_GPU_MAX_NAME_STRING_LENGTH];
NvU8 shortGpuNameString[NV2080_GPU_MAX_NAME_STRING_LENGTH];
src/common/sdk/nvidia/inc/nverror.h
+2 -2
View File
@@ -109,7 +109,7 @@
#define ROBUST_CHANNEL_NVJPG5_ERROR (103)
#define ROBUST_CHANNEL_NVJPG6_ERROR (104)
#define ROBUST_CHANNEL_NVJPG7_ERROR (105)
#define DESTINATION_FLA_TRANSLATION_ERROR (108)
#define NVLINK_REMOTE_TRANSLATION_ERROR (108)
#define SEC_FAULT_ERROR (110)
#define GSP_RPC_TIMEOUT (119)
#define GSP_ERROR (120)
@@ -129,7 +129,7 @@
#define ROBUST_CHANNEL_CE18_ERROR (134)
#define ROBUST_CHANNEL_CE19_ERROR (135)
#define ALI_TRAINING_FAIL (136)
#define NVLINK_FLA_PRIV_ERR (137)
#define NVLINK_PRIV_ERR (137)
#define ROBUST_CHANNEL_DLA_ERROR (138)
#define ROBUST_CHANNEL_OFA1_ERROR (139)
#define UNRECOVERABLE_ECC_ERROR_ESCAPE (140)
src/common/shared/inc/g_vgpu_chip_flags.h
+12 -19
View File
@@ -621,25 +621,6 @@ ENTRY(0x2238, 0x16B8, 0x10de, "NVIDIA A10M-10C"),
ENTRY(0x2238, 0x16B9, 0x10de, "NVIDIA A10M-20C"),
ENTRY(0x2238, 0x16E6, 0x10de, "NVIDIA A10M-1"),
ENTRY(0x2238, 0x2208, 0x10de, "NVIDIA A10M-3B"),
ENTRY(0x230E, 0x20F5, 0x10de, "NVIDIA H20L-1-15CME"),
ENTRY(0x230E, 0x20F6, 0x10de, "NVIDIA H20L-1-15C"),
ENTRY(0x230E, 0x20F7, 0x10de, "NVIDIA H20L-1-30C"),
ENTRY(0x230E, 0x20F8, 0x10de, "NVIDIA H20L-2-30C"),
ENTRY(0x230E, 0x20F9, 0x10de, "NVIDIA H20L-3-60C"),
ENTRY(0x230E, 0x20FA, 0x10de, "NVIDIA H20L-4-60C"),
ENTRY(0x230E, 0x20FB, 0x10de, "NVIDIA H20L-7-120C"),
ENTRY(0x230E, 0x20FC, 0x10de, "NVIDIA H20L-4C"),
ENTRY(0x230E, 0x20FD, 0x10de, "NVIDIA H20L-5C"),
ENTRY(0x230E, 0x20FE, 0x10de, "NVIDIA H20L-6C"),
ENTRY(0x230E, 0x20FF, 0x10de, "NVIDIA H20L-8C"),
ENTRY(0x230E, 0x2100, 0x10de, "NVIDIA H20L-10C"),
ENTRY(0x230E, 0x2101, 0x10de, "NVIDIA H20L-12C"),
ENTRY(0x230E, 0x2102, 0x10de, "NVIDIA H20L-15C"),
ENTRY(0x230E, 0x2103, 0x10de, "NVIDIA H20L-20C"),
ENTRY(0x230E, 0x2104, 0x10de, "NVIDIA H20L-30C"),
ENTRY(0x230E, 0x2105, 0x10de, "NVIDIA H20L-40C"),
ENTRY(0x230E, 0x2106, 0x10de, "NVIDIA H20L-60C"),
ENTRY(0x230E, 0x2107, 0x10de, "NVIDIA H20L-120C"),
ENTRY(0x2321, 0x1853, 0x10de, "NVIDIA H100L-1-12CME"),
ENTRY(0x2321, 0x1854, 0x10de, "NVIDIA H100L-1-12C"),
ENTRY(0x2321, 0x1855, 0x10de, "NVIDIA H100L-1-24C"),
@@ -1314,6 +1295,18 @@ ENTRY(0x2BB5, 0x21C6, 0x10de, "NVIDIA RTX Pro 6000 Blackwell DC-48"),
ENTRY(0x2BB5, 0x21C7, 0x10de, "NVIDIA RTX Pro 6000 Blackwell DC-96"),
ENTRY(0x2BB5, 0x21F8, 0x10de, "NVIDIA RTX Pro 6000 Blackwell DC-1-3B"),
ENTRY(0x2BB5, 0x21F9, 0x10de, "NVIDIA RTX Pro 6000 Blackwell DC-3B"),
ENTRY(0x2BB9, 0x2233, 0x10de, "NVIDIA RTX 6000D-1-42Q"),
ENTRY(0x2BB9, 0x2234, 0x10de, "NVIDIA RTX 6000D-1-42A"),
ENTRY(0x2BB9, 0x2235, 0x10de, "NVIDIA RTX 6000D-1-42C"),
ENTRY(0x2BB9, 0x2236, 0x10de, "NVIDIA RTX 6000D-1-42"),
ENTRY(0x2BB9, 0x2243, 0x10de, "NVIDIA RTX 6000D-2-84Q"),
ENTRY(0x2BB9, 0x2244, 0x10de, "NVIDIA RTX 6000D-2-84A"),
ENTRY(0x2BB9, 0x2245, 0x10de, "NVIDIA RTX 6000D-2-84C"),
ENTRY(0x2BB9, 0x2246, 0x10de, "NVIDIA RTX 6000D-2-84"),
ENTRY(0x2BB9, 0x226C, 0x10de, "NVIDIA RTX 6000D-84Q"),
ENTRY(0x2BB9, 0x226D, 0x10de, "NVIDIA RTX 6000D-84A"),
ENTRY(0x2BB9, 0x226E, 0x10de, "NVIDIA RTX 6000D-84C"),
ENTRY(0x2BB9, 0x226F, 0x10de, "NVIDIA RTX 6000D-84"),
};
#endif /* _G_VGPU_CHIP_FLAGS_H_ */
src/common/shared/inc/g_vgpu_resman_specific.h
+8 -8
View File
@@ -17,7 +17,6 @@ static inline void _get_chip_id_for_alias_pgpu(NvU32 *dev_id, NvU32 *subdev_id)
{ 0x20B7, 0x1804, 0x20B7, 0x1532 },
{ 0x20B9, 0x157F, 0x20B7, 0x1532 },
{ 0x20FD, 0x17F8, 0x20F5, 0x0 },
{ 0x230E, 0x20DF, 0x230E, 0x20DF },
{ 0x2324, 0x17A8, 0x2324, 0x17A6 },
{ 0x2329, 0x198C, 0x2329, 0x198B },
{ 0x232C, 0x2064, 0x232C, 0x2063 },
@@ -122,13 +121,6 @@ static const struct {
{0x20F610DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 1094}, // GRID A800-4-20C
{0x20F610DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 1095}, // GRID A800-7-40C
{0x20F610DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1091}, // GRID A800-1-10C
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 1499}, // NVIDIA H20L-1-15CME
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 1500}, // NVIDIA H20L-1-15C
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1501}, // NVIDIA H20L-1-30C
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU , 1502}, // NVIDIA H20L-2-30C
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU , 1503}, // NVIDIA H20L-3-60C
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 1504}, // NVIDIA H20L-4-60C
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 1505}, // NVIDIA H20L-7-120C
{0x232110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 1061}, // NVIDIA H100L-1-12CME
{0x232110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 1062}, // NVIDIA H100L-1-12C
{0x232110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1063}, // NVIDIA H100L-1-24C
@@ -308,6 +300,14 @@ static const struct {
{0x2BB510DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL) , 1619}, // NVIDIA RTX Pro 6000 Blackwell DC-4-48
{0x2BB510DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL) , 1620}, // NVIDIA RTX Pro 6000 Blackwell DC-4-96
{0x2BB510DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _QUARTER) , 2158}, // NVIDIA RTX Pro 6000 Blackwell DC-1-3B
{0x2BB910DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _MINI_HALF) , 2199}, // NVIDIA RTX 6000D-1-42Q
{0x2BB910DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _MINI_HALF) , 2200}, // NVIDIA RTX 6000D-1-42A
{0x2BB910DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _MINI_HALF) , 2201}, // NVIDIA RTX 6000D-1-42C
{0x2BB910DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _MINI_HALF) , 2202}, // NVIDIA RTX 6000D-1-42
{0x2BB910DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL) , 2203}, // NVIDIA RTX 6000D-2-84Q
{0x2BB910DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL) , 2204}, // NVIDIA RTX 6000D-2-84A
{0x2BB910DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL) , 2205}, // NVIDIA RTX 6000D-2-84C
{0x2BB910DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL) , 2206}, // NVIDIA RTX 6000D-2-84
};
#endif // GENERATE_vgpuSmcTypeIdMappings
src/common/shared/inc/nvdevid.h
+1
View File
@@ -654,6 +654,7 @@ enum {
, CS_AMD_RPH
, CS_INTEL_B660
, CS_AMPERE_AMPEREONE192
, CS_NVIDIA_T254
, CS_MAX_PCIE
};
src/common/uproc/os/libos-v3.1.0/lib/liblogdecode.c
+38 -28
View File
@@ -1871,25 +1871,25 @@ NvBool isLibosPreserveLogBufferFull(LIBOS_LOG_DECODE *pLogDecode, NvU32 gpuInsta
{
NvU64 i = (NvU32)(pLogDecode->numLogBuffers);
NvU32 tag = LIBOS_LOG_NVLOG_BUFFER_TAG(pLogDecode->sourceName, i * 2);
NVLOG_BUFFER_HANDLE handle = 0;
NV_STATUS status = nvlogGetBufferHandleFromTag(tag, &handle);
if (status != NV_OK)
//
// Cannot use nvlogGetBufferHandleFromTag here since in multi GPU case,
// we can have multiple buffers with exact same tag, only differentiable
// from gpuInstance
//
for (i = 0; i < NVLOG_MAX_BUFFERS; i++)
{
return NV_FALSE;
}
NVLOG_BUFFER *pNvLogBuffer = NvLogLogger.pBuffers[handle];
if (pNvLogBuffer == NULL)
{
return NV_FALSE;
}
if (FLD_TEST_DRF(LOG_BUFFER, _FLAGS, _PRESERVE, _YES, pNvLogBuffer->flags) &&
DRF_VAL(LOG, _BUFFER_FLAGS, _GPU_INSTANCE, pNvLogBuffer->flags) == gpuInstance &&
(pNvLogBuffer->pos >= pNvLogBuffer->size - NV_OFFSETOF(LIBOS_LOG_NVLOG_BUFFER, data) - sizeof(NvU64)))
{
return NV_TRUE;
if (NvLogLogger.pBuffers[i] != NULL)
{
NVLOG_BUFFER *pNvLogBuffer = NvLogLogger.pBuffers[i];
if ((pNvLogBuffer->tag == tag) &&
(DRF_VAL(LOG, _BUFFER_FLAGS, _GPU_INSTANCE, pNvLogBuffer->flags) == gpuInstance) &&
FLD_TEST_DRF(LOG_BUFFER, _FLAGS, _PRESERVE, _YES, pNvLogBuffer->flags) &&
(pNvLogBuffer->pos >= pNvLogBuffer->size - NV_OFFSETOF(LIBOS_LOG_NVLOG_BUFFER, data) - sizeof(NvU64)))
{
return NV_TRUE;
}
}
}
return NV_FALSE;
@@ -1897,19 +1897,27 @@ NvBool isLibosPreserveLogBufferFull(LIBOS_LOG_DECODE *pLogDecode, NvU32 gpuInsta
static NvBool findPreservedNvlogBuffer(NvU32 tag, NvU32 gpuInstance, NVLOG_BUFFER_HANDLE *pHandle)
{
NVLOG_BUFFER_HANDLE handle = 0;
NV_STATUS status = nvlogGetBufferHandleFromTag(tag, &handle);
NvU64 i;
if (status != NV_OK)
return NV_FALSE;
NVLOG_BUFFER *pNvLogBuffer = NvLogLogger.pBuffers[handle];
if (FLD_TEST_DRF(LOG_BUFFER, _FLAGS, _PRESERVE, _YES, pNvLogBuffer->flags) &&
DRF_VAL(LOG, _BUFFER_FLAGS, _GPU_INSTANCE, pNvLogBuffer->flags) == gpuInstance &&
(pNvLogBuffer->pos < pNvLogBuffer->size - NV_OFFSETOF(LIBOS_LOG_NVLOG_BUFFER, data) - sizeof(NvU64)))
//
// Cannot use nvlogGetBufferHandleFromTag here since in multi GPU case,
// we can have multiple buffers with exact same tag, only differentiable
// from gpuInstance
//
for (i = 0; i < NVLOG_MAX_BUFFERS; i++)
{
*pHandle = handle;
return NV_TRUE;
if (NvLogLogger.pBuffers[i] != NULL)
{
NVLOG_BUFFER *pNvLogBuffer = NvLogLogger.pBuffers[i];
if ((pNvLogBuffer->tag == tag) &&
(DRF_VAL(LOG, _BUFFER_FLAGS, _GPU_INSTANCE, pNvLogBuffer->flags) == gpuInstance) &&
FLD_TEST_DRF(LOG_BUFFER, _FLAGS, _PRESERVE, _YES, pNvLogBuffer->flags) &&
(pNvLogBuffer->pos < pNvLogBuffer->size - NV_OFFSETOF(LIBOS_LOG_NVLOG_BUFFER, data) - sizeof(NvU64)))
{
*pHandle = i;
return NV_TRUE;
}
}
}
return NV_FALSE;
@@ -2247,6 +2255,7 @@ void libosLogAddLogEx(LIBOS_LOG_DECODE *logDecode, void *buffer, NvU64 bufferSiz
);
NvLogLogger.pBuffers[pLog->hNvLogWrap]->pos = NV_OFFSETOF(LIBOS_LOG_NVLOG_BUFFER, data) + sizeof(NvU64); // offset to account for LIBOS buffer header and put pointer
}
else
{
@@ -2447,6 +2456,7 @@ void libosLogUpdateTimerDelta(LIBOS_LOG_DECODE *logDecode, NvU64 localToGlobalTi
pNoWrapBuf->localToGlobalTimerDelta = localToGlobalTimerDelta;
pWrapBuf->localToGlobalTimerDelta = localToGlobalTimerDelta;
#endif
logDecode->log[i].localToGlobalTimerDelta = localToGlobalTimerDelta;
}
src/nvidia-modeset/Makefile
+1
View File
@@ -54,6 +54,7 @@ CFLAGS += -D__NO_CTYPE
CFLAGS += -DNV_CPU_INTRINSICS_KERNEL
CFLAGS += -DNVHDMIPKT_RM_CALLS_INTERNAL=0
CFLAGS += -DNVHDMIPKT_NVKMS
# XXX it would be nice to only define these for appropriate files...
CFLAGS += -DSOFTFLOAT_ROUND_ODD
src/nvidia-modeset/include/dp/nvdp-connector.h
-2
View File
@@ -39,8 +39,6 @@ void nvDPNotifyShortPulse(NVDPLibConnectorPtr pNVDpLibConnector);
void nvDPDestroyConnector(NVDPLibConnectorPtr pNVDpLibConnector);
NvBool nvDPIsLinkAwaitingTransition(NVConnectorEvoPtr pConnectorEvo);
NVDPLibModesetStatePtr nvDPLibCreateModesetState(
const NVDispEvoRec *pDispEvo,
const NvU32 head,
src/nvidia-modeset/include/nvkms-event.h
+1
View File
@@ -28,5 +28,6 @@
void nvHandleHotplugEventDeferredWork(void *dataPtr, NvU32 dataU32);
void nvHandleDPIRQEventDeferredWork(void *dataPtr, NvU32 dataU32);
void nvHandleHDMIFRLRetrainEventDeferredWork(void *dataPtr, NvU32 dataU32);
#endif /* __NVKMS_EVENT_H__ */
src/nvidia-modeset/include/nvkms-hdmi.h
+14 -8
View File
@@ -61,14 +61,14 @@ void nvTeardownHdmiLibrary(NVDevEvoRec *pDevEvo);
NvBool nvHdmiFrlAssessLink(NVDpyEvoPtr pDpyEvo);
NvBool nvHdmiDpySupportsFrl(const NVDpyEvoRec *pDpyEvo);
NvBool nvHdmiFrlQueryConfig(const NVDpyEvoRec *pDpyEvo,
const NvModeTimings *pModeTimings,
const NVHwModeTimingsEvo *pHwTimings,
NVDpyAttributeColor *pDpyColor,
const NvBool b2Heads1Or,
const struct NvKmsModeValidationParams *pValidationParams,
HDMI_FRL_CONFIG *pConfig,
NVDscInfoEvoRec *pDscInfo);
NvBool nvHdmiFrlQueryConfigOneColorSpaceAndBpc(const NVDpyEvoRec *pDpyEvo,
const NvModeTimings *pModeTimings,
const NVHwModeTimingsEvo *pHwTimings,
const NVDpyAttributeColor *pDpyColor,
const NvBool b2Heads1Or,
const struct NvKmsModeValidationParams *pValidationParams,
HDMI_FRL_CONFIG *pConfig,
NVDscInfoEvoRec *pDscInfo);
void nvHdmiFrlClearConfig(NVDispEvoRec *pDispEvo, NvU32 activeRmId);
void nvHdmiFrlSetConfig(NVDispEvoRec *pDispEvo, NvU32 head);
@@ -80,6 +80,12 @@ NvBool nvHdmiIsTmdsPossible(const NVDpyEvoRec *pDpyEvo,
const NVHwModeTimingsEvo *pHwTimings,
const NVDpyAttributeColor *pDpyColor);
static inline NvBool nvHdmiIsFrlPossible(const NVDpyEvoRec *pDpyEvo)
{
return nvHdmiDpySupportsFrl(pDpyEvo) &&
(pDpyEvo->hdmi.sinkCaps.linkMaxFRLRate != HDMI_FRL_DATA_RATE_NONE);
}
static inline NvBool nvHdmiDpySupportsDsc(const NVDpyEvoRec *pDpyEvo)
{
return nvDpyIsHdmiEvo(pDpyEvo) &&
src/nvidia-modeset/include/nvkms-headsurface-priv.h
+2 -2
View File
@@ -277,7 +277,7 @@ typedef struct _NVHsChannelEvoRec {
*/
NVRgLine1CallbackPtr pRgIntrCallback;
#if NVKMS_PROCFS_ENABLE
#if NVKMS_HEADSURFACE_STATS
/*
* We track statistics differently for SwapGroup and non-SwapGroup
@@ -342,7 +342,7 @@ typedef struct _NVHsChannelEvoRec {
} statistics;
#else
#define NVKMS_HEADSURFACE_STATS_MAX_SEMAPHORES 0
#endif /* NVKMS_PROCFS_ENABLE */
#endif /* NVKMS_HEADSURFACE_STATS */
/*
* We need one semaphore for the non-stall interrupt following rendering to
src/nvidia-modeset/include/nvkms-headsurface.h
+1 -1
View File
@@ -123,7 +123,7 @@ NVSurfaceEvoRec *nvHsGetNvKmsSurface(const NVDevEvoRec *pDevEvo,
NvKmsSurfaceHandle surfaceHandle,
const NvBool requireDisplayHardwareAccess);
#if NVKMS_PROCFS_ENABLE
#if NVKMS_HEADSURFACE_STATS
void nvHsProcFs(
NVEvoInfoStringRec *pInfoString,
NVDevEvoRec *pDevEvo,
src/nvidia-modeset/include/nvkms-types.h
+12 -3
View File
@@ -66,9 +66,13 @@ extern "C" {
#include "nv_smg.h"
#if defined(DEBUG) || defined(DEVELOP)
#define NVKMS_PROCFS_ENABLE 1
#define NVKMS_HEADSURFACE_STATS 1
#define NVKMS_PROCFS_OBJECT_DUMP 1
#define NVKMS_PROCFS_CRCS 1
#else
#define NVKMS_PROCFS_ENABLE 0
#define NVKMS_HEADSURFACE_STATS 0
#define NVKMS_PROCFS_OBJECT_DUMP 0
#define NVKMS_PROCFS_CRCS 0
#endif
#define NV_DMA_EVO_PUSH_BUFFER_SIZE (4 * 1024)
@@ -2041,8 +2045,10 @@ typedef struct _NVDispEvoRec {
NVDevEvoPtr pDevEvo;
NvU32 hotplugEventHandle;
NvU32 DPIRQEventHandle;
NvU32 HDMIFRLRetrainEventHandle;
NVOS10_EVENT_KERNEL_CALLBACK_EX rmHotplugCallback;
NVOS10_EVENT_KERNEL_CALLBACK_EX rmDPIRQCallback;
NVOS10_EVENT_KERNEL_CALLBACK_EX rmHDMIFRLRetrainCallback;
NVDispHeadStateEvoRec headState[NVKMS_MAX_HEADS_PER_DISP];
NVDispApiHeadStateEvoRec apiHeadState[NVKMS_MAX_HEADS_PER_DISP];
@@ -2296,6 +2302,8 @@ typedef struct _NVDpyEvoRec {
struct {
HDMI_SRC_CAPS srcCaps;
HDMI_SINK_CAPS sinkCaps;
NvBool reassessFrlLinkCaps : 1;
} hdmi;
struct {
@@ -2831,7 +2839,7 @@ struct _NVSurfaceEvoRec {
NvU64 rmRefCnt;
NvU64 structRefCnt;
#if NVKMS_PROCFS_ENABLE
#if NVKMS_PROCFS_OBJECT_DUMP
NvBool procFsFlag;
#endif
@@ -3288,6 +3296,7 @@ typedef const struct _nv_evo_hal {
NvU32 supportsDPAudio192KHz :1;
NvU32 supportsInputColorSpace :1;
NvU32 supportsInputColorRange :1;
NvU32 supportsYCbCr422OverHDMIFRL :1;
NvU32 supportedDitheringModes;
size_t impStructSize;
src/nvidia-modeset/include/nvkms-utils.h
+1 -1
View File
@@ -279,7 +279,7 @@ void nvEvoDestroyApiHandles(NVEvoApiHandlesPtr pEvoApiHandles);
(_pointer) = nvEvoGetPointerFromApiHandleNext(_pEvoApiHandles, \
&(_handle)))
NvBool nvDoDebugLogging(void);
#ifdef __cplusplus
};
src/nvidia-modeset/interface/nvkms-api-types.h
+3 -1
View File
@@ -667,7 +667,9 @@ enum NvKmsInputTf {
enum NvKmsOutputColorimetry {
NVKMS_OUTPUT_COLORIMETRY_DEFAULT = 0,
NVKMS_OUTPUT_COLORIMETRY_BT2100 = 1,
NVKMS_OUTPUT_COLORIMETRY_BT601 = 1,
NVKMS_OUTPUT_COLORIMETRY_BT709 = 2,
NVKMS_OUTPUT_COLORIMETRY_BT2100 = 3,
};
enum NvKmsOutputTf {
src/nvidia-modeset/os-interface/include/nvidia-modeset-os-interface.h
+1
View File
@@ -119,6 +119,7 @@ NvBool nvkms_vblank_sem_control(void);
NvBool nvkms_opportunistic_display_sync(void);
enum NvKmsDebugForceColorSpace nvkms_debug_force_color_space(void);
NvBool nvkms_enable_overlay_layers(void);
NvBool nvkms_debug_logging(void);
void nvkms_call_rm (void *ops);
void* nvkms_alloc (size_t size,
src/nvidia-modeset/src/dp/nvdp-connector.cpp
+15 -54
View File
@@ -151,16 +151,6 @@ void nvDPDestroyConnector(NVDPLibConnectorPtr pNVDpLibConnector)
nvFree(pNVDpLibConnector);
}
NvBool nvDPIsLinkAwaitingTransition(NVConnectorEvoPtr pConnectorEvo)
{
if (nvConnectorUsesDPLib(pConnectorEvo)) {
DisplayPort::Connector *c = pConnectorEvo->pDpLibConnector->connector;
return c->isLinkAwaitingTransition();
}
return FALSE;
}
/*!
* Create a new DisplayPort group and populate it with the devices specified by
* dpyIdList. For MST groups, this allocates a dynamic RM display ID.
@@ -1128,10 +1118,11 @@ void nvDPSetAllowMultiStreamingOneConnector(
pDpLibConnector->connector->setAllowMultiStreaming(allowMST);
}
static NvBool IsDpSinkMstCapableForceSst(const NVDispEvoRec *pDispEvo,
const NvU32 apiHead,
void *pData)
static NvBool IsDpSinkMstTransitionNeeded(const NVDispEvoRec *pDispEvo,
const NvU32 apiHead,
void *pData)
{
const NvBool *pAllowMST = reinterpret_cast<const NvBool*>(pData);
const NVDispApiHeadStateEvoRec *pApiHeadState =
&pDispEvo->apiHeadState[apiHead];
const NVDpyEvoRec *pDpyEvo =
@@ -1147,49 +1138,24 @@ static NvBool IsDpSinkMstCapableForceSst(const NVDispEvoRec *pDispEvo,
DisplayPort::Connector *c =
pConnectorEvo->pDpLibConnector->connector;
return (c->getSinkMultiStreamCap() && !c->getAllowMultiStreaming());
}
return c->isLinkAwaitingTransition() ||
(c->getSinkMultiStreamCap() &&
c->getAllowMultiStreaming() != *pAllowMST);
static NvBool IsDpLinkTransitionWaitingForHeadShutDown(
const NVDispEvoRec *pDispEvo,
const NvU32 apiHead,
void *pData)
{
const NVDispApiHeadStateEvoRec *pApiHeadState =
&pDispEvo->apiHeadState[apiHead];
const NVDpyEvoRec *pDpyEvo =
nvGetOneArbitraryDpyEvo(pApiHeadState->activeDpys, pDispEvo);
return (pDpyEvo != NULL) &&
nvDPIsLinkAwaitingTransition(pDpyEvo->pConnectorEvo);
}
void nvDPSetAllowMultiStreaming(NVDevEvoPtr pDevEvo, NvBool allowMST)
{
NvBool needUpdate = FALSE;
NVDispEvoPtr pDispEvo;
NvU32 dispIndex;
FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) {
NVConnectorEvoPtr pConnectorEvo;
FOR_ALL_EVO_CONNECTORS(pConnectorEvo, pDispEvo) {
NVDPLibConnectorPtr pDpLibConnector =
pConnectorEvo->pDpLibConnector;
if (pDpLibConnector &&
pDpLibConnector->connector->getAllowMultiStreaming()
!= allowMST) {
needUpdate = TRUE;
}
}
}
if (!needUpdate) {
return;
}
/*
* Shut down any heads that are driving SST and need to transition to MST,
* and any heads where we're toggling the value of allowMST.
*/
nvShutDownApiHeads(pDevEvo, pDevEvo->pNvKmsOpenDev,
IsDpSinkMstCapableForceSst, NULL /* pData */,
IsDpSinkMstTransitionNeeded,
reinterpret_cast<void *>(&allowMST),
TRUE /* doRasterLock */);
/*
@@ -1214,15 +1180,10 @@ void nvDPSetAllowMultiStreaming(NVDevEvoPtr pDevEvo, NvBool allowMST)
}
}
/* Shut down all DisplayPort heads that need to transition to/from SST. */
nvShutDownApiHeads(pDevEvo, pDevEvo->pNvKmsOpenDev,
IsDpLinkTransitionWaitingForHeadShutDown,
NULL /* pData */,
TRUE /* doRasterLock */);
/*
* Handle any pending timers the DP library scheduled to notify us
* about changes in the connected device list.
* about changes to MST devices on connectors that now allow or disallow
* MST.
*/
nvDPFireExpiredTimers(pDevEvo);
}
src/nvidia-modeset/src/dp/nvdp-host.cpp
+2
View File
@@ -63,6 +63,8 @@ void dpPrintf(DP_LOG_LEVEL severity, const char *format, ...)
{
if (severity == DP_SILENT) return;
if (!nvDoDebugLogging()) return;
va_list ap;
va_start(ap, format);
nvVEvoLog(dpSeverityToNvkmsMap(severity), NV_INVALID_GPU_LOG_INDEX, format, ap);
src/nvidia-modeset/src/nvkms-attributes.c
+3 -12
View File
@@ -644,22 +644,13 @@ static void DpyPostColorSpaceOrRangeSetEvo(NVDpyEvoPtr pDpyEvo)
colorSpaceChanged = (pApiHeadState->attributes.color.format != colorSpace);
colorBpcChanged = (pApiHeadState->attributes.color.bpc != colorBpc);
/* For DP, neither color space nor bpc can be changed without a modeset */
if (nvConnectorUsesDPLib(pDpyEvo->pConnectorEvo) &&
/* For DP and HDMI FRL, neither color space nor bpc can be changed without a modeset */
if ((nvConnectorUsesDPLib(pDpyEvo->pConnectorEvo) ||
(pApiHeadState->timings.protocol == NVKMS_PROTOCOL_SOR_HDMI_FRL)) &&
(colorSpaceChanged || colorBpcChanged)) {
return;
}
/*
* Hardware does not support HDMI FRL with YUV422, and it is not possible
* to downgrade current color bpc on HDMI FRL at this point.
*/
if ((pApiHeadState->timings.protocol == NVKMS_PROTOCOL_SOR_HDMI_FRL) &&
((colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422) ||
(pApiHeadState->attributes.color.bpc > colorBpc))) {
return;
}
if (nvDpyIsHdmiEvo(pDpyEvo) &&
(colorBpc > pApiHeadState->attributes.color.bpc)) {
NVDpyAttributeColor tmpDpyColor = pApiHeadState->attributes.color;
src/nvidia-modeset/src/nvkms-dpy.c
+74 -42
View File
@@ -24,6 +24,7 @@
#include "dp/nvdp-device.h"
#include "dp/nvdp-connector-event-sink.h"
#include "nvkms-api-types.h"
#include "nvkms-evo.h"
#include "nvkms-dpy.h"
#include "nvkms-dpy-override.h"
@@ -44,6 +45,7 @@
#include "timing/dpsdp.h"
#include "displayport/displayport.h"
#include "timing/nvtiming.h"
#include <ctrl/ctrl0073/ctrl0073dfp.h> // NV0073_CTRL_DFP_FLAGS_*
#include <ctrl/ctrl0073/ctrl0073dp.h> // NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_*
@@ -100,23 +102,6 @@ static void DpyDisconnectEvo(NVDpyEvoPtr pDpyEvo, const NvBool bSendHdmiCapsToRm
ClearEdid(pDpyEvo, bSendHdmiCapsToRm);
}
static void HdmiFrlSetConfig(NVDpyEvoRec *pDpyEvo)
{
NVDispEvoRec *pDispEvo = pDpyEvo->pDispEvo;
NvU32 head;
if ((pDpyEvo->apiHead == NV_INVALID_HEAD) || !nvDpyIsHdmiEvo(pDpyEvo) ||
!nvHdmiDpySupportsFrl(pDpyEvo)) {
return;
}
head = nvGetPrimaryHwHead(pDispEvo, pDpyEvo->apiHead);
nvAssert(head != NV_INVALID_HEAD);
nvHdmiFrlSetConfig(pDispEvo, head);
}
static NvBool DpyConnectEvo(
NVDpyEvoPtr pDpyEvo,
struct NvKmsQueryDpyDynamicDataParams *pParams)
@@ -140,8 +125,6 @@ static NvBool DpyConnectEvo(
nvUpdateInfoFrames(pDpyEvo);
HdmiFrlSetConfig(pDpyEvo);
return TRUE;
}
@@ -682,7 +665,20 @@ static void ReadAndApplyEdidEvo(
&infoString);
} else {
nvFree(edid.buffer);
if (nvDpyIsHdmiEvo(pDpyEvo) &&
nvHdmiDpySupportsFrl(pDpyEvo) &&
pDpyEvo->hdmi.reassessFrlLinkCaps) {
/*
* Although there’s no change in EDID, if there was a HPD or
* re-training request, reassess the FRL Link.
*/
nvHdmiFrlAssessLink(pDpyEvo);
}
}
pDpyEvo->hdmi.reassessFrlLinkCaps = FALSE;
nvFree(pParsedEdid);
}
@@ -2593,6 +2589,8 @@ void nvConstructDpVscSdp(const NVDispHeadInfoFrameStateEvoRec *pInfoFrame,
sdp->db.colorimetryFormat =
SDP_VSC_COLOR_FMT_RGB_COLORIMETRY_ITU_R_BT2020_RGB;
break;
case NVKMS_OUTPUT_COLORIMETRY_BT601:
case NVKMS_OUTPUT_COLORIMETRY_BT709:
case NVKMS_OUTPUT_COLORIMETRY_DEFAULT:
sdp->db.colorimetryFormat =
SDP_VSC_COLOR_FMT_RGB_COLORIMETRY_SRGB;
@@ -2622,6 +2620,14 @@ void nvConstructDpVscSdp(const NVDispHeadInfoFrameStateEvoRec *pInfoFrame,
sdp->db.colorimetryFormat =
SDP_VSC_COLOR_FMT_YCBCR_COLORIMETRY_ITU_R_BT2020_YCBCR;
break;
case NVKMS_OUTPUT_COLORIMETRY_BT601:
sdp->db.colorimetryFormat =
SDP_VSC_COLOR_FMT_YCBCR_COLORIMETRY_ITU_R_BT601;
break;
case NVKMS_OUTPUT_COLORIMETRY_BT709:
sdp->db.colorimetryFormat =
SDP_VSC_COLOR_FMT_YCBCR_COLORIMETRY_ITU_R_BT709;
break;
case NVKMS_OUTPUT_COLORIMETRY_DEFAULT:
sdp->db.colorimetryFormat =
(pInfoFrame->hdTimings ?
@@ -2674,6 +2680,7 @@ static void UpdateDpVscSdpInfoFrame(
&pDispEvo->headState[head];
NV0073_CTRL_SPECIFIC_SET_OD_PACKET_PARAMS params = { 0 };
NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo;
DPSDP_DP_VSC_SDP_DESCRIPTOR *sdp;
NvU32 ret;
/*
@@ -2687,31 +2694,23 @@ static void UpdateDpVscSdpInfoFrame(
params.subDeviceInstance = pDispEvo->displayOwner;
params.displayId = pHeadState->activeRmId;
if ((pDpyColor->format == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr420) ||
(pDpyColor->colorimetry == NVKMS_OUTPUT_COLORIMETRY_BT2100)) {
// DPSDP_DP_VSC_SDP_DESCRIPTOR has a (dataSize, hb, db) layout, while
// NV0073_CTRL_SPECIFIC_SET_OD_PACKET_PARAMS.aPacket needs to contain
// (hb, db) without dataSize, so this makes sdp->hb align with aPacket.
sdp = (DPSDP_DP_VSC_SDP_DESCRIPTOR *)(params.aPacket -
offsetof(DPSDP_DP_VSC_SDP_DESCRIPTOR, hb));
// DPSDP_DP_VSC_SDP_DESCRIPTOR has a (dataSize, hb, db) layout, while
// NV0073_CTRL_SPECIFIC_SET_OD_PACKET_PARAMS.aPacket needs to contain
// (hb, db) without dataSize, so this makes sdp->hb align with aPacket.
DPSDP_DP_VSC_SDP_DESCRIPTOR *sdp =
(DPSDP_DP_VSC_SDP_DESCRIPTOR *)(params.aPacket -
offsetof(DPSDP_DP_VSC_SDP_DESCRIPTOR, hb));
nvAssert((void *)&sdp->hb == (void *)params.aPacket);
nvAssert((void *)&sdp->hb == (void *)params.aPacket);
nvConstructDpVscSdp(pInfoFrame, pDpyColor, sdp);
nvConstructDpVscSdp(pInfoFrame, pDpyColor, sdp);
params.packetSize = sizeof(sdp->hb) + sdp->hb.numValidDataBytes;
params.packetSize = sizeof(sdp->hb) + sdp->hb.numValidDataBytes;
params.transmitControl =
DRF_DEF(0073_CTRL_SPECIFIC, _SET_OD_PACKET_TRANSMIT_CONTROL, _ENABLE, _YES) |
DRF_DEF(0073_CTRL_SPECIFIC, _SET_OD_PACKET_TRANSMIT_CONTROL, _OTHER_FRAME, _DISABLE) |
DRF_DEF(0073_CTRL_SPECIFIC, _SET_OD_PACKET_TRANSMIT_CONTROL, _SINGLE_FRAME, _DISABLE) |
DRF_DEF(0073_CTRL_SPECIFIC, _SET_OD_PACKET_TRANSMIT_CONTROL, _ON_HBLANK, _DISABLE);
} else {
params.transmitControl =
DRF_DEF(0073_CTRL_SPECIFIC, _SET_OD_PACKET_TRANSMIT_CONTROL, _ENABLE, _NO);
}
params.transmitControl =
DRF_DEF(0073_CTRL_SPECIFIC, _SET_OD_PACKET_TRANSMIT_CONTROL, _ENABLE, _YES) |
DRF_DEF(0073_CTRL_SPECIFIC, _SET_OD_PACKET_TRANSMIT_CONTROL, _OTHER_FRAME, _DISABLE) |
DRF_DEF(0073_CTRL_SPECIFIC, _SET_OD_PACKET_TRANSMIT_CONTROL, _SINGLE_FRAME, _DISABLE) |
DRF_DEF(0073_CTRL_SPECIFIC, _SET_OD_PACKET_TRANSMIT_CONTROL, _ON_HBLANK, _DISABLE);
ret = nvRmApiControl(nvEvoGlobal.clientHandle,
pDevEvo->displayCommonHandle,
@@ -3360,10 +3359,10 @@ NvKmsDpyOutputColorFormatInfo nvDpyGetOutputColorFormatInfo(
NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8;
}
} else if (nvConnectorUsesDPLib(pDpyEvo->pConnectorEvo)) {
const NVT_EDID_INFO *info = &pDpyEvo->parsedEdid.info;
if (pDpyEvo->parsedEdid.valid &&
pDpyEvo->parsedEdid.info.input.isDigital &&
pDpyEvo->parsedEdid.info.version >= NVT_EDID_VER_1_4) {
info->input.isDigital && info->version >= NVT_EDID_VER_1_4) {
if (pDpyEvo->parsedEdid.info.input.u.digital.bpc >= 10) {
colorFormatsInfo.rgb444.maxBpc =
NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_10;
@@ -3407,6 +3406,39 @@ NvKmsDpyOutputColorFormatInfo nvDpyGetOutputColorFormatInfo(
colorFormatsInfo.rgb444.minBpc =
NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8;
}
if (pDpyEvo->parsedEdid.valid && info->input.isDigital &&
(info->input.u.digital.video_interface ==
NVT_EDID_DIGITAL_VIDEO_INTERFACE_STANDARD_HDMI_A_SUPPORTED ||
info->input.u.digital.video_interface ==
NVT_EDID_DIGITAL_VIDEO_INTERFACE_STANDARD_HDMI_B_SUPPORTED)) {
/*
* Prevent RGB 444 @ 6 BPC on active DP-to-HDMI adapters since
* HDMI does not support RGB 444 @ 6 BPC.
*/
if (colorFormatsInfo.rgb444.minBpc ==
NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_6) {
colorFormatsInfo.rgb444.minBpc =
NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8;
}
// Prevent >=10 BPC on active DP-to-HDMI adapters, if the dc_30_bit is not set
if ((info->version < NVT_EDID_VER_1_4 ||
!info->hdmiLlcInfo.dc_30_bit) &&
colorFormatsInfo.rgb444.maxBpc !=
NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_UNKNOWN) {
colorFormatsInfo.rgb444.maxBpc =
NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8;
}
if ((info->version < NVT_EDID_VER_1_4 ||
!info->hdmiLlcInfo.dc_30_bit) &&
colorFormatsInfo.yuv444.maxBpc !=
NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_UNKNOWN) {
colorFormatsInfo.yuv444.maxBpc =
NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8;
}
}
} else {
colorFormatsInfo.rgb444.maxBpc =
nvDpyIsHdmiDepth30Evo(pDpyEvo) ?
src/nvidia-modeset/src/nvkms-event.c
+16
View File
@@ -31,6 +31,7 @@
#include "nvkms-utils.h"
#include "nvkms-private.h"
#include "nvkms-evo.h"
#include "nvkms-hdmi.h"
/*
* Handle a display device hotplug event.
@@ -180,6 +181,10 @@ nvHandleHotplugEventDeferredWork(void *dataPtr, NvU32 dataU32)
} else {
nvSendDpyEventEvo(pDpyEvo, NVKMS_EVENT_TYPE_DPY_CHANGED);
}
if (nvDpyIsHdmiEvo(pDpyEvo)) {
pDpyEvo->hdmi.reassessFrlLinkCaps = TRUE;
}
}
}
@@ -205,3 +210,14 @@ nvHandleDPIRQEventDeferredWork(void *dataPtr, NvU32 dataU32)
}
}
}
void
nvHandleHDMIFRLRetrainEventDeferredWork(void *dataPtr, NvU32 dataU32)
{
NVDispEvoPtr pDispEvo = dataPtr;
NVDpyId id = nvNvU32ToDpyId(dataU32);
NVDpyEvoRec *pDpyEvo = nvGetDpyEvoFromDispEvo(pDispEvo, id);
nvSendDpyEventEvo(pDpyEvo, NVKMS_EVENT_TYPE_DPY_CHANGED);
pDpyEvo->hdmi.reassessFrlLinkCaps = TRUE;
}
src/nvidia-modeset/src/nvkms-evo.c
+37 -15
View File
@@ -1025,10 +1025,8 @@ void nvEvoSetDpVscSdp(NVDispEvoPtr pDispEvo,
nvPushEvoSubDevMaskDisp(pDispEvo);
if (((pDpyColor->format == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr420) ||
(pDpyColor->colorimetry == NVKMS_OUTPUT_COLORIMETRY_BT2100)) &&
((pTimings->protocol == NVKMS_PROTOCOL_SOR_DP_A) ||
(pTimings->protocol == NVKMS_PROTOCOL_SOR_DP_B))) {
if (pTimings->protocol == NVKMS_PROTOCOL_SOR_DP_A ||
pTimings->protocol == NVKMS_PROTOCOL_SOR_DP_B) {
DPSDP_DP_VSC_SDP_DESCRIPTOR sdp = { };
nvConstructDpVscSdp(pInfoFrame, pDpyColor, &sdp);
pDevEvo->hal->SetDpVscSdp(pDispEvo, head, &sdp, updateState);
@@ -3048,12 +3046,23 @@ void nvUpdateCurrentHardwareColorSpaceAndRangeEvo(
case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr444:
case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422:
case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr420:
if (pDpyColor->colorimetry == NVKMS_OUTPUT_COLORIMETRY_BT2100) {
switch (pDpyColor->colorimetry) {
case NVKMS_OUTPUT_COLORIMETRY_BT2100:
pHeadState->procAmp.colorimetry = NVT_COLORIMETRY_BT2020YCC;
} else if (nvEvoIsHDQualityVideoTimings(&pHeadState->timings)) {
break;
case NVKMS_OUTPUT_COLORIMETRY_BT709:
pHeadState->procAmp.colorimetry = NVT_COLORIMETRY_YUV_709;
} else {
break;
case NVKMS_OUTPUT_COLORIMETRY_BT601:
pHeadState->procAmp.colorimetry = NVT_COLORIMETRY_YUV_601;
break;
case NVKMS_OUTPUT_COLORIMETRY_DEFAULT:
if (nvEvoIsHDQualityVideoTimings(&pHeadState->timings)) {
pHeadState->procAmp.colorimetry = NVT_COLORIMETRY_YUV_709;
} else {
pHeadState->procAmp.colorimetry = NVT_COLORIMETRY_YUV_601;
}
break;
}
break;
default:
@@ -6867,10 +6876,19 @@ ConstructHwModeTimingsViewPort(const NVDispEvoRec *pDispEvo,
}
static NvBool GetDefaultFrlDpyColor(
static NvBool FrlOverrideForYCbCr422(
const NVDevEvoRec *pDevEvo,
const NvKmsDpyOutputColorFormatInfo *pColorFormatsInfo,
NVDpyAttributeColor *pDpyColor)
{
/*
* If the hardware natively supports YCbCr422 + FRL,
* there is nothing to do.
*/
if (pDevEvo->hal->caps.supportsYCbCr422OverHDMIFRL) {
return TRUE;
}
nvkms_memset(pDpyColor, 0, sizeof(*pDpyColor));
pDpyColor->colorimetry = NVKMS_OUTPUT_COLORIMETRY_DEFAULT;
@@ -6916,14 +6934,18 @@ static NvBool GetDfpHdmiProtocol(
NVKMS_MODE_VALIDATION_REQUIRE_BOOT_CLOCKS) == 0) &&
(!nvHdmiIsTmdsPossible(pDpyEvo, pTimings, pDpyColor) ||
nvGetPreferHdmiFrlMode(pDevEvo, pValidationParams)) &&
/* If FRL is supported... */
nvHdmiDpySupportsFrl(pDpyEvo)) {
/* If FRL is possible... */
nvHdmiIsFrlPossible(pDpyEvo)) {
/* Hardware does not support HDMI FRL with YUV422 */
if ((pDpyColor->format ==
NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422) &&
!GetDefaultFrlDpyColor(&colorFormatsInfo, pDpyColor)) {
return FALSE;
/*
* Not all hardware configurations support YCbCr422 with FRL;
* override if necessary, or fail FRL.
*/
if (pDpyColor->format ==
NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422) {
if (!FrlOverrideForYCbCr422(pDevEvo, &colorFormatsInfo, pDpyColor)) {
return FALSE;
}
}
*pTimingsProtocol = NVKMS_PROTOCOL_SOR_HDMI_FRL;
src/nvidia-modeset/src/nvkms-evo2.c
+2
View File
@@ -4098,6 +4098,7 @@ NVEvoHAL nvEvo97 = {
FALSE, /* supportsDPAudio192KHz */
FALSE, /* supportsInputColorSpace */
FALSE, /* supportsInputColorRange */
FALSE, /* supportsYCbCr422OverHDMIFRL */
NV_EVO2_SUPPORTED_DITHERING_MODES, /* supportedDitheringModes */
sizeof(NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS), /* impStructSize */
NV_EVO_SCALER_1TAP, /* minScalerTaps */
@@ -4196,6 +4197,7 @@ NVEvoHAL nvEvo94 = {
FALSE, /* supportsDPAudio192KHz */
FALSE, /* supportsInputColorSpace */
FALSE, /* supportsInputColorRange */
FALSE, /* supportsYCbCr422OverHDMIFRL */
NV_EVO2_SUPPORTED_DITHERING_MODES, /* supportedDitheringModes */
sizeof(NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS), /* impStructSize */
NV_EVO_SCALER_1TAP, /* minScalerTaps */
src/nvidia-modeset/src/nvkms-evo3.c
+3
View File
@@ -8146,6 +8146,7 @@ NVEvoHAL nvEvoC3 = {
FALSE, /* supportsDPAudio192KHz */
FALSE, /* supportsInputColorSpace */
FALSE, /* supportsInputColorRange */
FALSE, /* supportsYCbCr422OverHDMIFRL */
NV_EVO3_SUPPORTED_DITHERING_MODES, /* supportedDitheringModes */
sizeof(NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS), /* impStructSize */
NV_EVO_SCALER_2TAPS, /* minScalerTaps */
@@ -8244,6 +8245,7 @@ NVEvoHAL nvEvoC5 = {
FALSE, /* supportsDPAudio192KHz */
TRUE, /* supportsInputColorSpace */
TRUE, /* supportsInputColorRange */
FALSE, /* supportsYCbCr422OverHDMIFRL */
NV_EVO3_SUPPORTED_DITHERING_MODES, /* supportedDitheringModes */
sizeof(NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS), /* impStructSize */
NV_EVO_SCALER_2TAPS, /* minScalerTaps */
@@ -8342,6 +8344,7 @@ NVEvoHAL nvEvoC6 = {
FALSE, /* supportsDPAudio192KHz */
TRUE, /* supportsInputColorSpace */
TRUE, /* supportsInputColorRange */
FALSE, /* supportsYCbCr422OverHDMIFRL */
NV_EVO3_SUPPORTED_DITHERING_MODES, /* supportedDitheringModes */
sizeof(NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS), /* impStructSize */
NV_EVO_SCALER_2TAPS, /* minScalerTaps */
src/nvidia-modeset/src/nvkms-evo4.c
+2
View File
@@ -3140,6 +3140,7 @@ NVEvoHAL nvEvoC9 = {
TRUE, /* supportsDPAudio192KHz */
TRUE, /* supportsInputColorSpace */
TRUE, /* supportsInputColorRange */
TRUE, /* supportsYCbCr422OverHDMIFRL */
NV_EVO3_SUPPORTED_DITHERING_MODES, /* supportedDitheringModes */
sizeof(NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS), /* impStructSize */
NV_EVO_SCALER_2TAPS, /* minScalerTaps */
@@ -3238,6 +3239,7 @@ NVEvoHAL nvEvoCA = {
TRUE, /* supportsDPAudio192KHz */
TRUE, /* supportsInputColorSpace */
TRUE, /* supportsInputColorRange */
TRUE, /* supportsYCbCr422OverHDMIFRL */
NV_EVO3_SUPPORTED_DITHERING_MODES, /* supportedDitheringModes */
sizeof(NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS), /* impStructSize */
NV_EVO_SCALER_2TAPS, /* minScalerTaps */
src/nvidia-modeset/src/nvkms-hdmi.c
+150 -54
View File
@@ -51,6 +51,19 @@
#define CAP_HDMI_SUPPORT_MONITOR_36_BPP 0x00000008
#define CAP_HDMI_SUPPORT_MONITOR_30_BPP 0x00000010
#define SRC_TEST_CONFIG_DSC_FRL_MAX_OFFSET 6
#define SRC_TEST_CONFIG_FRL_MAX_OFFSET 7
typedef enum {
FORCE_NONE,
FORCE_MAX_FRL_RATE,
FORCE_MAX_DSC_FRL_RATE,
} NVForceMaxFrlRateType;
static NVForceMaxFrlRateType GetForceMaxFrlRateType(
const NVDpyEvoRec *pDpyEvo,
const NVDpyId displayId);
static inline const NVT_EDID_CEA861_INFO *GetExt861(const NVParsedEdidEvoRec *pParsedEdid,
int extIndex)
{
@@ -102,6 +115,8 @@ static void CalculateVideoInfoFrameColorFormat(
pCtrl->extended_colorimetry =
NVT_VIDEO_INFOFRAME_BYTE3_EC_BT2020RGBYCC;
break;
case NVKMS_OUTPUT_COLORIMETRY_BT601:
case NVKMS_OUTPUT_COLORIMETRY_BT709:
case NVKMS_OUTPUT_COLORIMETRY_DEFAULT:
pCtrl->colorimetry = NVT_VIDEO_INFOFRAME_BYTE2_C1C0_NO_DATA;
break;
@@ -115,6 +130,12 @@ static void CalculateVideoInfoFrameColorFormat(
pCtrl->extended_colorimetry =
NVT_VIDEO_INFOFRAME_BYTE3_EC_BT2020RGBYCC;
break;
case NVKMS_OUTPUT_COLORIMETRY_BT601:
pCtrl->colorimetry = NVT_VIDEO_INFOFRAME_BYTE2_C1C0_SMPTE170M_ITU601;
break;
case NVKMS_OUTPUT_COLORIMETRY_BT709:
pCtrl->colorimetry = NVT_VIDEO_INFOFRAME_BYTE2_C1C0_ITU709;
break;
case NVKMS_OUTPUT_COLORIMETRY_DEFAULT:
pCtrl->colorimetry =
(hdTimings ? NVT_VIDEO_INFOFRAME_BYTE2_C1C0_ITU709 :
@@ -1869,11 +1890,13 @@ static void HdmiLibPrint(
{
NVDevEvoRec *pDevEvo = handle;
if (!nvDoDebugLogging()) return;
va_list ap;
va_start(ap, format);
/* The HDMI library doesn't have log levels, but currently only logs in
* debug builds. It's pretty chatty (e.g., it prints "Initialize Success"
* when it inits), so hardcode it to INFO level for now. */
/* The HDMI library doesn't have log levels. It's pretty chatty (e.g., it
* prints "Initialize Success" when it inits), so hardcode it to INFO level
* for now. */
nvVEvoLog(EVO_LOG_INFO, pDevEvo->gpuLogIndex, format, ap);
va_end(ap);
}
@@ -1962,19 +1985,40 @@ NvBool nvHdmiFrlAssessLink(NVDpyEvoPtr pDpyEvo)
NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo;
NVHDMIPKT_RESULT ret;
const NvU32 displayId = nvDpyIdToNvU32(pDpyEvo->pConnectorEvo->displayId);
NvBool bIsDisplayActive = NV_FALSE;
NvBool bPerformLinkTrainingToAssess = NV_TRUE;
HDMI_FRL_DATA_RATE currFRLRate = HDMI_FRL_DATA_RATE_NONE;
nvAssert(nvDpyIsHdmiEvo(pDpyEvo));
nvAssert(nvDpyIsHdmiEvo(pDpyEvo) && nvHdmiDpySupportsFrl(pDpyEvo));
if (pDpyEvo->apiHead != NV_INVALID_HEAD) {
const NvU32 head =
nvGetPrimaryHwHead(pDispEvo, pDpyEvo->apiHead);
const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head];
const HDMI_FRL_CONFIG *pFrlConfig = &pHeadState->hdmiFrlConfig;
bIsDisplayActive = NV_TRUE;
if (pFrlConfig->frlRate == HDMI_FRL_DATA_RATE_NONE) {
bPerformLinkTrainingToAssess = NV_FALSE;
} else {
bPerformLinkTrainingToAssess = NV_TRUE;
}
currFRLRate = pFrlConfig->frlRate;
}
/* HDMI dpys not dynamic dpy so its connector should have a dpyId. */
nvAssert(displayId != 0);
nvAssert(pDpyEvo->parsedEdid.valid);
ret = NvHdmi_AssessLinkCapabilities(pDevEvo->hdmiLib.handle,
pDispEvo->displayOwner,
displayId,
&pDpyEvo->parsedEdid.info,
&pDpyEvo->hdmi.srcCaps,
&pDpyEvo->hdmi.sinkCaps);
ret = NvHdmi_AssessLinkCapabilities2(pDevEvo->hdmiLib.handle,
pDispEvo->displayOwner,
displayId,
&pDpyEvo->parsedEdid.info,
bPerformLinkTrainingToAssess,
bIsDisplayActive,
currFRLRate,
&pDpyEvo->hdmi.srcCaps,
&pDpyEvo->hdmi.sinkCaps);
if (ret != NVHDMIPKT_SUCCESS) {
nvAssert(ret == NVHDMIPKT_SUCCESS);
return FALSE;
@@ -2120,7 +2164,7 @@ static NvU64 GetHdmiFrlLinkRate(HDMI_FRL_DATA_RATE frlRate)
return hdmiLinkRate;
}
static NvBool nvHdmiFrlQueryConfigOneBpc(
NvBool nvHdmiFrlQueryConfigOneColorSpaceAndBpc(
const NVDpyEvoRec *pDpyEvo,
const NvModeTimings *pModeTimings,
const NVHwModeTimingsEvo *pHwTimings,
@@ -2130,8 +2174,11 @@ static NvBool nvHdmiFrlQueryConfigOneBpc(
HDMI_FRL_CONFIG *pConfig,
NVDscInfoEvoRec *pDscInfo)
{
const NVConnectorEvoRec *pConnectorEvo = pDpyEvo->pConnectorEvo;
const NVDispEvoRec *pDispEvo = pDpyEvo->pDispEvo;
const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo;
const NVForceMaxFrlRateType forceMaxFrlType =
GetForceMaxFrlRateType(pDpyEvo, pConnectorEvo->displayId);
HDMI_VIDEO_TRANSPORT_INFO videoTransportInfo = { };
HDMI_QUERY_FRL_CLIENT_CONTROL clientControl = { };
const NVT_TIMING *pNvtTiming;
@@ -2145,7 +2192,7 @@ static NvBool nvHdmiFrlQueryConfigOneBpc(
}
nvAssert(nvDpyIsHdmiEvo(pDpyEvo));
nvAssert(nvHdmiDpySupportsFrl(pDpyEvo));
nvAssert(nvHdmiIsFrlPossible(pDpyEvo));
nvAssert(!nvHdmiIsTmdsPossible(pDpyEvo, pHwTimings, pDpyColor) ||
nvGetPreferHdmiFrlMode(pDevEvo, pValidationParams));
@@ -2202,21 +2249,32 @@ static NvBool nvHdmiFrlQueryConfigOneBpc(
return FALSE;
}
/* TODO: support YUV/YCbCr 444 and 422 packing modes. */
switch (pModeTimings->yuv420Mode) {
case NV_YUV420_MODE_NONE:
switch (pDpyColor->format) {
case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB:
videoTransportInfo.packing = HDMI_PIXEL_PACKING_RGB;
break;
case NV_YUV420_MODE_SW:
/*
* Don't bother implementing this with FRL.
* HDMI FRL and HW YUV420 support were both added in nvdisplay 4.0
* hardware, so if the hardware supports FRL it should support
* YUV420_MODE_HW.
*/
return FALSE;
case NV_YUV420_MODE_HW:
videoTransportInfo.packing = HDMI_PIXEL_PACKING_YCbCr420;
case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422:
nvAssert(pDevEvo->hal->caps.supportsYCbCr422OverHDMIFRL);
videoTransportInfo.packing = HDMI_PIXEL_PACKING_YCbCr422;
break;
case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr444:
videoTransportInfo.packing = HDMI_PIXEL_PACKING_YCbCr444;
break;
case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr420:
switch (pModeTimings->yuv420Mode) {
case NV_YUV420_MODE_NONE:
case NV_YUV420_MODE_SW:
/*
* Don't bother implementing this with FRL.
* HDMI FRL and HW YUV420 support were both added in nvdisplay 4.0
* hardware, so if the hardware supports FRL it should support
* YUV420_MODE_HW.
*/
return FALSE;
case NV_YUV420_MODE_HW:
videoTransportInfo.packing = HDMI_PIXEL_PACKING_YCbCr420;
break;
}
break;
}
@@ -2224,8 +2282,32 @@ static NvBool nvHdmiFrlQueryConfigOneBpc(
clientControl.option = HDMI_QUERY_FRL_HIGHEST_PIXEL_QUALITY;
if (pValidationParams->dscMode == NVKMS_DSC_MODE_FORCE_ENABLE) {
clientControl.enableDSC = TRUE;
switch (pValidationParams->dscMode) {
case NVKMS_DSC_MODE_FORCE_DISABLE:
clientControl.forceDisableDSC = TRUE;
break;
case NVKMS_DSC_MODE_FORCE_ENABLE:
clientControl.enableDSC = TRUE;
break;
case NVKMS_DSC_MODE_DEFAULT:
clientControl.forceFRLRate = (forceMaxFrlType != FORCE_NONE);
switch (forceMaxFrlType) {
case FORCE_MAX_FRL_RATE:
clientControl.forceDisableDSC = TRUE;
clientControl.frlRate =
NV_MIN(pDpyEvo->hdmi.srcCaps.linkMaxFRLRate,
pDpyEvo->hdmi.sinkCaps.linkMaxFRLRate);
break;
case FORCE_MAX_DSC_FRL_RATE:
clientControl.enableDSC = TRUE;
clientControl.frlRate =
NV_MIN(pDpyEvo->hdmi.srcCaps.linkMaxFRLRate,
pDpyEvo->hdmi.sinkCaps.linkMaxFRLRateDSC);
break;
case FORCE_NONE:
break;
}
break;
}
/*
@@ -2233,7 +2315,7 @@ static NvBool nvHdmiFrlQueryConfigOneBpc(
* but YUV420 is not, force DSC.
*/
if (b2Heads1Or && (pHwTimings->yuv420Mode != NV_YUV420_MODE_HW)) {
if (pValidationParams->dscMode == NVKMS_DSC_MODE_FORCE_DISABLE) {
if (clientControl.forceDisableDSC) {
return FALSE;
}
clientControl.enableDSC = TRUE;
@@ -2334,34 +2416,48 @@ void nvHdmiFrlClearConfig(NVDispEvoRec *pDispEvo, NvU32 activeRmId)
}
}
NvBool nvHdmiFrlQueryConfig(
static NVForceMaxFrlRateType GetForceMaxFrlRateType(
const NVDpyEvoRec *pDpyEvo,
const NvModeTimings *pModeTimings,
const NVHwModeTimingsEvo *pHwTimings,
NVDpyAttributeColor *pDpyColor,
const NvBool b2Heads1Or,
const struct NvKmsModeValidationParams *pValidationParams,
HDMI_FRL_CONFIG *pConfig,
NVDscInfoEvoRec *pDscInfo)
const NVDpyId displayId)
{
const NvKmsDpyOutputColorFormatInfo supportedColorFormats =
nvDpyGetOutputColorFormatInfo(pDpyEvo);
NVDpyAttributeColor dpyColor = *pDpyColor;
do {
if (nvHdmiFrlQueryConfigOneBpc(pDpyEvo,
pModeTimings,
pHwTimings,
&dpyColor,
b2Heads1Or,
pValidationParams,
pConfig,
pDscInfo)) {
*pDpyColor = dpyColor;
return TRUE;
}
} while(nvDowngradeColorBpc(&supportedColorFormats, &dpyColor) &&
(dpyColor.bpc >= NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8));
return FALSE;
const NVDispEvoRec *pDispEvo = pDpyEvo->pDispEvo;
const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo;
const NVParsedEdidEvoRec *pParsedEdid = &pDpyEvo->parsedEdid;
const NVT_HDMI_FORUM_INFO *pHdmiInfo = &pParsedEdid->info.hdmiForumInfo;
NvBool bTestMaxFrlRate;
NvBool bTestMaxDscFrlRate;
NvU32 ret;
if (!pHdmiInfo->scdc_present) {
return FORCE_NONE;
}
NV0073_CTRL_SPECIFIC_GET_HDMI_SCDC_DATA_PARAMS scdcParams;
nvkms_memset(&scdcParams, 0, sizeof(scdcParams));
scdcParams.subDeviceInstance = 0;
scdcParams.displayId = nvDpyIdToNvU32(displayId);
scdcParams.offset = NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_SOURCE_TEST_CONFIGURATION;
ret = nvRmApiControl(nvEvoGlobal.clientHandle,
pDevEvo->displayCommonHandle,
NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA,
&scdcParams,
sizeof(scdcParams));
if (ret != NVOS_STATUS_SUCCESS) {
return FORCE_NONE;
}
bTestMaxFrlRate = !!(scdcParams.data & NVBIT(SRC_TEST_CONFIG_FRL_MAX_OFFSET));
bTestMaxDscFrlRate = !!(scdcParams.data & NVBIT(SRC_TEST_CONFIG_DSC_FRL_MAX_OFFSET));
if (bTestMaxFrlRate != bTestMaxDscFrlRate) {
return bTestMaxFrlRate ? FORCE_MAX_FRL_RATE : FORCE_MAX_DSC_FRL_RATE;
}
return FORCE_NONE;
}
void nvHdmiFrlSetConfig(NVDispEvoRec *pDispEvo, NvU32 head)
src/nvidia-modeset/src/nvkms-headsurface-3d.c
+6 -6
View File
@@ -1257,7 +1257,7 @@ static inline NvGpuSemaphore *Hs3dGetSemaphore(
return (NvGpuSemaphore *) pNotifier;
}
#if NVKMS_PROCFS_ENABLE
#if NVKMS_HEADSURFACE_STATS
/*!
* Get the semaphore index (e.g., to be passed into
* nvPushGetNotifierGpuAddress()) for an (eye, slot) pair.
@@ -1358,7 +1358,7 @@ static void Hs3dStatisticsComputeFps(
}
}
#endif /* NVKMS_PROCFS_ENABLE */
#endif /* NVKMS_HEADSURFACE_STATS */
/*!
* Collect statistics on headSurface rendering.
@@ -1380,7 +1380,7 @@ static void Hs3dStatisticsBefore(
const NvU8 eye,
const NvU8 slot)
{
#if NVKMS_PROCFS_ENABLE
#if NVKMS_HEADSURFACE_STATS
NVHsChannelStatisticsOneEyeRec *pPerEye =
&pHsChannel->statistics.perEye[eye][slot];
@@ -1438,7 +1438,7 @@ done:
semIndex + NVKMS_HEADSURFACE_STATS_SEMAPHORE_BEFORE,
pPerEye->nFrames);
#endif /* NVKMS_PROCFS_ENABLE */
#endif /* NVKMS_HEADSURFACE_STATS */
}
static void Hs3dStatisticsAfter(
@@ -1446,7 +1446,7 @@ static void Hs3dStatisticsAfter(
const NvU8 eye,
const NvU8 slot)
{
#if NVKMS_PROCFS_ENABLE
#if NVKMS_HEADSURFACE_STATS
NVHsChannelStatisticsOneEyeRec *pPerEye =
&pHsChannel->statistics.perEye[eye][slot];
const NvU8 semIndex = Hs3dGetStatisticsSemaphoreIndex(eye, slot);
@@ -1458,7 +1458,7 @@ static void Hs3dStatisticsAfter(
pPerEye->nFrames++;
#endif /* NVKMS_PROCFS_ENABLE */
#endif /* NVKMS_HEADSURFACE_STATS */
}
/*!
src/nvidia-modeset/src/nvkms-headsurface.c
+12 -12
View File
@@ -1866,7 +1866,7 @@ static void HsProcFsRecordScanline(
const NVDispEvoRec *pDispEvo,
const NvU32 apiHead)
{
#if NVKMS_PROCFS_ENABLE
#if NVKMS_HEADSURFACE_STATS
NVHsChannelEvoRec *pHsChannel = pDispEvo->pHsChannel[apiHead];
NvU16 scanLine = 0;
NvBool inBlankingPeriod = FALSE;
@@ -1890,13 +1890,13 @@ static void HsProcFsRecordScanline(
scanLine, pHsChannel->statistics.scanLine.vVisible);
}
}
#endif /* NVKMS_PROCFS_ENABLE */
#endif /* NVKMS_HEADSURFACE_STATS */
}
static void HsProcFsRecordPreviousFrameNotDone(
NVHsChannelEvoPtr pHsChannel)
{
#if NVKMS_PROCFS_ENABLE
#if NVKMS_HEADSURFACE_STATS
pHsChannel->statistics.nPreviousFrameNotDone++;
#endif
}
@@ -1905,19 +1905,19 @@ static void HsProcFsRecordFullscreenSgFrames(
NVHsChannelEvoPtr pHsChannel,
NvBool isFullscreen)
{
#if NVKMS_PROCFS_ENABLE
#if NVKMS_HEADSURFACE_STATS
if (isFullscreen) {
pHsChannel->statistics.nFullscreenSgFrames++;
} else {
pHsChannel->statistics.nNonFullscreenSgFrames++;
}
#endif /* NVKMS_PROCFS_ENABLE */
#endif /* NVKMS_HEADSURFACE_STATS */
}
static void HsProcFsRecordOmittedNonSgHsUpdate(
NVHsChannelEvoPtr pHsChannel)
{
#if NVKMS_PROCFS_ENABLE
#if NVKMS_HEADSURFACE_STATS
pHsChannel->statistics.nOmittedNonSgHsUpdates++;
#endif
}
@@ -2416,7 +2416,7 @@ void nvHsRemoveVBlankCallback(NVHsChannelEvoPtr pHsChannel)
void nvHsAllocStatistics(
NVHsChannelEvoRec *pHsChannel)
{
#if NVKMS_PROCFS_ENABLE
#if NVKMS_HEADSURFACE_STATS
const NVDispEvoRec *pDispEvo = pHsChannel->pDispEvo;
const NvU32 apiHead = pHsChannel->apiHead;
const NVHwModeTimingsEvo *pTimings =
@@ -2430,19 +2430,19 @@ void nvHsAllocStatistics(
n = pHsChannel->statistics.scanLine.vVisible + 1;
pHsChannel->statistics.scanLine.pHistogram = nvCalloc(1, sizeof(NvU64) * n);
#endif /* NVKMS_PROCFS_ENABLE */
#endif /* NVKMS_HEADSURFACE_STATS */
}
void nvHsFreeStatistics(
NVHsChannelEvoRec *pHsChannel)
{
#if NVKMS_PROCFS_ENABLE
#if NVKMS_HEADSURFACE_STATS
nvFree(pHsChannel->statistics.scanLine.pHistogram);
nvkms_memset(&pHsChannel->statistics, 0, sizeof(pHsChannel->statistics));
#endif /* NVKMS_PROCFS_ENABLE */
#endif /* NVKMS_HEADSURFACE_STATS */
}
#if NVKMS_PROCFS_ENABLE
#if NVKMS_HEADSURFACE_STATS
static const struct {
const char *before;
@@ -2972,4 +2972,4 @@ void nvHsProcFs(
HsProcFsScanLine(pInfoString, pHsChannel);
}
#endif /* NVKMS_PROCFS_ENABLE */
#endif /* NVKMS_HEADSURFACE_STATS */
src/nvidia-modeset/src/nvkms-modepool.c
+17 -8
View File
@@ -1714,18 +1714,27 @@ static NvBool ValidateMode(NVDpyEvoPtr pDpyEvo,
b2Heads1Or = nvEvoUse2Heads1OR(pDpyEvo, pTimingsEvo, pParams);
if (nvDpyIsHdmiEvo(pDpyEvo)) {
if (!nvHdmiFrlQueryConfig(pDpyEvo,
&pKmsMode->timings,
pTimingsEvo,
&dpyColor,
b2Heads1Or,
pParams,
pHdmiFrlConfig,
pDscInfo)) {
NvBool foundFrlConfig = FALSE;
do {
if (nvHdmiFrlQueryConfigOneColorSpaceAndBpc(pDpyEvo,
&pKmsMode->timings,
pTimingsEvo,
&dpyColor,
b2Heads1Or,
pParams,
pHdmiFrlConfig,
pDscInfo)) {
foundFrlConfig = TRUE;
break;
}
} while (nvDowngradeColorSpaceAndBpc(pDpyEvo, &supportedColorFormats, &dpyColor));
if (!foundFrlConfig) {
LogModeValidationEnd(pDispEvo, pInfoString,
"Unable to determine HDMI 2.1 Fixed Rate Link configuration.");
goto done;
}
} else {
if (!nvDPValidateModeEvo(pDpyEvo, pTimingsEvo, &dpyColor, b2Heads1Or,
pDscInfo, pParams)) {
src/nvidia-modeset/src/nvkms-modeset.c
+38 -9
View File
@@ -102,6 +102,14 @@
#include "nvkms-attributes.h"
#include "nvkms-headsurface-config.h"
static NvBool
AssignProposedHdmiFrlConfig(
NVProposedModeSetStateOneApiHead *pProposedApiHead,
NVProposedModeSetHwStateOneHead *pProposedPrimaryHead,
const struct NvKmsSetModeOneHeadRequest *pRequestHead,
const NVDispEvoRec *pDispEvo,
const NVDpyEvoRec *pDpyEvo);
static NvBool
GetColorSpaceAndColorRange(
const NVDispEvoRec *pDispEvo,
@@ -1367,15 +1375,11 @@ AssignProposedModeSetHwState(NVDevEvoRec *pDevEvo,
* proposed modeset state, to broadcast it onto all hardware heads
* during modeset.
*/
if (!nvHdmiFrlQueryConfig(pDpyEvo,
&pRequestHead->mode.timings,
&pProposedApiHead->timings,
&pProposedApiHead->attributes.color,
(nvPopCount32(pProposedApiHead->hwHeadsMask) > 1)
/* b2Heads1Or */,
&pProposedApiHead->modeValidationParams,
&pProposedPrimaryHead->hdmiFrlConfig,
&pProposedApiHead->dscInfo)) {
if (!AssignProposedHdmiFrlConfig(pProposedApiHead,
pProposedPrimaryHead,
pRequestHead,
pDispEvo,
pDpyEvo)) {
pReply->disp[sd].head[apiHead].status =
NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_MODE;
ret = FALSE;
@@ -1763,6 +1767,31 @@ static NvBool DowngradeColorSpaceAndBpcOneConnectorEvo(
return FALSE;
}
static NvBool AssignProposedHdmiFrlConfig(
NVProposedModeSetStateOneApiHead *pProposedApiHead,
NVProposedModeSetHwStateOneHead *pProposedPrimaryHead,
const struct NvKmsSetModeOneHeadRequest *pRequestHead,
const NVDispEvoRec *pDispEvo,
const NVDpyEvoRec *pDpyEvo)
{
do {
if (nvHdmiFrlQueryConfigOneColorSpaceAndBpc(pDpyEvo,
&pRequestHead->mode.timings,
&pProposedApiHead->timings,
&pProposedApiHead->attributes.color,
(nvPopCount32(pProposedApiHead->hwHeadsMask) > 1)
/* b2Heads1Or */,
&pProposedApiHead->modeValidationParams,
&pProposedPrimaryHead->hdmiFrlConfig,
&pProposedApiHead->dscInfo)) {
return TRUE;
}
} while (DowngradeColorSpaceAndBpcOneHead(pDispEvo, pProposedApiHead));
return FALSE;
}
static NvBool ValidateProposedModeSetHwStateOneConnectorDPlib(
const NVConnectorEvoRec *pConnectorEvo,
NVProposedModeSetHwStateOneDisp *pProposedDisp,
src/nvidia-modeset/src/nvkms-rm.c
+68 -1
View File
@@ -1584,6 +1584,19 @@ static void ReceiveDPIRQEvent(void *arg, void *pEventDataVoid, NvU32 hEvent,
0);
}
static void ReceiveHDMIFRLRetrainEvent(void *arg, void *pEventDataVoid, NvU32 hEvent,
NvU32 Data, NV_STATUS Status)
{
Nv2080HdmiFrlRequestNotification *pEventData =
(Nv2080HdmiFrlRequestNotification *) pEventDataVoid;
(void) nvkms_alloc_timer_with_ref_ptr(
nvHandleHDMIFRLRetrainEventDeferredWork, /* callback */
arg, /* argument (this is a ref_ptr to a pDispEvo) */
pEventData->displayId, /* dataU32 */
0);
}
NvBool nvRmRegisterCallback(const NVDevEvoRec *pDevEvo,
NVOS10_EVENT_KERNEL_CALLBACK_EX *cb,
struct nvkms_ref_ptr *ref_ptr,
@@ -1820,6 +1833,35 @@ enum NvKmsAllocDeviceStatus nvRmAllocDisplays(NVDevEvoPtr pDevEvo)
}
}
// Allocate a handler for the HDMI "FRL Retraining" event, which is signaled
// when there's a FRL retraining request from the sink.
FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) {
NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS setEventParams = { };
NvU32 subDevice, ret;
subDevice = pDevEvo->pSubDevices[pDispEvo->displayOwner]->handle;
pDispEvo->HDMIFRLRetrainEventHandle =
nvGenerateUnixRmHandle(&pDevEvo->handleAllocator);
if (!RegisterDispCallback(&pDispEvo->rmHDMIFRLRetrainCallback, pDispEvo,
pDispEvo->HDMIFRLRetrainEventHandle, ReceiveHDMIFRLRetrainEvent,
NV2080_NOTIFIERS_HDMI_FRL_RETRAINING_REQUEST)) {
nvEvoLogDev(pDevEvo, EVO_LOG_WARN,
"Failed to register HDMI FRL retrain event");
}
// Enable HDMI FRL retrain event notifications for this subdevice.
setEventParams.event = NV2080_NOTIFIERS_HDMI_FRL_RETRAINING_REQUEST;
setEventParams.action = NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT;
if ((ret = nvRmApiControl(nvEvoGlobal.clientHandle,
subDevice,
NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION,
&setEventParams,
sizeof(setEventParams)))
!= NVOS_STATUS_SUCCESS) {
nvEvoLogDev(pDevEvo, EVO_LOG_WARN,
"Failed to enable HDMI FRL retrain notifications (subdevice: %d) (error: 0x%x)", sd, ret);
}
}
FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) {
ProbeBootDisplays(pDispEvo);
@@ -1850,7 +1892,7 @@ void nvRmDestroyDisplays(NVDevEvoPtr pDevEvo)
nvFreeVrrEvo(pDevEvo);
FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) {
const NvU32 subDevice = pDevEvo->pSubDevices[pDispEvo->displayOwner]->handle;
// Before freeing anything, dump anything left in the RM's DisplayPort
// AUX channel log.
if (pDispEvo->dpAuxLoggingEnabled) {
@@ -1882,6 +1924,31 @@ void nvRmDestroyDisplays(NVDevEvoPtr pDevEvo)
pDispEvo->hotplugEventHandle);
pDispEvo->hotplugEventHandle = 0;
}
// Free the HDMI FRL retrain event
if (pDispEvo->HDMIFRLRetrainEventHandle != 0) {
NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS setEventParams = { };
// Disable HDMI FRL retrain notifications for this subdevice
setEventParams.event = NV2080_NOTIFIERS_HDMI_FRL_RETRAINING_REQUEST;
setEventParams.action = NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE;
if ((ret = nvRmApiControl(nvEvoGlobal.clientHandle,
subDevice,
NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION,
&setEventParams,
sizeof(setEventParams))
!= NVOS_STATUS_SUCCESS)) {
nvEvoLogDev(pDevEvo, EVO_LOG_WARN,
"Failed to disable HDMI FRL retrain notifications (subdevice: %d) (error: 0x%x)", dispIndex, ret);
}
nvRmApiFree(nvEvoGlobal.clientHandle,
nvEvoGlobal.clientHandle,
pDispEvo->HDMIFRLRetrainEventHandle);
nvFreeUnixRmHandle(&pDevEvo->handleAllocator,
pDispEvo->HDMIFRLRetrainEventHandle);
pDispEvo->HDMIFRLRetrainEventHandle = 0;
}
}
FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) {
src/nvidia-modeset/src/nvkms-utils.c
+11
View File
@@ -801,3 +801,14 @@ void nvDebugAssert(const char *expString, const char *filenameString,
}
#endif /* DEBUG */
NvBool nvDoDebugLogging(void)
{
#if defined(DEBUG)
/* Always do debug logging in debug builds. */
return TRUE;
#endif
/* Otherwise, do debug logging if the kernel module is enabled. */
return nvkms_debug_logging();
}
src/nvidia-modeset/src/nvkms.c
+191 -72
View File
@@ -5345,7 +5345,7 @@ fail:
extern const char *const pNV_KMS_ID;
#if NVKMS_PROCFS_ENABLE
#if NVKMS_PROCFS_OBJECT_DUMP
static const char *ProcFsPerOpenTypeString(
enum NvKmsPerOpenType type)
@@ -5713,44 +5713,6 @@ ProcFsPrintSurfaces(
}
}
static void
ProcFsPrintHeadSurface(
void *data,
char *buffer,
size_t size,
nvkms_procfs_out_string_func_t *outString)
{
NVDevEvoPtr pDevEvo;
NVDispEvoPtr pDispEvo;
NvU32 dispIndex, apiHead;
NVEvoInfoStringRec infoString;
FOR_ALL_EVO_DEVS(pDevEvo) {
nvInitInfoString(&infoString, buffer, size);
nvEvoLogInfoString(&infoString,
"pDevEvo (deviceId:%02d) : %p",
pDevEvo->deviceId.rmDeviceId, pDevEvo);
outString(data, buffer);
FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) {
nvInitInfoString(&infoString, buffer, size);
nvEvoLogInfoString(&infoString,
" pDispEvo (dispIndex:%02d) : %p",
dispIndex, pDispEvo);
outString(data, buffer);
for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) {
nvInitInfoString(&infoString, buffer, size);
nvHsProcFs(&infoString, pDevEvo, dispIndex, apiHead);
nvEvoLogInfoString(&infoString, "");
outString(data, buffer);
}
}
}
}
static const char *SwapGroupPerEyeStereoString(const NvU32 request)
{
const NvU32 value =
@@ -5942,6 +5904,50 @@ ProcFsPrintDeferredRequestFifos(
}
}
#endif /* NVKMS_PROCFS_OBJECT_DUMP */
#if NVKMS_HEADSURFACE_STATS
static void
ProcFsPrintHeadSurface(
void *data,
char *buffer,
size_t size,
nvkms_procfs_out_string_func_t *outString)
{
NVDevEvoPtr pDevEvo;
NVDispEvoPtr pDispEvo;
NvU32 dispIndex, apiHead;
NVEvoInfoStringRec infoString;
FOR_ALL_EVO_DEVS(pDevEvo) {
nvInitInfoString(&infoString, buffer, size);
nvEvoLogInfoString(&infoString,
"pDevEvo (deviceId:%02d) : %p",
pDevEvo->deviceId.rmDeviceId, pDevEvo);
outString(data, buffer);
FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) {
nvInitInfoString(&infoString, buffer, size);
nvEvoLogInfoString(&infoString,
" pDispEvo (dispIndex:%02d) : %p",
dispIndex, pDispEvo);
outString(data, buffer);
for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) {
nvInitInfoString(&infoString, buffer, size);
nvHsProcFs(&infoString, pDevEvo, dispIndex, apiHead);
nvEvoLogInfoString(&infoString, "");
outString(data, buffer);
}
}
}
}
#endif /* NVKMS_HEADSURFACE_STATS */
#if NVKMS_PROCFS_CRCS
static void
ProcFsPrintDpyCrcs(
void *data,
@@ -6024,17 +6030,37 @@ ProcFsPrintDpyCrcs(
}
}
}
#endif /* NVKMS_PROCFS_CRCS */
static const char *
SignalFormatString(NvKmsConnectorSignalFormat signalFormat)
SignalFormatString(const enum nvKmsTimingsProtocol protocol)
{
switch (signalFormat) {
case NVKMS_CONNECTOR_SIGNAL_FORMAT_VGA: return "VGA";
case NVKMS_CONNECTOR_SIGNAL_FORMAT_LVDS: return "LVDS";
case NVKMS_CONNECTOR_SIGNAL_FORMAT_TMDS: return "TMDS";
case NVKMS_CONNECTOR_SIGNAL_FORMAT_DP: return "DP";
case NVKMS_CONNECTOR_SIGNAL_FORMAT_DSI: return "DSI";
case NVKMS_CONNECTOR_SIGNAL_FORMAT_UNKNOWN: break;
switch (protocol) {
case NVKMS_PROTOCOL_DAC_RGB:
return "VGA";
case NVKMS_PROTOCOL_SOR_SINGLE_TMDS_A:
case NVKMS_PROTOCOL_SOR_SINGLE_TMDS_B:
return "TMDS";
case NVKMS_PROTOCOL_SOR_DUAL_TMDS:
return "Dual TMDS";
case NVKMS_PROTOCOL_SOR_DP_A:
case NVKMS_PROTOCOL_SOR_DP_B:
return "DP";
case NVKMS_PROTOCOL_SOR_LVDS_CUSTOM:
return "LVDS";
case NVKMS_PROTOCOL_SOR_HDMI_FRL:
return "HDMI FRL";
case NVKMS_PROTOCOL_DSI:
return "DSI";
case NVKMS_PROTOCOL_PIOR_EXT_TMDS_ENC:
return "EXT TMDS";
}
return "unknown";
@@ -6070,27 +6096,24 @@ ProcFsPrintHeads(
nvInitInfoString(&infoString, buffer, size);
nvEvoLogInfoString(&infoString,
"pDevEvo (deviceId:%02d) : %p",
pDevEvo->deviceId.rmDeviceId, pDevEvo);
"deviceId : %02d",
pDevEvo->deviceId.rmDeviceId);
outString(data, buffer);
FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) {
const NVLockGroup *pLockGroup = pDispEvo->pLockGroup;
nvInitInfoString(&infoString, buffer, size);
nvEvoLogInfoString(&infoString,
" pDispEvo (dispIndex:%02d) : %p",
dispIndex, pDispEvo);
if (pLockGroup != NULL) {
const NvBool flipLocked = nvIsLockGroupFlipLocked(pLockGroup);
nvInitInfoString(&infoString, buffer, size);
nvEvoLogInfoString(&infoString,
" pLockGroup : %p",
" pLockGroup : %p",
pLockGroup);
nvEvoLogInfoString(&infoString,
" flipLock : %s",
" flipLock : %s",
flipLocked ? "yes" : "no");
outString(data, buffer);
}
outString(data, buffer);
if (pDevEvo->coreInitMethodsPending) {
/* If the core channel has been allocated but no mode has yet
@@ -6098,7 +6121,7 @@ ProcFsPrintHeads(
* driven by the console, but data like the mode timings will
* be bogus. */
nvInitInfoString(&infoString, buffer, size);
nvEvoLogInfoString(&infoString, " (not yet initialized)");
nvEvoLogInfoString(&infoString, " (not yet initialized)");
outString(data, buffer);
continue;
}
@@ -6114,29 +6137,43 @@ ProcFsPrintHeads(
nvInitInfoString(&infoString, buffer, size);
if (pConnectorEvo == NULL) {
nvEvoLogInfoString(&infoString,
" head %d : inactive",
" head %d : inactive",
head);
} else {
const NvU32 refreshRate10kHz =
nvGetRefreshRate10kHz(pHwModeTimings);
const NVDpyEvoRec *pDpyEvo;
/* Find the dpy driven by this head. Multiple heads may be
* driving the same dpy with 2head1or, but a head should
* only drive one dpy at a time. */
FOR_ALL_EVO_DPYS(pDpyEvo, pDispEvo->validDisplays, pDispEvo) {
const NvU32 apiHead = pDpyEvo->apiHead;
if (apiHead == NV_INVALID_HEAD) {
continue;
}
if (pDispEvo->apiHeadState[apiHead].hwHeadsMask &
NVBIT(head)) {
nvEvoLogInfoString(&infoString,
" head %d : %s",
head, pDpyEvo->name);
break;
}
}
nvEvoLogInfoString(&infoString,
" head %d : %s",
head, pConnectorEvo->name);
" protocol : %s",
SignalFormatString(pHwModeTimings->protocol));
nvEvoLogInfoString(&infoString,
" protocol : %s",
SignalFormatString(pConnectorEvo->signalFormat));
nvEvoLogInfoString(&infoString,
" mode : %u x %u @ %u.%04u Hz",
" mode : %u x %u @ %u.%04u Hz",
nvEvoVisibleWidth(pHwModeTimings),
nvEvoVisibleHeight(pHwModeTimings),
refreshRate10kHz / 10000,
refreshRate10kHz % 10000);
nvEvoLogInfoString(&infoString,
" depth : %s",
" depth : %s",
PixelDepthString(pHeadState->pixelDepth));
}
outString(data, buffer);
@@ -6145,25 +6182,107 @@ ProcFsPrintHeads(
}
}
#endif /* NVKMS_PROCFS_ENABLE */
/*
* Dump all dpys for all devices, grouped by connector.
* With DP MST there may be multiple dpys on the same connector.
*/
static void
ProcFsPrintDpys(
void *data,
char *buffer,
size_t size,
nvkms_procfs_out_string_func_t *outString)
{
const NVDevEvoRec *pDevEvo;
const NVDispEvoRec *pDispEvo;
NvU32 dispIndex;
NVEvoInfoStringRec infoString;
FOR_ALL_EVO_DEVS(pDevEvo) {
nvInitInfoString(&infoString, buffer, size);
nvEvoLogInfoString(&infoString,
"deviceId : %02d",
pDevEvo->deviceId.rmDeviceId);
outString(data, buffer);
FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) {
const NVConnectorEvoRec *pConnectorEvo;
FOR_ALL_EVO_CONNECTORS(pConnectorEvo, pDispEvo) {
const NVDpyEvoRec *pDpyEvo;
nvInitInfoString(&infoString, buffer, size);
nvEvoLogInfoString(&infoString,
" connector : %s",
pConnectorEvo->name);
outString(data, buffer);
FOR_ALL_EVO_DPYS(pDpyEvo, pDispEvo->validDisplays, pDispEvo) {
const char *name;
if (pDpyEvo->pConnectorEvo != pConnectorEvo) {
continue;
}
nvInitInfoString(&infoString, buffer, size);
if (nvDpyIdIsInDpyIdList(pDpyEvo->id,
pDispEvo->connectedDisplays)) {
name = pDpyEvo->name;
} else {
name = "(not connected)";
}
nvEvoLogInfoString(&infoString,
" dpy : %s", name);
if (pDpyEvo->edid.length) {
NvU32 i;
const NvU8 *buf = pDpyEvo->edid.buffer;
nvEvoLogInfoStringRaw(&infoString,
" edid :");
for (i = 0; i < pDpyEvo->edid.length; i++) {
if (i % 16 == 0) {
nvEvoLogInfoStringRaw(&infoString, "\n ");
}
if (i % 8 == 0) {
nvEvoLogInfoStringRaw(&infoString, " ");
}
nvEvoLogInfoStringRaw(&infoString, " %02x",
buf[i]);
}
nvEvoLogInfoStringRaw(&infoString, "\n");
}
outString(data, buffer);
}
}
}
}
}
void nvKmsGetProcFiles(const nvkms_procfs_file_t **ppProcFiles)
{
#if NVKMS_PROCFS_ENABLE
static const nvkms_procfs_file_t procFiles[] = {
#if NVKMS_PROCFS_OBJECT_DUMP
{ "clients", ProcFsPrintClients },
{ "surfaces", ProcFsPrintSurfaces },
{ "headsurface", ProcFsPrintHeadSurface },
{ "deferred-request-fifos", ProcFsPrintDeferredRequestFifos },
#endif
#if NVKMS_HEADSURFACE_STATS
{ "headsurface", ProcFsPrintHeadSurface },
#endif
#if NVKMS_PROCFS_CRCS
{ "crcs", ProcFsPrintDpyCrcs },
#endif
{ "heads", ProcFsPrintHeads },
{ "dpys", ProcFsPrintDpys },
{ NULL, NULL },
};
*ppProcFiles = procFiles;
#else
*ppProcFiles = NULL;
#endif
}
static void FreeGlobalState(void)
src/nvidia/arch/nvalloc/common/inc/nvcst.h
+2
View File
@@ -297,6 +297,7 @@ CSINFO chipsetInfo[] =
{PCI_VENDOR_ID_AMPERE, 0xE20D, CS_AMPERE_AMPEREONE192, "Ampere AmpereOne-192", Ampere_AmpereOne_setupFunc},
{PCI_VENDOR_ID_AMPERE, 0xE20E, CS_AMPERE_AMPEREONE192, "Ampere AmpereOne-192", Ampere_AmpereOne_setupFunc},
{PCI_VENDOR_ID_AMPERE, 0xE20F, CS_AMPERE_AMPEREONE192, "Ampere AmpereOne-192", Ampere_AmpereOne_setupFunc},
{PCI_VENDOR_ID_NVIDIA, 0x22D1, CS_NVIDIA_T254, "T254", Nvidia_T194_setupFunc},
///////////////////////////////////////////////////////////////////////////////////////////////////
@@ -420,6 +421,7 @@ ARMCSALLOWLISTINFO armChipsetAllowListInfo[] =
{PCI_VENDOR_ID_AMPERE, 0xE20D, CS_AMPERE_AMPEREONE192}, // Ampere AmpereOne-192
{PCI_VENDOR_ID_AMPERE, 0xE20E, CS_AMPERE_AMPEREONE192}, // Ampere AmpereOne-192
{PCI_VENDOR_ID_AMPERE, 0xE20F, CS_AMPERE_AMPEREONE192}, // Ampere AmpereOne-192
{PCI_VENDOR_ID_NVIDIA, 0x22D1, CS_NVIDIA_T254},
// last element must have chipset CS_UNKNOWN (zero)
{0, 0, CS_UNKNOWN}
src/nvidia/arch/nvalloc/unix/include/nv-gpu-info.h
+2
View File
@@ -32,6 +32,8 @@ typedef struct {
NvU8 bus, slot, function;
} pci_info;
NvBool needs_numa_setup;
/*
* opaque OS-specific pointer; on Linux, this is a pointer to the
* 'struct device' for the GPU.
src/nvidia/arch/nvalloc/unix/include/nv.h
+2 -2
View File
@@ -588,8 +588,8 @@ typedef struct nv_state_t
/* Console is managed by drm drivers or NVKMS */
NvBool client_managed_console;
/* Bool to check if power management is supported */
NvBool is_pm_supported;
/* Bool to check if power management is unsupported */
NvBool is_pm_unsupported;
} nv_state_t;
#define NVFP_TYPE_NONE 0x0
src/nvidia/arch/nvalloc/unix/src/dynamic-power.c
+1 -1
View File
@@ -3008,7 +3008,7 @@ void RmInitPowerManagement(
nvp->gc6_upstream_port_configured = RmConfigureUpstreamPortForRTD3(nv, NV_TRUE);
}
nv->is_pm_supported = pGpu->getProperty(pGpu, PDB_PROP_GPU_POWER_MANAGEMENT_SUPPORTED);
nv->is_pm_unsupported = pGpu->getProperty(pGpu, PDB_PROP_GPU_POWER_MANAGEMENT_UNSUPPORTED);
// UNLOCK: release GPUs lock
rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL);
src/nvidia/arch/nvalloc/unix/src/os-hypervisor.c
-1
View File
@@ -976,7 +976,6 @@ NV_STATUS rm_is_vgpu_supported_device(
for (i = 0; i < NV_ARRAY_ELEMENTS(sVgpuUsmTypes); i++)
{
if (pOsGpuInfo->pci_info.device_id == sVgpuUsmTypes[i].ulDevID &&
pOsGpuInfo->subsystem_vendor == sVgpuUsmTypes[i].ulSubSystemVendorID &&
pOsGpuInfo->subsystem_id == sVgpuUsmTypes[i].ulSubID)
{
return NV_OK;
src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GB20B.c
+26498 -26498
View File
File diff suppressed because it is too large Load Diff
src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GB20B.c
+13264 -13264
View File
File diff suppressed because it is too large Load Diff
src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwProdSigned_GB20B.c
+13287 -13287
View File
File diff suppressed because it is too large Load Diff
src/nvidia/generated/g_ce_utils_nvoc.h
+18
View File
@@ -44,6 +44,7 @@ extern "C" {
#ifndef CE_UTILS_H
#define CE_UTILS_H
#include "core/core.h"
#include "gpu/gpu_resource.h" // GpuResource
#include "class/cl0050.h"
#include "ctrl/ctrl0050.h"
@@ -58,6 +59,8 @@ typedef struct
NvU32 pattern;
NvU64 flags;
NvU64 submittedWorkId; // Payload to poll for async completion
ChannelCompletionCallback pCompletionCallback;
void *pCompletionCallbackArg;
} CEUTILS_MEMSET_PARAMS;
typedef struct
@@ -69,6 +72,8 @@ typedef struct
NvU64 length;
NvU64 flags;
NvU64 submittedWorkId; // Payload to poll for async completion
ChannelCompletionCallback pCompletionCallback;
void *pCompletionCallbackArg;
NvBool bSecureCopy; // The copy encrypts/decrypts when copying to/from unprotected memory
NvBool bEncrypt; // Toggle encrypt/decrypt
@@ -91,6 +96,15 @@ typedef struct KernelChannel KernelChannel;
typedef struct
{
ChannelCompletionCallback pCallback;
void *pArg;
NvU64 payload;
ListNode listNode;
} CeUtilsCallback;
MAKE_INTRUSIVE_LIST(CeUtilsCallbackList, CeUtilsCallback, listNode);
// Private field names are wrapped in PRIVATE_FIELD, which does nothing for
// the matching C source file, but causes diagnostics to be issued if another
@@ -133,6 +147,10 @@ struct CeUtils {
NvU64 lastCompletedPayload;
NvBool bForcedCeId;
NvU64 submissionPausedRefCount;
NvBool bCompletionCallbackEnabled;
PORT_SPINLOCK *pCallbackLock;
CeUtilsCallbackList completionCallbacks;
NVOS10_EVENT_KERNEL_CALLBACK_EX semaphoreCallback;
struct KernelChannel *pLiteKernelChannel;
};
src/nvidia/generated/g_disp_objs_nvoc.c
+121 -91
View File
@@ -3695,6 +3695,21 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
{ /* [55] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
/*pFunc=*/ (void (*)(void)) &dispcmnCtrlCmdSpecificSetHdmiFrlFlushMode_IMPL,
#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*flags=*/ 0x44u,
/*accessRight=*/0x0u,
/*methodId=*/ 0x73029bu,
/*paramSize=*/ sizeof(NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_FLUSH_MODE_PARAMS),
/*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo),
#if NV_PRINTF_STRINGS_ALLOWED
/*func=*/ "dispcmnCtrlCmdSpecificSetHdmiFrlFlushMode"
#endif
},
{ /* [56] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
/*pFunc=*/ (void (*)(void)) &dispcmnCtrlCmdSpecificGetRegionalCrcs_IMPL,
#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
@@ -3707,7 +3722,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdSpecificGetRegionalCrcs"
#endif
},
{ /* [56] */
{ /* [57] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x40u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -3722,7 +3737,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdSpecificApplyEdidOverrideV2"
#endif
},
{ /* [57] */
{ /* [58] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x40u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -3737,7 +3752,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdSpecificGetHdmiGpuCaps"
#endif
},
{ /* [58] */
{ /* [59] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x40u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -3752,7 +3767,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdSpecificDisplayChange"
#endif
},
{ /* [59] */
{ /* [60] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -3767,7 +3782,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdSpecificGetHdmiScdcData"
#endif
},
{ /* [60] */
{ /* [61] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x40u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -3782,7 +3797,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdSpecificIsDirectmodeDisplay"
#endif
},
{ /* [61] */
{ /* [62] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -3797,7 +3812,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdSpecificSetHdmiFrlCapacityComputation"
#endif
},
{ /* [62] */
{ /* [63] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -3812,7 +3827,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdSpecificSetSharedGenericPacket"
#endif
},
{ /* [63] */
{ /* [64] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -3827,7 +3842,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdSpecificAcquireSharedGenericPacket"
#endif
},
{ /* [64] */
{ /* [65] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -3842,7 +3857,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdSpecificReleaseSharedGenericPacket"
#endif
},
{ /* [65] */
{ /* [66] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -3857,7 +3872,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdSpecificDispI2cReadWrite"
#endif
},
{ /* [66] */
{ /* [67] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -3872,7 +3887,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdSpecificGetValidHeadWindowAssignment"
#endif
},
{ /* [67] */
{ /* [68] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x40u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -3887,7 +3902,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdSpecificDefaultAdaptivesyncDisplay"
#endif
},
{ /* [68] */
{ /* [69] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -3902,7 +3917,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdInternalGetHotplugUnplugState"
#endif
},
{ /* [69] */
{ /* [70] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -3917,7 +3932,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdInternalVRRSetRgLineActive"
#endif
},
{ /* [70] */
{ /* [71] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -3932,7 +3947,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdInternalDfpGetDispMuxStatus"
#endif
},
{ /* [71] */
{ /* [72] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -3947,7 +3962,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdInternalDfpSwitchDispMux"
#endif
},
{ /* [72] */
{ /* [73] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -3962,7 +3977,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdFrlConfigMacroPad"
#endif
},
{ /* [73] */
{ /* [74] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4au)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -3977,7 +3992,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDfpGetInfo"
#endif
},
{ /* [74] */
{ /* [75] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -3992,7 +4007,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDfpGetDisplayportDongleInfo"
#endif
},
{ /* [75] */
{ /* [76] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4007,7 +4022,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDfpSetEldAudioCaps"
#endif
},
{ /* [76] */
{ /* [77] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4022,7 +4037,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDfpGetSpreadSpectrum"
#endif
},
{ /* [77] */
{ /* [78] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4037,7 +4052,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDfpUpdateDynamicDfpCache"
#endif
},
{ /* [78] */
{ /* [79] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x40u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4052,7 +4067,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDfpSetAudioEnable"
#endif
},
{ /* [79] */
{ /* [80] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4067,7 +4082,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDfpAssignSor"
#endif
},
{ /* [80] */
{ /* [81] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4082,7 +4097,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDfpGetPadlinkMask"
#endif
},
{ /* [81] */
{ /* [82] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4097,7 +4112,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDfpGetLcdGpioPinNum"
#endif
},
{ /* [82] */
{ /* [83] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4112,7 +4127,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDfpConfigTwoHeadOneOr"
#endif
},
{ /* [83] */
{ /* [84] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4127,7 +4142,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDfpDscCrcControl"
#endif
},
{ /* [84] */
{ /* [85] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x40u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4142,7 +4157,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDfpInitMuxData"
#endif
},
{ /* [85] */
{ /* [86] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4157,7 +4172,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDfpSwitchDispMux"
#endif
},
{ /* [86] */
{ /* [87] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x40u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4172,7 +4187,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDfpRunPreDispMuxOperations"
#endif
},
{ /* [87] */
{ /* [88] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x40u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4187,7 +4202,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDfpRunPostDispMuxOperations"
#endif
},
{ /* [88] */
{ /* [89] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4202,7 +4217,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDfpGetDispMuxStatus"
#endif
},
{ /* [89] */
{ /* [90] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4217,7 +4232,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDfpGetDsiModeTiming"
#endif
},
{ /* [90] */
{ /* [91] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x46u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4232,7 +4247,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDfpGetFixedModeTiming"
#endif
},
{ /* [91] */
{ /* [92] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x40u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4247,7 +4262,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDfpEnterDisplayPowerGating"
#endif
},
{ /* [92] */
{ /* [93] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x40u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4262,7 +4277,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDfpExitDisplayPowerGating"
#endif
},
{ /* [93] */
{ /* [94] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4au)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4277,7 +4292,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDfpEdpDriverUnload"
#endif
},
{ /* [94] */
{ /* [95] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4292,7 +4307,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdSystemSetRegionRamRectangles"
#endif
},
{ /* [95] */
{ /* [96] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4307,7 +4322,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdSystemConfigureSafetyInterrupts"
#endif
},
{ /* [96] */
{ /* [97] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4322,7 +4337,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDfpSetForceBlackPixels"
#endif
},
{ /* [97] */
{ /* [98] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
/*pFunc=*/ (void (*)(void)) &dispcmnCtrlCmdDfpGetDispPhyInfo_IMPL,
#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*flags=*/ 0x44u,
/*accessRight=*/0x0u,
/*methodId=*/ 0x731180u,
/*paramSize=*/ sizeof(NV0073_CTRL_DFP_GET_DISP_PHY_INFO_PARAMS),
/*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo),
#if NV_PRINTF_STRINGS_ALLOWED
/*func=*/ "dispcmnCtrlCmdDfpGetDispPhyInfo"
#endif
},
{ /* [99] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x844u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4337,7 +4367,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDpAuxchCtrl"
#endif
},
{ /* [98] */
{ /* [100] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x844u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4352,7 +4382,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDpCtrl"
#endif
},
{ /* [99] */
{ /* [101] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4367,7 +4397,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDpGetLaneData"
#endif
},
{ /* [100] */
{ /* [102] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4382,7 +4412,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDpSetLaneData"
#endif
},
{ /* [101] */
{ /* [103] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4397,7 +4427,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDpSetTestpattern"
#endif
},
{ /* [102] */
{ /* [104] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4412,7 +4442,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDpGetTestpattern"
#endif
},
{ /* [103] */
{ /* [105] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4427,7 +4457,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDpSetPreemphasisDrivecurrentPostcursor2Data"
#endif
},
{ /* [104] */
{ /* [106] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4442,7 +4472,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDpGetPreemphasisDrivecurrentPostcursor2Data"
#endif
},
{ /* [105] */
{ /* [107] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4457,7 +4487,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDpMainLinkCtrl"
#endif
},
{ /* [106] */
{ /* [108] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4472,7 +4502,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDpSetAudioMuteStream"
#endif
},
{ /* [107] */
{ /* [109] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4487,7 +4517,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDpASSRCtrl"
#endif
},
{ /* [108] */
{ /* [110] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4502,7 +4532,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDpTopologyAllocateDisplayId"
#endif
},
{ /* [109] */
{ /* [111] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4517,7 +4547,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDpTopologyFreeDisplayId"
#endif
},
{ /* [110] */
{ /* [112] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4532,7 +4562,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDpGetLinkConfig"
#endif
},
{ /* [111] */
{ /* [113] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4547,7 +4577,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDpGetEDPData"
#endif
},
{ /* [112] */
{ /* [114] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4562,7 +4592,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDpConfigStream"
#endif
},
{ /* [113] */
{ /* [115] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4577,7 +4607,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDpSetRateGov"
#endif
},
{ /* [114] */
{ /* [116] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4592,7 +4622,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDpSetManualDisplayPort"
#endif
},
{ /* [115] */
{ /* [117] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4607,7 +4637,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDpSetEcf"
#endif
},
{ /* [116] */
{ /* [118] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4622,7 +4652,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDpSendACT"
#endif
},
{ /* [117] */
{ /* [119] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x820046u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4637,7 +4667,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDpGetCaps"
#endif
},
{ /* [118] */
{ /* [120] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4652,7 +4682,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDpGenerateFakeInterrupt"
#endif
},
{ /* [119] */
{ /* [121] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4667,7 +4697,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDpConfigRadScratchReg"
#endif
},
{ /* [120] */
{ /* [122] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4682,7 +4712,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDpConfigSingleHeadMultiStream"
#endif
},
{ /* [121] */
{ /* [123] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4697,7 +4727,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDpSetTriggerSelect"
#endif
},
{ /* [122] */
{ /* [124] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4712,7 +4742,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDpSetTriggerAll"
#endif
},
{ /* [123] */
{ /* [125] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4727,7 +4757,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDpRetrieveDpRingBuffer"
#endif
},
{ /* [124] */
{ /* [126] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4742,7 +4772,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDpGetAuxLogData"
#endif
},
{ /* [125] */
{ /* [127] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4757,7 +4787,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDpConfigIndexedLinkRates"
#endif
},
{ /* [126] */
{ /* [128] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4772,7 +4802,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDpSetStereoMSAProperties"
#endif
},
{ /* [127] */
{ /* [129] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4787,7 +4817,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDpConfigureFec"
#endif
},
{ /* [128] */
{ /* [130] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4802,7 +4832,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDpConfigMacroPad"
#endif
},
{ /* [129] */
{ /* [131] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x40u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4817,7 +4847,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDpAuxchI2cTransferCtrl"
#endif
},
{ /* [130] */
{ /* [132] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x844u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4832,7 +4862,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDpEnableVrr"
#endif
},
{ /* [131] */
{ /* [133] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4847,7 +4877,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDpGetGenericInfoframe"
#endif
},
{ /* [132] */
{ /* [134] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4862,7 +4892,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDpGetMsaAttributes"
#endif
},
{ /* [133] */
{ /* [135] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4877,7 +4907,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDfpInternalLcdOverdrive"
#endif
},
{ /* [134] */
{ /* [136] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4892,7 +4922,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDpSetMSAPropertiesv2"
#endif
},
{ /* [135] */
{ /* [137] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x844u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4907,7 +4937,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDp2xLinkTrain"
#endif
},
{ /* [136] */
{ /* [138] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4922,7 +4952,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDp2xGetLaneData"
#endif
},
{ /* [137] */
{ /* [139] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4937,7 +4967,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDp2xSetLaneData"
#endif
},
{ /* [138] */
{ /* [140] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x40u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4952,7 +4982,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDfpVariableBacklightCtrl"
#endif
},
{ /* [139] */
{ /* [141] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4967,7 +4997,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDpSetLevelInfoTableData"
#endif
},
{ /* [140] */
{ /* [142] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4982,7 +5012,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDpGetLevelInfoTableData"
#endif
},
{ /* [141] */
{ /* [143] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -4997,7 +5027,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDp2xSetLevelInfoTableData"
#endif
},
{ /* [142] */
{ /* [144] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -5012,7 +5042,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDp2xGetLevelInfoTableData"
#endif
},
{ /* [143] */
{ /* [145] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -5027,7 +5057,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdCalculateDpImp"
#endif
},
{ /* [144] */
{ /* [146] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -5042,7 +5072,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
/*func=*/ "dispcmnCtrlCmdDPGetCableIDInfoFromMacro"
#endif
},
{ /* [145] */
{ /* [147] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -5341,7 +5371,7 @@ NV_STATUS __nvoc_up_thunk_Notifier_dispcmnGetOrAllocNotifShare(struct DispCommon
const struct NVOC_EXPORT_INFO __nvoc_export_info__DispCommon =
{
/*numEntries=*/ 146,
/*numEntries=*/ 148,
/*pExportEntries=*/ __nvoc_exported_method_def_DispCommon
};
src/nvidia/generated/g_disp_objs_nvoc.h
+24
View File
@@ -2568,6 +2568,16 @@ static inline NV_STATUS dispcmnCtrlCmdSpecificSetHdmiFrlLinkConfig(struct DispCo
#define dispcmnCtrlCmdSpecificSetHdmiFrlLinkConfig(pDispCommon, pParams) dispcmnCtrlCmdSpecificSetHdmiFrlLinkConfig_IMPL(pDispCommon, pParams)
#endif // __nvoc_disp_objs_h_disabled
NV_STATUS dispcmnCtrlCmdSpecificSetHdmiFrlFlushMode_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_FLUSH_MODE_PARAMS *pParams);
#ifdef __nvoc_disp_objs_h_disabled
static inline NV_STATUS dispcmnCtrlCmdSpecificSetHdmiFrlFlushMode(struct DispCommon *pDispCommon, NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_FLUSH_MODE_PARAMS *pParams) {
NV_ASSERT_FAILED_PRECOMP("DispCommon was disabled!");
return NV_ERR_NOT_SUPPORTED;
}
#else // __nvoc_disp_objs_h_disabled
#define dispcmnCtrlCmdSpecificSetHdmiFrlFlushMode(pDispCommon, pParams) dispcmnCtrlCmdSpecificSetHdmiFrlFlushMode_IMPL(pDispCommon, pParams)
#endif // __nvoc_disp_objs_h_disabled
NV_STATUS dispcmnCtrlCmdSpecificApplyEdidOverrideV2_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_SPECIFIC_APPLY_EDID_OVERRIDE_V2_PARAMS *pEdidOverrideParams);
#ifdef __nvoc_disp_objs_h_disabled
static inline NV_STATUS dispcmnCtrlCmdSpecificApplyEdidOverrideV2(struct DispCommon *pDispCommon, NV0073_CTRL_SPECIFIC_APPLY_EDID_OVERRIDE_V2_PARAMS *pEdidOverrideParams) {
@@ -3258,6 +3268,16 @@ static inline NV_STATUS dispcmnCtrlCmdDfpExitDisplayPowerGating(struct DispCommo
#define dispcmnCtrlCmdDfpExitDisplayPowerGating(pDispCommon, pParams) dispcmnCtrlCmdDfpExitDisplayPowerGating_IMPL(pDispCommon, pParams)
#endif // __nvoc_disp_objs_h_disabled
NV_STATUS dispcmnCtrlCmdDfpGetDispPhyInfo_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_DFP_GET_DISP_PHY_INFO_PARAMS *pParams);
#ifdef __nvoc_disp_objs_h_disabled
static inline NV_STATUS dispcmnCtrlCmdDfpGetDispPhyInfo(struct DispCommon *pDispCommon, NV0073_CTRL_DFP_GET_DISP_PHY_INFO_PARAMS *pParams) {
NV_ASSERT_FAILED_PRECOMP("DispCommon was disabled!");
return NV_ERR_NOT_SUPPORTED;
}
#else // __nvoc_disp_objs_h_disabled
#define dispcmnCtrlCmdDfpGetDispPhyInfo(pDispCommon, pParams) dispcmnCtrlCmdDfpGetDispPhyInfo_IMPL(pDispCommon, pParams)
#endif // __nvoc_disp_objs_h_disabled
// Wrapper macros for halified functions
#define dispcmnControl_FNPTR(pDisplayApi) pDisplayApi->__nvoc_base_DisplayApi.__nvoc_metadata_ptr->vtable.__dispapiControl__
@@ -3572,6 +3592,8 @@ NV_STATUS dispcmnCtrlCmdSpecificSetMonitorPower_IMPL(struct DispCommon *pDispCom
NV_STATUS dispcmnCtrlCmdSpecificSetHdmiFrlLinkConfig_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_LINK_CONFIG_PARAMS *pParams);
NV_STATUS dispcmnCtrlCmdSpecificSetHdmiFrlFlushMode_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_FLUSH_MODE_PARAMS *pParams);
NV_STATUS dispcmnCtrlCmdSpecificApplyEdidOverrideV2_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_SPECIFIC_APPLY_EDID_OVERRIDE_V2_PARAMS *pEdidOverrideParams);
NV_STATUS dispcmnCtrlCmdSpecificGetI2cPortid_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_SPECIFIC_GET_I2C_PORTID_PARAMS *pParams);
@@ -3710,6 +3732,8 @@ NV_STATUS dispcmnCtrlCmdDfpEnterDisplayPowerGating_IMPL(struct DispCommon *pDisp
NV_STATUS dispcmnCtrlCmdDfpExitDisplayPowerGating_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_DFP_EXIT_DISPLAY_POWER_GATING_PARAMS *pParams);
NV_STATUS dispcmnCtrlCmdDfpGetDispPhyInfo_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_DFP_GET_DISP_PHY_INFO_PARAMS *pParams);
#undef PRIVATE_FIELD
src/nvidia/generated/g_gpu_nvoc.c
+6 -3
View File
@@ -346,6 +346,9 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) {
pThis->setProperty(pThis, PDB_PROP_GPU_TOGGLE_DYNAMIC_THROTTLE_WINDOW_SIZE_SUPPORTED, NV_FALSE);
}
// NVOC Property Hal field -- PDB_PROP_GPU_UNIX_HDMI_FRL_COMPLIANCE_ENABLED
pThis->setProperty(pThis, PDB_PROP_GPU_UNIX_HDMI_FRL_COMPLIANCE_ENABLED, NV_TRUE);
// Hal field -- bIsFlexibleFlaSupported
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0xf0000000UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000fe6UL) )) /* ChipHal: GH100 | GB100 | GB102 | GB10B | GB110 | GB112 | GB202 | GB203 | GB205 | GB206 | GB207 | GB20B | GB20C */
@@ -382,17 +385,17 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) {
pThis->setProperty(pThis, PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE, NV_FALSE);
}
// NVOC Property Hal field -- PDB_PROP_GPU_POWER_MANAGEMENT_SUPPORTED
// NVOC Property Hal field -- PDB_PROP_GPU_POWER_MANAGEMENT_UNSUPPORTED
if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000003UL) )) /* RmVariantHal: VF | PF_KERNEL_ONLY */
{
if (( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000c00UL) )) /* ChipHal: GB20B | GB20C */
{
pThis->setProperty(pThis, PDB_PROP_GPU_POWER_MANAGEMENT_SUPPORTED, NV_FALSE);
pThis->setProperty(pThis, PDB_PROP_GPU_POWER_MANAGEMENT_UNSUPPORTED, NV_TRUE);
}
// default
else
{
pThis->setProperty(pThis, PDB_PROP_GPU_POWER_MANAGEMENT_SUPPORTED, NV_TRUE);
pThis->setProperty(pThis, PDB_PROP_GPU_POWER_MANAGEMENT_UNSUPPORTED, NV_FALSE);
}
}
src/nvidia/generated/g_gpu_nvoc.h
+8 -4
View File
@@ -690,6 +690,7 @@ typedef struct
#define GPU_STATE_FLAGS_PM_HIBERNATE NVBIT(4)
#define GPU_STATE_FLAGS_GC6_TRANSITION NVBIT(5) // To be used with GPU_STATE_FLAGS_PRESERVING.
#define GPU_STATE_FLAGS_FAST_UNLOAD NVBIT(6) // Used during windows restart, skips stateDestroy steps
#define GPU_STATE_FLAGS_FORCE_GSP_UNLOAD NVBIT(7) // Force GSP to unload
#define GPU_STATE_DEFAULT 0 // Default flags for destructive state loads
// and unloads
@@ -1159,7 +1160,7 @@ struct OBJGPU {
NV_STATUS (*__gpuRequireGrCePresence__)(struct OBJGPU * /*this*/, ENGDESCRIPTOR, NvBool *); // halified (2 hals) body
NvBool (*__gpuGetIsCmpSku__)(struct OBJGPU * /*this*/); // halified (2 hals) body
// 121 PDB properties
// 122 PDB properties
NvBool PDB_PROP_GPU_HIGH_SPEED_BRIDGE_CONNECTED;
NvBool PDB_PROP_GPU_IN_STANDBY;
NvBool PDB_PROP_GPU_IN_HIBERNATE;
@@ -1207,9 +1208,10 @@ struct OBJGPU {
NvBool PDB_PROP_GPU_IS_COT_ENABLED;
NvBool PDB_PROP_GPU_FW_WPR_OFFSET_SET_BY_ACR;
NvBool PDB_PROP_GPU_TOGGLE_DYNAMIC_THROTTLE_WINDOW_SIZE_SUPPORTED;
NvBool PDB_PROP_GPU_UNIX_HDMI_FRL_COMPLIANCE_ENABLED;
NvBool PDB_PROP_GPU_SRIOV_SYSMEM_DIRTY_PAGE_TRACKING_ENABLED;
NvBool PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE;
NvBool PDB_PROP_GPU_POWER_MANAGEMENT_SUPPORTED;
NvBool PDB_PROP_GPU_POWER_MANAGEMENT_UNSUPPORTED;
NvBool PDB_PROP_GPU_SWRL_GRANULAR_LOCKING;
NvBool PDB_PROP_GPU_IN_SLI_LINK_CODEPATH;
NvBool PDB_PROP_GPU_IS_PLX_PRESENT;
@@ -1621,12 +1623,14 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU;
#define PDB_PROP_GPU_FW_WPR_OFFSET_SET_BY_ACR_BASE_NAME PDB_PROP_GPU_FW_WPR_OFFSET_SET_BY_ACR
#define PDB_PROP_GPU_TOGGLE_DYNAMIC_THROTTLE_WINDOW_SIZE_SUPPORTED_BASE_CAST
#define PDB_PROP_GPU_TOGGLE_DYNAMIC_THROTTLE_WINDOW_SIZE_SUPPORTED_BASE_NAME PDB_PROP_GPU_TOGGLE_DYNAMIC_THROTTLE_WINDOW_SIZE_SUPPORTED
#define PDB_PROP_GPU_UNIX_HDMI_FRL_COMPLIANCE_ENABLED_BASE_CAST
#define PDB_PROP_GPU_UNIX_HDMI_FRL_COMPLIANCE_ENABLED_BASE_NAME PDB_PROP_GPU_UNIX_HDMI_FRL_COMPLIANCE_ENABLED
#define PDB_PROP_GPU_SRIOV_SYSMEM_DIRTY_PAGE_TRACKING_ENABLED_BASE_CAST
#define PDB_PROP_GPU_SRIOV_SYSMEM_DIRTY_PAGE_TRACKING_ENABLED_BASE_NAME PDB_PROP_GPU_SRIOV_SYSMEM_DIRTY_PAGE_TRACKING_ENABLED
#define PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE_BASE_CAST
#define PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE_BASE_NAME PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE
#define PDB_PROP_GPU_POWER_MANAGEMENT_SUPPORTED_BASE_CAST
#define PDB_PROP_GPU_POWER_MANAGEMENT_SUPPORTED_BASE_NAME PDB_PROP_GPU_POWER_MANAGEMENT_SUPPORTED
#define PDB_PROP_GPU_POWER_MANAGEMENT_UNSUPPORTED_BASE_CAST
#define PDB_PROP_GPU_POWER_MANAGEMENT_UNSUPPORTED_BASE_NAME PDB_PROP_GPU_POWER_MANAGEMENT_UNSUPPORTED
#define PDB_PROP_GPU_SWRL_GRANULAR_LOCKING_BASE_CAST
#define PDB_PROP_GPU_SWRL_GRANULAR_LOCKING_BASE_NAME PDB_PROP_GPU_SWRL_GRANULAR_LOCKING
#define PDB_PROP_GPU_IN_SLI_LINK_CODEPATH_BASE_CAST
src/nvidia/generated/g_intr_nvoc.h
+6 -6
View File
@@ -589,12 +589,12 @@ static inline NV_STATUS intrRestoreIntrRegValue(OBJGPU *pGpu, struct Intr *pIntr
#endif // __nvoc_intr_h_disabled
#ifdef __nvoc_intr_h_disabled
static inline NV_STATUS intrTriggerCpuDoorbellForVF(OBJGPU *pGpu, struct Intr *pIntr, NvU32 gfid) {
static inline NV_STATUS intrTriggerCpuDoorbellForVF(OBJGPU *pGpu, struct Intr *pIntr, NvU32 gfid, NvBool bRearmIntr) {
NV_ASSERT_FAILED_PRECOMP("Intr was disabled!");
return NV_ERR_NOT_SUPPORTED;
}
#else // __nvoc_intr_h_disabled
#define intrTriggerCpuDoorbellForVF(pGpu, pIntr, gfid) intrTriggerCpuDoorbellForVF_46f6a7(pGpu, pIntr, gfid)
#define intrTriggerCpuDoorbellForVF(pGpu, pIntr, gfid, bRearmIntr) intrTriggerCpuDoorbellForVF_46f6a7(pGpu, pIntr, gfid, bRearmIntr)
#endif // __nvoc_intr_h_disabled
NvU64 intrGetUvmSharedLeafEnDisableMask_IMPL(OBJGPU *pGpu, struct Intr *pIntr);
@@ -1086,7 +1086,7 @@ static inline NV_STATUS intrRefetchInterruptTable(OBJGPU *pGpu, struct Intr *pIn
#define intrResetIntrRegistersForVF_HAL(pGpu, pIntr, gfid) intrResetIntrRegistersForVF(pGpu, pIntr, gfid)
#define intrSaveIntrRegValue_HAL(pGpu, pIntr, arg3, arg4, arg5) intrSaveIntrRegValue(pGpu, pIntr, arg3, arg4, arg5)
#define intrRestoreIntrRegValue_HAL(pGpu, pIntr, arg3, arg4, arg5) intrRestoreIntrRegValue(pGpu, pIntr, arg3, arg4, arg5)
#define intrTriggerCpuDoorbellForVF_HAL(pGpu, pIntr, gfid) intrTriggerCpuDoorbellForVF(pGpu, pIntr, gfid)
#define intrTriggerCpuDoorbellForVF_HAL(pGpu, pIntr, gfid, bRearmIntr) intrTriggerCpuDoorbellForVF(pGpu, pIntr, gfid, bRearmIntr)
#define intrTriggerPrivDoorbell_FNPTR(pIntr) pIntr->__intrTriggerPrivDoorbell__
#define intrTriggerPrivDoorbell(pGpu, pIntr, gfid) intrTriggerPrivDoorbell_DISPATCH(pGpu, pIntr, gfid)
#define intrTriggerPrivDoorbell_HAL(pGpu, pIntr, gfid) intrTriggerPrivDoorbell_DISPATCH(pGpu, pIntr, gfid)
@@ -1592,13 +1592,13 @@ static inline NV_STATUS intrRestoreIntrRegValue_dffb6f(OBJGPU *pGpu, struct Intr
}
static inline NV_STATUS intrTriggerCpuDoorbellForVF_46f6a7(OBJGPU *pGpu, struct Intr *pIntr, NvU32 gfid) {
static inline NV_STATUS intrTriggerCpuDoorbellForVF_46f6a7(OBJGPU *pGpu, struct Intr *pIntr, NvU32 gfid, NvBool bRearmIntr) {
return NV_ERR_NOT_SUPPORTED;
}
NV_STATUS intrTriggerCpuDoorbellForVF_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 gfid);
NV_STATUS intrTriggerCpuDoorbellForVF_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 gfid, NvBool bRearmIntr);
static inline NV_STATUS intrTriggerCpuDoorbellForVF_92bfc3(OBJGPU *pGpu, struct Intr *pIntr, NvU32 gfid) {
static inline NV_STATUS intrTriggerCpuDoorbellForVF_92bfc3(OBJGPU *pGpu, struct Intr *pIntr, NvU32 gfid, NvBool bRearmIntr) {
NV_ASSERT_PRECOMP(0);
return NV_ERR_NOT_SUPPORTED;
}
src/nvidia/generated/g_kern_gmmu_nvoc.h
-2
View File
@@ -544,7 +544,6 @@ struct KernelGmmu {
// NvBool PDB_PROP_KGMMU_IS_MISSING inherited from OBJENGSTATE
// Data members
NvBool bReportFlaTranslationXid;
MEMORY_DESCRIPTOR *pFakeSparseBuffer;
NvU64 fakeSparseEntry[3];
NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS *pStaticInfo;
@@ -719,7 +718,6 @@ struct KernelGmmu_PRIVATE {
// NvBool PDB_PROP_KGMMU_IS_MISSING inherited from OBJENGSTATE
// Data members
NvBool bReportFlaTranslationXid;
MEMORY_DESCRIPTOR *pFakeSparseBuffer;
NvU64 fakeSparseEntry[3];
NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS *pStaticInfo;
src/nvidia/generated/g_kernel_hfrp_nvoc.h
+6 -5
View File
@@ -237,10 +237,11 @@ static inline NV_STATUS khfrpMailboxQueueMessage(struct KernelHFRP *pHfrp, NvU32
#define khfrpMailboxQueueMessage(pHfrp, messageHeader, pPayloadArray, payloadSize, mailboxFlag) khfrpMailboxQueueMessage_IMPL(pHfrp, messageHeader, pPayloadArray, payloadSize, mailboxFlag)
#endif // __nvoc_kernel_hfrp_h_disabled
void khfrpServiceEvent_IMPL(struct KernelHFRP *pHfrp);
NV_STATUS khfrpServiceEvent_IMPL(struct KernelHFRP *pHfrp);
#ifdef __nvoc_kernel_hfrp_h_disabled
static inline void khfrpServiceEvent(struct KernelHFRP *pHfrp) {
static inline NV_STATUS khfrpServiceEvent(struct KernelHFRP *pHfrp) {
NV_ASSERT_FAILED_PRECOMP("KernelHFRP was disabled!");
return NV_ERR_NOT_SUPPORTED;
}
#else // __nvoc_kernel_hfrp_h_disabled
#define khfrpServiceEvent(pHfrp) khfrpServiceEvent_IMPL(pHfrp)
@@ -295,14 +296,14 @@ static inline NV_STATUS khfrpPollOnIrqRm(struct KernelHFRP *pHfrp, NvU32 irqRegA
#define khfrpPollOnIrqRm(pHfrp, irqRegAddr, bitIndex, bData) khfrpPollOnIrqRm_IMPL(pHfrp, irqRegAddr, bitIndex, bData)
#endif // __nvoc_kernel_hfrp_h_disabled
NV_STATUS khfrpPostCommandBlocking_IMPL(struct KernelHFRP *pHfrp, NvU16 commandIndex, void *pCommandPayload, NvU32 commandPayloadSize, NvU16 *pResponseStatus, void *pResponsePayload, NvU32 *pResponsePayloadSize, NV_STATUS *pStatus);
NV_STATUS khfrpPostCommandBlocking_IMPL(struct KernelHFRP *pHfrp, NvU16 commandIndex, void *pCommandPayload, NvU32 commandPayloadSize, NvU16 *pResponseStatus, void *pResponsePayload, NvU32 *pResponsePayloadSize);
#ifdef __nvoc_kernel_hfrp_h_disabled
static inline NV_STATUS khfrpPostCommandBlocking(struct KernelHFRP *pHfrp, NvU16 commandIndex, void *pCommandPayload, NvU32 commandPayloadSize, NvU16 *pResponseStatus, void *pResponsePayload, NvU32 *pResponsePayloadSize, NV_STATUS *pStatus) {
static inline NV_STATUS khfrpPostCommandBlocking(struct KernelHFRP *pHfrp, NvU16 commandIndex, void *pCommandPayload, NvU32 commandPayloadSize, NvU16 *pResponseStatus, void *pResponsePayload, NvU32 *pResponsePayloadSize) {
NV_ASSERT_FAILED_PRECOMP("KernelHFRP was disabled!");
return NV_ERR_NOT_SUPPORTED;
}
#else // __nvoc_kernel_hfrp_h_disabled
#define khfrpPostCommandBlocking(pHfrp, commandIndex, pCommandPayload, commandPayloadSize, pResponseStatus, pResponsePayload, pResponsePayloadSize, pStatus) khfrpPostCommandBlocking_IMPL(pHfrp, commandIndex, pCommandPayload, commandPayloadSize, pResponseStatus, pResponsePayload, pResponsePayloadSize, pStatus)
#define khfrpPostCommandBlocking(pHfrp, commandIndex, pCommandPayload, commandPayloadSize, pResponseStatus, pResponsePayload, pResponsePayloadSize) khfrpPostCommandBlocking_IMPL(pHfrp, commandIndex, pCommandPayload, commandPayloadSize, pResponseStatus, pResponsePayload, pResponsePayloadSize)
#endif // __nvoc_kernel_hfrp_h_disabled
NV_STATUS khfrpInterfaceReset_IMPL(struct KernelHFRP *pHfrp);
src/nvidia/generated/g_mem_mgr_nvoc.c
+12
View File
@@ -402,6 +402,18 @@ void __nvoc_init_dataField_MemoryManager(MemoryManager *pThis, GpuHalspecOwner *
pThis->bFastScrubberEnabled = NV_FALSE;
}
// Hal field -- bFastScrubberSupportsSysmem
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x80000000UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000c00UL) )) /* ChipHal: GB10B | GB20B | GB20C */
{
pThis->bFastScrubberSupportsSysmem = NV_TRUE;
}
// default
else
{
pThis->bFastScrubberSupportsSysmem = NV_FALSE;
}
// Hal field -- bSysmemPageSizeDefaultAllowLargePages
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x80000000UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000c00UL) )) /* ChipHal: GB10B | GB20B | GB20C */

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