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595.71.05

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This commit is contained in:
Andy Ritger
2026-04-28 08:55:30 -07:00
parent db0c4e65c8
commit 51edebee79
47 changed files with 48117 additions and 47816 deletions
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README.md
+3 -3
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@@ -1,7 +1,7 @@
# NVIDIA Linux Open GPU Kernel Module Source
This is the source release of the NVIDIA Linux open GPU kernel modules,
version 595.58.03.
version 595.71.05.
## How to Build
@@ -17,7 +17,7 @@ as root:
Note that the kernel modules built here must be used with GSP
firmware and user-space NVIDIA GPU driver components from a corresponding
595.58.03 driver release. This can be achieved by installing
595.71.05 driver release. This can be achieved by installing
the NVIDIA GPU driver from the .run file using the `--no-kernel-modules`
option. E.g.,
@@ -185,7 +185,7 @@ table below).
For details on feature support and limitations, see the NVIDIA GPU driver
end user README here:
https://us.download.nvidia.com/XFree86/Linux-x86_64/595.58.03/README/kernel_open.html
https://us.download.nvidia.com/XFree86/Linux-x86_64/595.71.05/README/kernel_open.html
For vGPU support, please refer to the README.vgpu packaged in the vGPU Host
Package for more details.
kernel-open/Kbuild
+1 -1
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@@ -79,7 +79,7 @@ ccflags-y += -I$(src)/common/inc
ccflags-y += -I$(src)
ccflags-y += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-format-extra-args
ccflags-y += -D__KERNEL__ -DMODULE -DNVRM
ccflags-y += -DNV_VERSION_STRING=\"595.58.03\"
ccflags-y += -DNV_VERSION_STRING=\"595.71.05\"
# Include and link Tegra out-of-tree modules.
ifneq ($(wildcard /usr/src/nvidia/nvidia-public),)
kernel-open/Makefile
+3 -26
View File
@@ -71,31 +71,6 @@ else
CC ?= cc
LD ?= ld
OBJDUMP ?= objdump
AWK ?= awk
# Bake the following awk program in a string. The program is needed to add C++
# to the languages excluded from BTF generation.
#
# Also, unconditionally return success (0) from the awk program, rather than
# propagating pahole's return status (with 'exit system(pahole_cmd)'), to
# workaround an DW_TAG_rvalue_reference_type error in
# kernel/nvidia-modeset.ko.
#
# BEGIN {
# pahole_cmd = "pahole"
# for (i = 1; i < ARGC; i++) {
# if (ARGV[i] ~ /--lang_exclude=/) {
# pahole_cmd = pahole_cmd sprintf(" %s,c++", ARGV[i])
# } else {
# pahole_cmd = pahole_cmd sprintf(" %s", ARGV[i])
# }
# }
# system(pahole_cmd)
# }
PAHOLE_AWK_PROGRAM = BEGIN { pahole_cmd = \"pahole\"; for (i = 1; i < ARGC; i++) { if (ARGV[i] ~ /--lang_exclude=/) { pahole_cmd = pahole_cmd sprintf(\" %s,c++\", ARGV[i]); } else { pahole_cmd = pahole_cmd sprintf(\" %s\", ARGV[i]); } } system(pahole_cmd); }
# If scripts/pahole-flags.sh is not present in the kernel tree, add PAHOLE and
# PAHOLE_AWK_PROGRAM assignments to PAHOLE_VARIABLES; otherwise assign the
# empty string to PAHOLE_VARIABLES.
PAHOLE_VARIABLES=$(if $(wildcard $(KERNEL_SOURCES)/scripts/pahole-flags.sh),,"PAHOLE=$(AWK) '$(PAHOLE_AWK_PROGRAM)'")
ifndef ARCH
ARCH := $(shell uname -m | sed -e 's/i.86/i386/' \
@@ -133,10 +108,12 @@ else
KBUILD_PARAMS += INSTALL_MOD_DIR="$(INSTALL_MOD_DIR)"
KBUILD_PARAMS += NV_SPECTRE_V2=$(SPECTRE_V2_RETPOLINE)
export ORIG_PAHOLE := $(PAHOLE)
.PHONY: modules module clean clean_conftest modules_install
modules clean modules_install:
@$(MAKE) "LD=$(LD)" "CC=$(CC)" "OBJDUMP=$(OBJDUMP)" \
$(PAHOLE_VARIABLES) $(KBUILD_PARAMS) $@
PAHOLE=$(CURDIR)/pahole.sh $(KBUILD_PARAMS) $@
@if [ "$@" = "modules" ]; then \
for module in $(NV_KERNEL_MODULES); do \
if [ -x split-object-file.sh ]; then \
kernel-open/common/inc/nv-linux.h
+62
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@@ -1726,7 +1726,69 @@ typedef enum
#include <linux/reset.h>
#include <linux/dma-buf.h>
#include <linux/gpio.h>
#if defined(NV_LINUX_OF_GPIO_H_PRESENT)
#include <linux/of_gpio.h>
#else
#include <linux/gpio/driver.h>
/*
* of_get_named_gpio() was removed along with linux/of_gpio.h by commit
* 51aaf65bbd21 ("gpio: of: Remove <linux/of_gpio.h>"). Provide a compat
* implementation using the remaining public GPIO APIs.
*/
static inline int of_get_named_gpio(const struct device_node *np,
const char *propname, int index)
{
struct of_phandle_args gpiospec;
struct gpio_device *gdev;
struct gpio_desc *desc;
int ret;
if (!np)
return -ENOENT;
ret =
of_parse_phandle_with_args_map(np, propname, "gpio", index, &gpiospec);
if (ret)
return ret;
gdev = gpio_device_find_by_fwnode(of_fwnode_handle(gpiospec.np));
of_node_put(gpiospec.np);
if (!gdev)
return -EPROBE_DEFER;
/*
* Use the chip's of_xlate callback to translate the DT GPIO
* specifier into a linear offset. Tegra GPIO controllers encode
* port and pin in args[0] and of_xlate sums per-port pin counts
* to produce the real offset.
*/
{
struct gpio_chip *chip = gpio_device_get_chip(gdev);
int hwgpio;
#if defined(CONFIG_OF_GPIO)
if (chip->of_xlate)
hwgpio = chip->of_xlate(chip, &gpiospec, NULL);
else
#endif
hwgpio = gpiospec.args[0];
if (hwgpio < 0) {
gpio_device_put(gdev);
return hwgpio;
}
desc = gpio_device_get_desc(gdev, hwgpio);
}
gpio_device_put(gdev);
if (IS_ERR(desc))
return PTR_ERR(desc);
return desc_to_gpio(desc);
}
#endif
#include <linux/of_device.h>
#include <linux/of_platform.h>
kernel-open/conftest.sh
+2 -1
View File
@@ -363,7 +363,8 @@ check_symbol_exists() {
for KMOD in linuxkpi.ko linuxkpi_gplv2.ko drm.ko dmabuf.ko ; do
for KMODPATH in $KMODPATHS; do
if [ -e "$KMODPATH/$KMOD" ] ; then
if nm "$KMODPATH/$KMOD" | grep "$SYMBOL" >/dev/null 2>&1 ; then
# Search if this symbol is a global text symbol in nm output
if nm "$KMODPATH/$KMOD" | grep "T.*$SYMBOL" >/dev/null 2>&1 ; then
return 0
fi
fi
kernel-open/header-presence-tests.mk
+1
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@@ -41,6 +41,7 @@ NV_HEADER_PRESENCE_TESTS = \
linux/vfio_pci_core.h \
linux/cc_platform.h \
linux/slub_def.h \
linux/of_gpio.h \
asm/cpufeature.h \
asm/mshyperv.h \
crypto/sig.h
kernel-open/nvidia-drm/nvidia-drm-linux.c
+1
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@@ -64,3 +64,4 @@ module_exit(nv_linux_drm_exit);
MODULE_INFO(supported, "external");
MODULE_VERSION(NV_VERSION_STRING);
MODULE_DESCRIPTION("NVIDIA DRM kernel module");
kernel-open/nvidia-modeset/nvidia-modeset-linux.c
+1
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@@ -2229,3 +2229,4 @@ module_exit(nvkms_exit);
MODULE_INFO(supported, "external");
MODULE_VERSION(NV_VERSION_STRING);
MODULE_DESCRIPTION("NVIDIA modeset kernel module");
kernel-open/nvidia-uvm/uvm.c
+1
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@@ -1230,3 +1230,4 @@ module_exit(uvm_exit_entry);
MODULE_LICENSE("Dual MIT/GPL");
MODULE_INFO(supported, "external");
MODULE_VERSION(NV_VERSION_STRING);
MODULE_DESCRIPTION("NVIDIA Unified Virtual Memory kernel module");
kernel-open/nvidia-uvm/uvm_gpu_replayable_faults.c
+2
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@@ -1800,6 +1800,7 @@ static NV_STATUS service_fault_batch_ats_sub(uvm_gpu_va_space_t *gpu_va_space,
// ATS faults can't be unserviceable, since unserviceable faults require
// GMMU PTEs.
UVM_ASSERT(!current_entry->is_fatal);
UVM_ASSERT(current_entry->gpu == gpu);
i++;
@@ -1849,6 +1850,7 @@ static NV_STATUS service_fault_batch_ats_sub(uvm_gpu_va_space_t *gpu_va_space,
} while (current_entry &&
(current_entry->fault_address < outer) &&
(previous_entry->gpu == current_entry->gpu) &&
(previous_entry->va_space == current_entry->va_space));
// Service the last sub-batch.
kernel-open/nvidia-uvm/uvm_hmm.c
+25
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@@ -1582,6 +1582,31 @@ uvm_va_block_region_t uvm_hmm_get_prefetch_region(uvm_va_block_t *va_block,
return uvm_va_block_region_from_start_end(va_block, start, end);
}
uvm_prot_t uvm_hmm_compute_mapping_prot(uvm_va_block_t *va_block,
uvm_processor_id_t processor_id,
uvm_page_index_t page_index)
{
if (!uvm_processor_mask_test(&va_block->mapped, UVM_ID_CPU))
return UVM_PROT_NONE;
if (uvm_page_mask_test(&va_block->cpu.pte_bits[UVM_PTE_BITS_CPU_WRITE], page_index)) {
if (uvm_processor_mask_test(&va_block->hmm.va_space->has_native_atomics[uvm_id_value(UVM_ID_CPU)],
processor_id))
// If the CPU has write access it also has atomic access, so it's
// fine for any GPU with HW support to do atomic accesses.
return UVM_PROT_READ_WRITE_ATOMIC;
else
// Otherwise the GPU needs to fault on atomic access to ensure the
// CPU is unmapped.
return UVM_PROT_READ_WRITE;
}
if (uvm_page_mask_test(&va_block->cpu.pte_bits[UVM_PTE_BITS_CPU_READ], page_index))
return UVM_PROT_READ_ONLY;
return UVM_PROT_NONE;
}
uvm_prot_t uvm_hmm_compute_logical_prot(uvm_va_block_t *va_block,
struct vm_area_struct *vma,
NvU64 addr)
kernel-open/nvidia-uvm/uvm_hmm.h
+15
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@@ -258,6 +258,14 @@ typedef struct
const uvm_va_policy_t *policy,
NvU64 address);
// Return the actual permissions allowed when mapping a page within a
// va_block on the given processor_id. This may differ from the logical
// permission if for example the kernel has the CPU pages mapped read-only
// to do copy-on-write.
uvm_prot_t uvm_hmm_compute_mapping_prot(uvm_va_block_t *va_block,
uvm_processor_id_t processor_id,
uvm_page_index_t page_index);
// Return the logical protection allowed of a HMM va_block for the page at
// the given address within the vma which must be valid. This is usually
// obtained from uvm_hmm_va_block_find_create()).
@@ -561,6 +569,13 @@ typedef struct
return (uvm_va_block_region_t){};
}
static uvm_prot_t uvm_hmm_compute_mapping_prot(uvm_va_block_t *va_block,
uvm_processor_id_t processor_id,
uvm_page_index_t page_index)
{
return UVM_PROT_NONE;
}
static uvm_prot_t uvm_hmm_compute_logical_prot(uvm_va_block_t *va_block,
struct vm_area_struct *vma,
NvU64 addr)
kernel-open/nvidia-uvm/uvm_va_block.c
+7
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@@ -10991,6 +10991,13 @@ uvm_prot_t uvm_va_block_page_compute_highest_permission(uvm_va_block_t *va_block
uvm_processor_mask_t *resident_processors = &va_block_context->scratch_processor_mask;
NvU32 resident_processors_count;
// TODO: Bug 5841902
// There are several calls to uvm_va_block_is_hmm() which need to be removed
if (uvm_va_block_is_hmm(va_block))
return uvm_hmm_compute_mapping_prot(va_block,
processor_id,
page_index);
uvm_va_block_page_resident_processors(va_block, page_index, resident_processors);
resident_processors_count = uvm_processor_mask_get_count(resident_processors);
kernel-open/nvidia-uvm/uvm_va_range.c
+10 -5
View File
@@ -929,8 +929,12 @@ void uvm_va_range_remove_gpu_va_space(uvm_va_range_t *va_range,
gpu_va_space->gpu);
break;
case UVM_VA_RANGE_TYPE_DEVICE_P2P:
unmap_mapping_range(va_range->va_space->mapping, va_range->node.start, uvm_va_range_size(va_range), 1);
uvm_va_range_deinit_device_p2p(uvm_va_range_to_device_p2p(va_range), deferred_free_list);
// Device P2P ranges are associated with a specific GPU so destroy
// the range entirely if unregistering the associated GPU.
if (uvm_va_range_to_device_p2p(va_range)->gpu == gpu_va_space->gpu) {
unmap_mapping_range(va_range->va_space->mapping, va_range->node.start, uvm_va_range_size(va_range), 1);
uvm_va_range_deinit_device_p2p(uvm_va_range_to_device_p2p(va_range), deferred_free_list);
}
break;
default:
UVM_ASSERT_MSG(0, "[0x%llx, 0x%llx] has type %d\n",
@@ -1172,9 +1176,10 @@ void uvm_va_range_unregister_gpu(uvm_va_range_t *va_range,
va_range_unregister_gpu_semaphore_pool(uvm_va_range_to_semaphore_pool(va_range), gpu);
break;
case UVM_VA_RANGE_TYPE_DEVICE_P2P:
// All ranges should have been deinited by GPU VA space unregister,
// which should have already happened.
UVM_ASSERT(!uvm_va_range_to_device_p2p(va_range)->p2p_mem);
// All ranges for this GPU should have been deinited by GPU VA space
// unregister, which should have already happened.
if (uvm_va_range_to_device_p2p(va_range)->p2p_mem != NULL)
UVM_ASSERT(uvm_va_range_to_device_p2p(va_range)->gpu != gpu);
break;
default:
UVM_ASSERT_MSG(0, "[0x%llx, 0x%llx] has type %d\n",
kernel-open/nvidia/nv-mmap.c
+5 -5
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@@ -129,10 +129,8 @@ nvidia_vma_access(
nv_alloc_mapping_list_node_t **pfile_mapping_list = NULL;
nv_alloc_mapping_context_t *mmap_context = NULL;
NvU64 offsInVma = addr - vma->vm_start;
NvBool bIsNuma = NV_FALSE;
int ret = -EINVAL;
bIsNuma = pfn_valid(mmap_context->access_start >> PAGE_SHIFT);
NvBool has_pages;
pageIndex = (offsInVma >> PAGE_SHIFT);
pageOffset = (offsInVma & ~PAGE_MASK);
@@ -152,6 +150,8 @@ nvidia_vma_access(
mmap_context = &(*pfile_mapping_list)->context;
has_pages = (mmap_context->num_pages != 0);
if (write && !(mmap_context->prot & NV_PROTECT_WRITEABLE))
{
ret = -EACCES;
@@ -180,7 +180,7 @@ nvidia_vma_access(
pageIndex = nv_array_index_no_speculate(pageIndex, at->num_pages);
kernel_mapping = (void *)(at->page_table[pageIndex].virt_addr + pageOffset);
}
else if (bIsNuma)
else if (has_pages)
{
struct page *pPage = NV_GET_PAGE_STRUCT(mmap_context->page_array[pageIndex]);
NvU8 *pPagePtr = (NvU8 *) page_address(pPage);
@@ -230,7 +230,7 @@ found:
memcpy(buffer, kernel_mapping, length);
#endif // defined(NVCPU_AARCH64)
if (at == NULL && !bIsNuma)
if (at == NULL && !has_pages)
{
kernel_mapping = ((char *)kernel_mapping - pageOffset);
os_unmap_kernel_space(kernel_mapping, PAGE_SIZE);
kernel-open/nvidia/nv-usermap.c
+5
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@@ -104,6 +104,11 @@ NV_STATUS NV_API_CALL nv_add_mapping_context_to_file(
if (*pfile_mapping_list == NULL)
{
*pfile_mapping_list = pNewNode;
if (NV_IS_CTL_DEVICE(nv))
{
nv_alloc_t *at = (nv_alloc_t *) nvamc->alloc;
atomic64_inc(&at->usage_count);
}
}
else
{
kernel-open/nvidia/nv.c
+15
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@@ -121,6 +121,7 @@ MODULE_LICENSE("Dual MIT/GPL");
MODULE_INFO(supported, "external");
MODULE_VERSION(NV_VERSION_STRING);
MODULE_DESCRIPTION("NVIDIA core GPU kernel module");
MODULE_ALIAS_CHARDEV_MAJOR(NV_MAJOR_DEVICE_NUMBER);
/*
@@ -3213,6 +3214,20 @@ nvidia_ctl_close(
rm_cleanup_file_private(sp, nv, &nvlfp->nvfp);
// Populate free list from file nodes
{
nv_alloc_mapping_list_node_t *pNode = nvlfp->file_mapping_list;
while (pNode != NULL)
{
if (pNode->context.alloc != NULL)
{
nv_alloc_t *at = pNode->context.alloc;
nv_alloc_release(nvlfp, at);
}
pNode = pNode->pNext;
}
}
if (nvlfp->free_list != NULL)
{
at = nvlfp->free_list;
kernel-open/pahole.sh
Executable
+66
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@@ -0,0 +1,66 @@
#!/bin/sh
if [ "$KBUILD_VERBOSE" = "1" ]; then
set -x
fi
PAHOLE=${ORIG_PAHOLE:-pahole}
# Use DRY_RUN=echo to print the command instead of executing it, for debugging.
DRY_RUN=${DRY_RUN:-}
btf_encode=0
lang_exclude=
# Parse args: detect BTF encoding and existing --lang_exclude, while
# rebuilding the argument list without --lang_exclude.
args_start=0
for arg in "$@"; do
case "$arg" in
--btf_features=*encode_force* | -J | --btf_encode | --btf_encode_force)
btf_encode=1
;;
--lang_exclude=*)
lang_exclude="${arg#*=}"
# Drop this arg from the rebuilt list.
if [ $args_start -eq 0 ]; then
set --
args_start=1
fi
continue
;;
esac
if [ $args_start -eq 0 ]; then
set -- "$arg"
args_start=1
else
set -- "$@" "$arg"
fi
done
# Capture anything the kernel is already excluding and extend it with c++.
# Even if in future the kernel doesn't have to exclude other languages,
# make sure to exclude c++ when generating encoding BTF.
if [ $btf_encode -eq 1 ] || [ -n "$lang_exclude" ]; then
if [ -n "$lang_exclude" ]; then
lang_exclude="${lang_exclude},c++"
else
lang_exclude="c++"
fi
set -- --lang_exclude="$lang_exclude" "$@"
$DRY_RUN "$PAHOLE" "$@"
ret=$?
# Until pahole 1.31, return code was still an error regardless of
# --btf_encode_force / --btf_features=encode_force.
# A pure version check is not possible as it's likely that pahole
# from distros will have fixes backported. Just ignore the error for now.
if [ $ret -ne 0 ]; then
echo "pahole.sh: warning: pahole exited with status $ret (ignored)" >&2
fi
exit 0
fi
# Do not override options or exit status, as this may interfere with the kernel
# build system when determining pahole version and options.
$DRY_RUN exec "$PAHOLE" "$@"
src/common/inc/nvBldVer.h
+10 -10
View File
@@ -36,25 +36,25 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r595_88
#define NV_BUILD_BRANCH r596_25
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r595_88
#define NV_PUBLIC_BRANCH r596_25
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r595/r595_88-200"
#define NV_BUILD_CHANGELIST_NUM (37651405)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r595/r596_25-250"
#define NV_BUILD_CHANGELIST_NUM (37855471)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r595/r595_88-200"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (37651405)
#define NV_BUILD_NAME "rel/gpu_drv/r595/r596_25-250"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (37855471)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r595_88-3"
#define NV_BUILD_CHANGELIST_NUM (37651405)
#define NV_BUILD_BRANCH_VERSION "r596_25-5"
#define NV_BUILD_CHANGELIST_NUM (37847067)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "595.97"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (37651405)
#define NV_BUILD_NAME "596.36"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (37847067)
#define NV_BUILD_BRANCH_BASE_VERSION R595
#endif
// End buildmeister python edited section
src/common/inc/nvUnixVersion.h
+1 -1
View File
@@ -5,7 +5,7 @@
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1) || \
defined(NV_DCECORE)
#define NV_VERSION_STRING "595.58.03"
#define NV_VERSION_STRING "595.71.05"
#else
src/common/modeset/timing/nvt_util.c
+7
View File
@@ -366,6 +366,13 @@ NvU32 NvTiming_IsTimingRelaxedEqual(const NVT_TIMING *pT1, const NVT_TIMING *pT2
(!!pT1->interlaced == !!pT2->interlaced));
}
CODE_SEGMENT(NONPAGE_DD_CODE)
NvU32 NvTiming_IsTimingRelaxedEqualEx(const NVT_TIMING *pT1, const NVT_TIMING *pT2)
{
NvU32 bIsTimingRelaxedEqual = NvTiming_IsTimingRelaxedEqual(pT1, pT2);
return (bIsTimingRelaxedEqual && (pT1->etc.rrx1k == pT2->etc.rrx1k));
}
CODE_SEGMENT(NONPAGE_DD_CODE)
NvU32 RRx1kToPclk (const NVT_TIMING *pT)
{
src/common/modeset/timing/nvtiming.h
+9
View File
@@ -2110,6 +2110,13 @@ typedef struct tagNVT_EDID_18BYTE_DESCRIPTOR
#define NVT_EDID_DISPLAY_DESCRIPTOR_CVT 0xF8 // CVT 3-byte timing code
#define NVT_EDID_DISPLAY_DESCRIPTOR_ESTIII 0xF7 // establishied timing III
#define NVT_EDID_DISPLAY_DESCRIPTOR_DUMMY 0x10 // dummy descriptor
// NVT_EDID_DISPLAY_DESCRIPTOR_MANUF_SPECIFIC: Generic tag for E-EDID manufacturer-specific
// display descriptors (0x00-0x0F per E-EDID spec). Used to preserve and pass through
// proprietary panel/display data (e.g. Barco medical devices) in Long Display Descriptors
// without interpretation. Customer: Barco medical devices. Bug reference: 5571067.
#define NVT_EDID_DISPLAY_DESCRIPTOR_MANUF_SPECIFIC 0x0E // generic tag for manufacturer-specific descriptors (range 0x00-0x0F)
#define NVT_EDID_DISPLAY_DESCRIPTOR_MANUF_SPECIFIC_MIN 0x00 // manufacturer-specific descriptor range minimum
#define NVT_EDID_DISPLAY_DESCRIPTOR_MANUF_SPECIFIC_MAX 0x0F // manufacturer-specific descriptor range maximum
//*******************
// Raw EDID offsets and info
@@ -2187,6 +2194,7 @@ typedef struct tagNVT_EDID_18BYTE_DESCRIPTOR
#define NVT_EDID_VER_1_2 0x102
#define NVT_EDID_VER_1_3 0x103
#define NVT_EDID_VER_1_4 0x104
#define NVT_EDID_MANUFACTURER_ID_CID 0x240D
//
// byte 0x14, Digital
// bits 0-3
@@ -5816,6 +5824,7 @@ NvU32 NvTiming_IsRoundedRREqual(NvU16 rr1, NvU32 rr1x1k, NvU16 rr2);
NvU32 NvTiming_IsTimingExactEqual(const NVT_TIMING *pT1, const NVT_TIMING *pT2);
NvU32 NvTiming_IsTimingExactEqualEx(const NVT_TIMING *pT1, const NVT_TIMING *pT2);
NvU32 NvTiming_IsTimingRelaxedEqual(const NVT_TIMING *pT1, const NVT_TIMING *pT2);
NvU32 NvTiming_IsTimingRelaxedEqualEx(const NVT_TIMING *pT1, const NVT_TIMING *pT2);
NvU16 NvTiming_MaxFrameWidth(NvU16 HVisible, NvU16 rep);
NvU32 NvTiming_GetVrrFmin(const NVT_EDID_INFO *pEdidInfo, const NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo,
src/common/sdk/nvidia/inc/class/cl00de.h
+3 -1
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -265,6 +265,8 @@ typedef struct RUSD_MEM_ROW_REMAP_INFO {
NvU32 correctableRows;
NvU32 uncorrectableRows;
NvU32 correctableRowsInactive;
NvU32 uncorrectableRowsInactive;
NvBool isPending;
NvBool hasFailureOccurred;
} RUSD_MEM_ROW_REMAP_INFO;
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080base.h
+1
View File
@@ -55,6 +55,7 @@
#define NV2080_CTRL_FIFO (0x11)
#define NV2080_CTRL_GR (0x12)
#define NV2080_CTRL_FB (0x13)
#define NV2080_CTRL_NOISE (0x15)
#define NV2080_CTRL_MC (0x17)
#define NV2080_CTRL_BUS (0x18)
#define NV2080_CTRL_PERF_LEGACY_PRIVILEGED (0xe0) /* finn: Evaluated from "(NV2080_CTRL_PERF | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h
+4 -1
View File
@@ -1866,9 +1866,12 @@ typedef struct NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS {
NvU32 backingStoreChunkOverfetch;
} NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS;
#define NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING 0:0
#define NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING 0:0
#define NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_FALSE 0U
#define NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_TRUE 1U
#define NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_ACTIVE 1:1
#define NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_ACTIVE_FALSE 0U
#define NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_ACTIVE_TRUE 1U
src/common/src/nv_smg.c
-12
View File
@@ -112,9 +112,7 @@ static struct nvGlobalMigMappingRec {
static NvBool InitializeGlobalMapping(nvRMContextPtr rmctx);
static NvBool ListPartitions(nvRMContextPtr rmctx, struct nvGlobalMigMappingRec *mappings);
#if !defined(NV_MODS) && !defined(NV_RMAPI_TEGRA)
static NvBool GetGraphicsPartitionUUIDForDevice(nvRMContextPtr rmctx, nvMIGDeviceDescription *migDev);
#endif
static NvU32 DeviceInMigMode (nvRMContextPtr rmctx, NvU32 hSubDevice, NvBool *inMigMode);
static NvBool GpuHasSMGPartitions (NvU32 gpuId);
@@ -388,7 +386,6 @@ static NvBool InitializeGlobalMapping(nvRMContextPtr rmctx)
*/
static NvBool ListPartitions(nvRMContextPtr rmctx, struct nvGlobalMigMappingRec *mapping)
{
#if !defined(NV_MODS) && !defined(NV_RMAPI_TEGRA)
struct workspace {
NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS activeParams;
NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS idInfoParams;
@@ -474,20 +471,12 @@ static NvBool ListPartitions(nvRMContextPtr rmctx, struct nvGlobalMigMappingRec
EXIT_WORKSPACE_AND_RETURN(ws, NV_TRUE);
#else /* !defined(NV_MODS) && !defined(NV_RMAPI_TEGRA) */
/*
* MODS and TEgra builds don't have all the MIG related rmcontrols so
* don't do any queries, just leave it with zero SMG partitions.
*/
return NV_TRUE;
#endif /* !defined(NV_MODS) && !defined(NV_RMAPI_TEGRA) */
}
/*
* Obtain the UUID of the MIG device. This means allocating the devices and
* partition refs so that we can access the GET_UUID control.
*/
#if !defined(NV_MODS) && !defined(NV_RMAPI_TEGRA)
static NvBool GetGraphicsPartitionUUIDForDevice(nvRMContextPtr rmctx, nvMIGDeviceDescription *migDev)
{
struct workspace {
@@ -626,7 +615,6 @@ out:
rmctx->free(rmctx, rmctx->clientHandle, rmctx->clientHandle, hDevice);
EXIT_WORKSPACE_AND_RETURN(ws, success);
}
#endif /* !defined(NV_MODS) && !defined(NV_RMAPI_TEGRA) */
/*
* Quick getter for SMC mode.
src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GB10B.c
+23770 -23770
View File
File diff suppressed because it is too large Load Diff
src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GB10B.c
+11904 -11904
View File
File diff suppressed because it is too large Load Diff
src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwProdSigned_GB10B.c
+11927 -11927
View File
File diff suppressed because it is too large Load Diff
src/nvidia/generated/g_chipset_nvoc.h
+4 -4
View File
@@ -794,12 +794,12 @@ static inline NV_STATUS clPcieIsRelaxedOrderingSafe(struct OBJCL *pCl, struct OB
#endif // __nvoc_chipset_h_disabled
#ifdef __nvoc_chipset_h_disabled
static inline NV_STATUS clStoreBusTopologyCache(struct OBJCL *pCl, NvU32 secDomain, NvU16 secBus) {
static inline NV_STATUS clStoreBusTopologyCache(struct OBJGPU *pGpu, struct OBJCL *pCl, NvU32 secDomain, NvU16 secBus) {
NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!");
return NV_ERR_NOT_SUPPORTED;
}
#else // __nvoc_chipset_h_disabled
#define clStoreBusTopologyCache(pCl, secDomain, secBus) clStoreBusTopologyCache_IMPL(pCl, secDomain, secBus)
#define clStoreBusTopologyCache(pGpu, pCl, secDomain, secBus) clStoreBusTopologyCache_IMPL(pGpu, pCl, secDomain, secBus)
#endif // __nvoc_chipset_h_disabled
#ifdef __nvoc_chipset_h_disabled
@@ -979,7 +979,7 @@ static inline void clSyncWithGsp(struct OBJCL *arg_this, GspSystemInfo *arg2) {
#define clSearchBR04_HAL(pCl, pBR04BusArray, pBR04RevArray, pBR04Count) clSearchBR04(pCl, pBR04BusArray, pBR04RevArray, pBR04Count)
#define clPcieGetMaxCapableLinkWidth_HAL(pCl, pGpu, maxCapableLinkWidth) clPcieGetMaxCapableLinkWidth(pCl, pGpu, maxCapableLinkWidth)
#define clPcieIsRelaxedOrderingSafe_HAL(pCl, pGpu, result) clPcieIsRelaxedOrderingSafe(pCl, pGpu, result)
#define clStoreBusTopologyCache_HAL(pCl, secDomain, secBus) clStoreBusTopologyCache(pCl, secDomain, secBus)
#define clStoreBusTopologyCache_HAL(pGpu, pCl, secDomain, secBus) clStoreBusTopologyCache(pGpu, pCl, secDomain, secBus)
#define clFreeBusTopologyCache_HAL(pCl) clFreeBusTopologyCache(pCl)
#define clIsL1SupportedForUpstreamPort_HAL(arg1, arg_this) clIsL1SupportedForUpstreamPort(arg1, arg_this)
#define clIsL0sMaskEnabledForUpstreamPort_HAL(arg1, arg_this) clIsL0sMaskEnabledForUpstreamPort(arg1, arg_this)
@@ -1066,7 +1066,7 @@ NV_STATUS clPcieGetMaxCapableLinkWidth_IMPL(struct OBJCL *pCl, struct OBJGPU *pG
NV_STATUS clPcieIsRelaxedOrderingSafe_IMPL(struct OBJCL *pCl, struct OBJGPU *pGpu, NvBool *result);
NV_STATUS clStoreBusTopologyCache_IMPL(struct OBJCL *pCl, NvU32 secDomain, NvU16 secBus);
NV_STATUS clStoreBusTopologyCache_IMPL(struct OBJGPU *pGpu, struct OBJCL *pCl, NvU32 secDomain, NvU16 secBus);
void clFreeBusTopologyCache_IMPL(struct OBJCL *pCl);
src/nvidia/generated/g_device_nvoc.c
+20 -35
View File
@@ -714,12 +714,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[]
#endif
},
{ /* [39] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10008u)
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100008u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
/*pFunc=*/ (void (*)(void)) &deviceCtrlCmdDmaGetPteInfo_IMPL,
#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10008u)
/*flags=*/ 0x10008u,
#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100008u)
/*flags=*/ 0x100008u,
/*accessRight=*/0x0u,
/*methodId=*/ 0x801801u,
/*paramSize=*/ sizeof(NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS),
@@ -776,21 +776,6 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[]
{ /* [43] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10008u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
/*pFunc=*/ (void (*)(void)) &deviceCtrlCmdDmaSetPteInfo_IMPL,
#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10008u)
/*flags=*/ 0x10008u,
/*accessRight=*/0x0u,
/*methodId=*/ 0x80180au,
/*paramSize=*/ sizeof(NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS),
/*pClassInfo=*/ &(__nvoc_class_def_Device.classInfo),
#if NV_PRINTF_STRINGS_ALLOWED
/*func=*/ "deviceCtrlCmdDmaSetPteInfo"
#endif
},
{ /* [44] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10008u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
/*pFunc=*/ (void (*)(void)) &deviceCtrlCmdDmaInvalidateTLB_IMPL,
#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10008u)
@@ -803,7 +788,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[]
/*func=*/ "deviceCtrlCmdDmaInvalidateTLB"
#endif
},
{ /* [45] */
{ /* [44] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10109u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -818,7 +803,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[]
/*func=*/ "deviceCtrlCmdDmaGetCaps"
#endif
},
{ /* [46] */
{ /* [45] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10008u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -833,7 +818,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[]
/*func=*/ "deviceCtrlCmdDmaSetVASpaceSize"
#endif
},
{ /* [47] */
{ /* [46] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -848,7 +833,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[]
/*func=*/ "deviceCtrlCmdDmaUpdatePde2"
#endif
},
{ /* [48] */
{ /* [47] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c000u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -863,7 +848,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[]
/*func=*/ "deviceCtrlCmdDmaSetDefaultVASpace"
#endif
},
{ /* [49] */
{ /* [48] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x14004u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -878,7 +863,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[]
/*func=*/ "deviceCtrlCmdDmaSetPageDirectory"
#endif
},
{ /* [50] */
{ /* [49] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x14004u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -893,7 +878,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[]
/*func=*/ "deviceCtrlCmdDmaUnsetPageDirectory"
#endif
},
{ /* [51] */
{ /* [50] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x118u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -908,7 +893,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[]
/*func=*/ "deviceCtrlCmdKPerfCudaLimitSetControl"
#endif
},
{ /* [52] */
{ /* [51] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50148u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -923,7 +908,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[]
/*func=*/ "deviceCtrlCmdMsencGetCapsV2"
#endif
},
{ /* [53] */
{ /* [52] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50148u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -938,7 +923,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[]
/*func=*/ "deviceCtrlCmdBspGetCapsV2"
#endif
},
{ /* [54] */
{ /* [53] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -953,7 +938,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[]
/*func=*/ "deviceCtrlCmdOsUnixVTSwitch"
#endif
},
{ /* [55] */
{ /* [54] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -968,7 +953,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[]
/*func=*/ "deviceCtrlCmdOsUnixVTGetFBInfo"
#endif
},
{ /* [56] */
{ /* [55] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50048u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -983,7 +968,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[]
/*func=*/ "deviceCtrlCmdNvjpgGetCapsV2"
#endif
},
{ /* [57] */
{ /* [56] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -998,7 +983,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[]
/*func=*/ "deviceCtrlCmdInternalPerfCudaLimitDisable"
#endif
},
{ /* [58] */
{ /* [57] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1d8u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -1013,7 +998,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[]
/*func=*/ "deviceCtrlCmdInternalPerfCudaLimitSetControl"
#endif
},
{ /* [59] */
{ /* [58] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10008u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -1028,7 +1013,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[]
/*func=*/ "deviceCtrlCmdFbSetZbcReferenced"
#endif
},
{ /* [60] */
{ /* [59] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1d0u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -1305,7 +1290,7 @@ void __nvoc_up_thunk_RsResource_deviceAddAdditionalDependants(struct RsClient *p
const struct NVOC_EXPORT_INFO __nvoc_export_info__Device =
{
.numEntries= 61,
.numEntries= 60,
.pExportEntries= __nvoc_exported_method_def_Device
};
src/nvidia/generated/g_device_nvoc.h
-12
View File
@@ -339,16 +339,6 @@ static inline NV_STATUS deviceCtrlCmdDmaGetPdeInfo(struct Device *pDevice, NV008
#define deviceCtrlCmdDmaGetPdeInfo(pDevice, pParams) deviceCtrlCmdDmaGetPdeInfo_IMPL(pDevice, pParams)
#endif // __nvoc_device_h_disabled
NV_STATUS deviceCtrlCmdDmaSetPteInfo_IMPL(struct Device *pDevice, NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS *pParams);
#ifdef __nvoc_device_h_disabled
static inline NV_STATUS deviceCtrlCmdDmaSetPteInfo(struct Device *pDevice, NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS *pParams) {
NV_ASSERT_FAILED_PRECOMP("Device was disabled!");
return NV_ERR_NOT_SUPPORTED;
}
#else // __nvoc_device_h_disabled
#define deviceCtrlCmdDmaSetPteInfo(pDevice, pParams) deviceCtrlCmdDmaSetPteInfo_IMPL(pDevice, pParams)
#endif // __nvoc_device_h_disabled
NV_STATUS deviceCtrlCmdDmaInvalidateTLB_IMPL(struct Device *pDevice, NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS *pParams);
#ifdef __nvoc_device_h_disabled
static inline NV_STATUS deviceCtrlCmdDmaInvalidateTLB(struct Device *pDevice, NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS *pParams) {
@@ -1018,8 +1008,6 @@ NV_STATUS deviceCtrlCmdDmaAdvSchedGetVaCaps_IMPL(struct Device *pDevice, NV0080_
NV_STATUS deviceCtrlCmdDmaGetPdeInfo_IMPL(struct Device *pDevice, NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS *pParams);
NV_STATUS deviceCtrlCmdDmaSetPteInfo_IMPL(struct Device *pDevice, NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS *pParams);
NV_STATUS deviceCtrlCmdDmaInvalidateTLB_IMPL(struct Device *pDevice, NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS *pParams);
NV_STATUS deviceCtrlCmdDmaGetCaps_IMPL(struct Device *pDevice, NV0080_CTRL_DMA_GET_CAPS_PARAMS *pDmaCapsParams);
src/nvidia/generated/g_kernel_gsp_nvoc.c
+37 -18
View File
@@ -1227,6 +1227,25 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, GpuHalspecOwner
}
}
// kgspCheckGspPoisonError -- halified (3 hals) body
if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
{
pThis->__kgspCheckGspPoisonError__ = &kgspCheckGspPoisonError_86b752;
}
else
{
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0xb8000000UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003f9UL) )) /* ChipHal: GB100 | GB102 | GB10B | GB110 | GB112 | GB202 | GB203 | GB205 | GB206 | GB207 | GB20B | GB20C */
{
pThis->__kgspCheckGspPoisonError__ = &kgspCheckGspPoisonError_GB100;
}
// default
else
{
pThis->__kgspCheckGspPoisonError__ = &kgspCheckGspPoisonError_d69453;
}
}
// kgspServiceFatalHwError -- halified (3 hals) body
if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
{
@@ -1991,6 +2010,21 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, GpuHalspecOwner
pThis->__kgspExecuteCoreResume__ = &kgspExecuteCoreResume_5baef9;
}
}
} // End __nvoc_init_funcTable_KernelGsp_1 with approximately 261 basic block(s).
// Vtable initialization 2/2
static void __nvoc_init_funcTable_KernelGsp_2(KernelGsp *pThis, GpuHalspecOwner *pGpuhalspecowner, RmHalspecOwner *pRmhalspecowner) {
ChipHal *chipHal = &pGpuhalspecowner->chipHal;
const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx;
RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal;
const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx;
PORT_UNREFERENCED_VARIABLE(pThis);
PORT_UNREFERENCED_VARIABLE(pGpuhalspecowner);
PORT_UNREFERENCED_VARIABLE(pRmhalspecowner);
PORT_UNREFERENCED_VARIABLE(chipHal);
PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx);
PORT_UNREFERENCED_VARIABLE(rmVariantHal);
PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx);
// kgspLoadAndExecuteGenericBootloader -- halified (3 hals) body
if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
@@ -2009,21 +2043,6 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, GpuHalspecOwner
pThis->__kgspLoadAndExecuteGenericBootloader__ = &kgspLoadAndExecuteGenericBootloader_5baef9;
}
}
} // End __nvoc_init_funcTable_KernelGsp_1 with approximately 261 basic block(s).
// Vtable initialization 2/2
static void __nvoc_init_funcTable_KernelGsp_2(KernelGsp *pThis, GpuHalspecOwner *pGpuhalspecowner, RmHalspecOwner *pRmhalspecowner) {
ChipHal *chipHal = &pGpuhalspecowner->chipHal;
const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx;
RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal;
const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx;
PORT_UNREFERENCED_VARIABLE(pThis);
PORT_UNREFERENCED_VARIABLE(pGpuhalspecowner);
PORT_UNREFERENCED_VARIABLE(pRmhalspecowner);
PORT_UNREFERENCED_VARIABLE(chipHal);
PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx);
PORT_UNREFERENCED_VARIABLE(rmVariantHal);
PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx);
// kgspLoadAndExecuteHsBinary -- halified (3 hals) body
if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
@@ -2060,13 +2079,13 @@ static void __nvoc_init_funcTable_KernelGsp_2(KernelGsp *pThis, GpuHalspecOwner
// kgspGetWFL0Offset -- virtual halified (2 hals) inherited (kcrashcatEngine) base (kflcn) body
pThis->__kgspGetWFL0Offset__ = &__nvoc_up_thunk_KernelCrashCatEngine_kgspGetWFL0Offset;
} // End __nvoc_init_funcTable_KernelGsp_2 with approximately 19 basic block(s).
} // End __nvoc_init_funcTable_KernelGsp_2 with approximately 22 basic block(s).
// Initialize vtable(s) for 100 virtual method(s).
// Initialize vtable(s) for 101 virtual method(s).
void __nvoc_init_funcTable_KernelGsp(KernelGsp *pThis, GpuHalspecOwner *pGpuhalspecowner, RmHalspecOwner *pRmhalspecowner) {
// Initialize vtable(s) with 73 per-object function pointer(s).
// Initialize vtable(s) with 74 per-object function pointer(s).
// To reduce stack pressure with some unoptimized builds, the logic is distributed among 2 functions.
__nvoc_init_funcTable_KernelGsp_1(pThis, pGpuhalspecowner, pRmhalspecowner);
__nvoc_init_funcTable_KernelGsp_2(pThis, pGpuhalspecowner, pRmhalspecowner);
src/nvidia/generated/g_kernel_gsp_nvoc.h
+20 -1
View File
@@ -428,7 +428,7 @@ struct KernelGsp {
struct KernelFalcon *__nvoc_pbase_KernelFalcon; // kflcn super
struct KernelGsp *__nvoc_pbase_KernelGsp; // kgsp
// Vtable with 73 per-object function pointers
// Vtable with 74 per-object function pointers
void (*__kgspConfigureFalcon__)(struct OBJGPU *, struct KernelGsp * /*this*/); // halified (4 hals) body
void (*__kgspFmcResetErrorCode__)(struct OBJGPU *, struct KernelGsp * /*this*/); // halified (3 hals) body
NvBool (*__kgspFmcCheckForErrorCode__)(struct OBJGPU *, struct KernelGsp * /*this*/); // halified (3 hals) body
@@ -456,6 +456,7 @@ struct KernelGsp {
void (*__kgspDumpMailbox__)(struct OBJGPU *, struct KernelGsp * /*this*/); // halified (3 hals) body
NvU32 (*__kgspReadMailbox__)(struct OBJGPU *, struct KernelGsp * /*this*/, NvU32); // halified (3 hals) body
NvU32 (*__kgspService__)(struct OBJGPU *, struct KernelGsp * /*this*/); // halified (3 hals) body
NvBool (*__kgspCheckGspPoisonError__)(struct OBJGPU *, struct KernelGsp * /*this*/, NvU32); // halified (3 hals) body
void (*__kgspServiceFatalHwError__)(struct OBJGPU *, struct KernelGsp * /*this*/, NvU32); // halified (3 hals) body
void (*__kgspEccServiceEvent__)(struct OBJGPU *, struct KernelGsp * /*this*/); // halified (3 hals) body
void (*__kgspEccServiceUncorrError__)(struct OBJGPU *, struct KernelGsp * /*this*/); // halified (3 hals) body
@@ -561,6 +562,7 @@ struct KernelGsp {
NvBool bInLockdown;
NvBool bPollingForRpcResponse;
NvBool bFatalError;
NvBool bGspRmForceUnloaded;
struct CrashCatReport *pWatchdogReport;
MEMORY_DESCRIPTOR *pMemDesc_simAccessBuf;
SimAccessBuffer *pSimAccessBuf;
@@ -964,6 +966,9 @@ static inline void kgspPrintGspBinBuildId(struct OBJGPU *pGpu, struct KernelGsp
#define kgspService_FNPTR(pKernelGsp) pKernelGsp->__kgspService__
#define kgspService(pGpu, pKernelGsp) kgspService_DISPATCH(pGpu, pKernelGsp)
#define kgspService_HAL(pGpu, pKernelGsp) kgspService_DISPATCH(pGpu, pKernelGsp)
#define kgspCheckGspPoisonError_FNPTR(pKernelGsp) pKernelGsp->__kgspCheckGspPoisonError__
#define kgspCheckGspPoisonError(pGpu, pKernelGsp, intrStatus) kgspCheckGspPoisonError_DISPATCH(pGpu, pKernelGsp, intrStatus)
#define kgspCheckGspPoisonError_HAL(pGpu, pKernelGsp, intrStatus) kgspCheckGspPoisonError_DISPATCH(pGpu, pKernelGsp, intrStatus)
#define kgspServiceFatalHwError_FNPTR(pKernelGsp) pKernelGsp->__kgspServiceFatalHwError__
#define kgspServiceFatalHwError(pGpu, pKernelGsp, intrStatus) kgspServiceFatalHwError_DISPATCH(pGpu, pKernelGsp, intrStatus)
#define kgspServiceFatalHwError_HAL(pGpu, pKernelGsp, intrStatus) kgspServiceFatalHwError_DISPATCH(pGpu, pKernelGsp, intrStatus)
@@ -1278,6 +1283,10 @@ static inline NvU32 kgspService_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *
return pKernelGsp->__kgspService__(pGpu, pKernelGsp);
}
static inline NvBool kgspCheckGspPoisonError_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 intrStatus) {
return pKernelGsp->__kgspCheckGspPoisonError__(pGpu, pKernelGsp, intrStatus);
}
static inline void kgspServiceFatalHwError_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 intrStatus) {
pKernelGsp->__kgspServiceFatalHwError__(pGpu, pKernelGsp, intrStatus);
}
@@ -1693,6 +1702,8 @@ NvU32 kgspReadMailbox_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, N
NvU32 kgspService_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp);
NvBool kgspCheckGspPoisonError_GB100(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 intrStatus);
void kgspServiceFatalHwError_GB100(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 intrStatus);
void kgspEccServiceEvent_GB100(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp);
@@ -1908,6 +1919,14 @@ static inline NvU32 kgspService_474d46(struct OBJGPU *pGpu, struct KernelGsp *pK
NV_ASSERT_OR_RETURN_PRECOMP(0, 0);
}
static inline NvBool kgspCheckGspPoisonError_86b752(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 intrStatus){
NV_ASSERT_OR_RETURN_PRECOMP(0, NV_FALSE);
}
static inline NvBool kgspCheckGspPoisonError_d69453(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 intrStatus){
return NV_FALSE;
}
static inline void kgspServiceFatalHwError_f2d351(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 intrStatus){
NV_ASSERT_PRECOMP(0);
}
src/nvidia/generated/g_mem_mgr_nvoc.c
+1 -1
View File
@@ -992,7 +992,7 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, GpuHalsp
// memmgrChooseKind -- halified (2 hals) body
if (( ((chipHal_HalVarIdx >> 5) == 3UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000a000UL) )) /* ChipHal: T234D | T264D */
{
pThis->__memmgrChooseKind__ = &memmgrChooseKind_474d46;
pThis->__memmgrChooseKind__ = &memmgrChooseKind_f4fe90;
}
else
{
src/nvidia/generated/g_mem_mgr_nvoc.h
+9 -7
View File
@@ -1930,8 +1930,8 @@ static inline NV_STATUS memmgrGetCarveoutRegionInfo(POBJGPU pGpu, struct MemoryM
#define memmgrGetCompressedKind(pMemoryManager, kind, bDisablePlc) memmgrGetCompressedKind_DISPATCH(pMemoryManager, kind, bDisablePlc)
#define memmgrGetCompressedKind_HAL(pMemoryManager, kind, bDisablePlc) memmgrGetCompressedKind_DISPATCH(pMemoryManager, kind, bDisablePlc)
#define memmgrChooseKind_FNPTR(pMemoryManager) pMemoryManager->__memmgrChooseKind__
#define memmgrChooseKind(pGpu, pMemoryManager, arg3, arg4, arg5) memmgrChooseKind_DISPATCH(pGpu, pMemoryManager, arg3, arg4, arg5)
#define memmgrChooseKind_HAL(pGpu, pMemoryManager, arg3, arg4, arg5) memmgrChooseKind_DISPATCH(pGpu, pMemoryManager, arg3, arg4, arg5)
#define memmgrChooseKind(pGpu, pMemoryManager, arg3, arg4, pKind) memmgrChooseKind_DISPATCH(pGpu, pMemoryManager, arg3, arg4, pKind)
#define memmgrChooseKind_HAL(pGpu, pMemoryManager, arg3, arg4, pKind) memmgrChooseKind_DISPATCH(pGpu, pMemoryManager, arg3, arg4, pKind)
#define memmgrIsKind_FNPTR(pMemoryManager) pMemoryManager->__memmgrIsKind__
#define memmgrIsKind(pMemoryManager, arg2, arg3) memmgrIsKind_DISPATCH(pMemoryManager, arg2, arg3)
#define memmgrIsKind_HAL(pMemoryManager, arg2, arg3) memmgrIsKind_DISPATCH(pMemoryManager, arg2, arg3)
@@ -2290,8 +2290,8 @@ static inline NvU32 memmgrGetCompressedKind_DISPATCH(struct MemoryManager *pMemo
return pMemoryManager->__memmgrGetCompressedKind__(pMemoryManager, kind, bDisablePlc);
}
static inline NV_STATUS memmgrChooseKind_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_ALLOC_PAGE_FORMAT *arg3, NvU32 arg4, NvU32 *arg5) {
return pMemoryManager->__memmgrChooseKind__(pGpu, pMemoryManager, arg3, arg4, arg5);
static inline NV_STATUS memmgrChooseKind_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_ALLOC_PAGE_FORMAT *arg3, NvU32 arg4, NvU32 *pKind) {
return pMemoryManager->__memmgrChooseKind__(pGpu, pMemoryManager, arg3, arg4, pKind);
}
static inline NvBool memmgrIsKind_DISPATCH(struct MemoryManager *pMemoryManager, FB_IS_KIND_OP arg2, NvU32 arg3) {
@@ -2659,7 +2659,7 @@ NvU32 memmgrGetCompressedKind_GB202(struct MemoryManager *pMemoryManager, NvU32
NvU32 memmgrGetCompressedKind_TU102(struct MemoryManager *pMemoryManager, NvU32 kind, NvBool bDisablePlc);
NV_STATUS memmgrChooseKind_TU102(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_ALLOC_PAGE_FORMAT *arg3, NvU32 arg4, NvU32 *arg5);
NV_STATUS memmgrChooseKind_TU102(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_ALLOC_PAGE_FORMAT *arg3, NvU32 arg4, NvU32 *pKind);
NvBool memmgrIsKind_GB20B(struct MemoryManager *pMemoryManager, FB_IS_KIND_OP arg2, NvU32 arg3);
@@ -3057,8 +3057,10 @@ static inline NvU32 memmgrGetCompressedKind_d1515c(struct MemoryManager *pMemory
NV_ASSERT_OR_RETURN_PRECOMP(0, kind);
}
static inline NV_STATUS memmgrChooseKind_474d46(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_ALLOC_PAGE_FORMAT *arg3, NvU32 arg4, NvU32 *arg5){
NV_ASSERT_OR_RETURN_PRECOMP(0, 0);
static inline NV_STATUS memmgrChooseKind_f4fe90(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_ALLOC_PAGE_FORMAT *arg3, NvU32 arg4, NvU32 *pKind){
NV_ASSERT_OR_RETURN_PRECOMP(pKind != ((void *)0), NV_ERR_INVALID_ARGUMENT);
*pKind = 0;
return NV_OK;
}
static inline NvU32 memmgrGetMessageKind_b2b553(OBJGPU *pGpu, struct MemoryManager *pMemoryManager){
src/nvidia/src/kernel/gpu/gsp/arch/blackwell/kernel_gsp_gb100.c
+55 -11
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -152,6 +152,59 @@ kgspGetGspRmBootUcodeStorage_GB100
kgspGetGspRmBootUcodeStorage_GA102(pGpu, pKernelGsp, ppBinStorageImage, ppBinStorageDesc);
}
/*!
* Check if GSP has been poisoned
*
* @param[in] pGpu OBJGPU pointer
* @param[in] pKernelGsp KernelGsp pointer
* @param[in] intrStatus Interrupt status
*
* @return NV_TRUE if GSP has been poisoned, NV_FALSE otherwise
*/
NvBool
kgspCheckGspPoisonError_GB100
(
OBJGPU *pGpu,
KernelGsp *pKernelGsp,
NvU32 intrStatus
)
{
NvU32 errorStatus = 0;
if (!FLD_TEST_DRF(_PGSP_FALCON, _IRQSTAT, _FATAL_ERROR, _TRUE, intrStatus))
{
return NV_FALSE;
}
KernelFalcon *pKernelFlcn = staticCast(pKernelGsp, KernelFalcon);
if (kflcnGetFatalHwErrorStatus_HAL(pGpu, pKernelFlcn, &errorStatus) != NV_OK)
{
NV_PRINTF(LEVEL_ERROR, "NV_PGSP_FALCON_IRQSTAT_FATAL_ERROR unknown error pending\n");
MODS_ARCH_ERROR_PRINTF("NV_PGSP_FALCON_IRQSTAT_FATAL_ERROR unknown error pending\n");
return NV_FALSE;
}
// Poison error
if (FLD_TEST_DRF(_PGSP, _RISCV_FAULT_CONTAINMENT_SRCSTAT, _GLOBAL_MEM, _FAULTED, errorStatus))
{
//
// Assert since this interrupt can't be cleared without a
// GPU reset and we shouldn't see this if poison is disabled
//
if (!gpuIsGlobalPoisonFuseEnabled(pGpu))
{
NV_ASSERT_FAILED("GSP poison pending when poison is disabled");
}
return NV_TRUE;
}
return NV_FALSE;
}
/*!
* Handle GSP Fatal Errors
*/
@@ -202,21 +255,12 @@ kgspServiceFatalHwError_GB100
#endif // NV_PRINTF_STRINGS_ALLOWED
// Poison error
if (FLD_TEST_DRF(_PGSP, _RISCV_FAULT_CONTAINMENT_SRCSTAT, _GLOBAL_MEM, _FAULTED, errorCode))
if (kgspCheckGspPoisonError_HAL(pGpu, pKernelGsp, intrStatus))
{
NV_ERROR_CONT_LOCATION loc = { 0 };
loc.locType = NV_ERROR_CONT_LOCATION_TYPE_NONE;
//
// Assert since this interrupt can't be cleared without a
// GPU reset and we shouldn't see this if poison is disabled
//
if (!gpuIsGlobalPoisonFuseEnabled(pGpu))
{
NV_ASSERT_FAILED("GSP poison pending when poison is disabled");
}
NV_ASSERT_OK(gpuUpdateErrorContainmentState_HAL(pGpu, NV_ERROR_CONT_ERR_ID_E24_GSP_POISON, loc, NULL));
}
else
src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c
+64 -15
View File
@@ -101,7 +101,6 @@
#define RPC_HDR ((rpc_message_header_v*)(pRpc->message_buffer))
#define GSP_SLOWNESS 0
struct MIG_CI_UPDATE_CALLBACK_PARAMS
{
@@ -200,6 +199,8 @@ static void _kgspDumpRmState(OBJGPU *pGpu, KernelGsp *pKernelGsp);
static NvU32 _kgspClassifyGspTimeout(OBJGPU *, KernelGsp *, OBJRPC *, NvU32, NvU32, NvBool, NvBool);
static NvBool _kgspCheckGspFatalHwError(OBJGPU *pGpu, KernelGsp *pKernelGsp);
static void _kgspInitGpuProperties(OBJGPU *);
static NV_STATUS _kgspDumpEngineFunc(OBJGPU*, PRB_ENCODER*, NVD_STATE*, void*);
@@ -2237,10 +2238,10 @@ _kgspHeartbeatIsInitialized(KernelGsp *pKernelGsp)
(pKernelGsp->libosHeartbeatTimeoutMs != 0);
}
static NV_STATUS
static void
_kgspHeartbeatInit(OBJGPU *pGpu, KernelGsp *pKernelGsp)
{
NV_ASSERT_OR_RETURN(kgspIsHeartbeatSupported(pGpu), NV_ERR_NOT_SUPPORTED);
NV_ASSERT_OR_RETURN_VOID(kgspIsHeartbeatSupported(pGpu));
NvU64 defaultTimeoutMs = pGpu->timeoutData.defaultus / 1000;
@@ -2263,8 +2264,14 @@ _kgspHeartbeatInit(OBJGPU *pGpu, KernelGsp *pKernelGsp)
// Since GSP-RM requests the DMA, and GSP-RM should be confined to default timeout, also
// set libos heartbeat timeout to 1.25 times the default timeout.
pKernelGsp->libosHeartbeatTimeoutMs = defaultTimeoutMs + ((defaultTimeoutMs / 10) * 3);
}
return NV_OK;
static void
_kgspHeartbeatDisable(OBJGPU *pGpu, KernelGsp *pKernelGsp)
{
// Disable heartbeat checking for GSP-RM and Libos
pKernelGsp->gspRmHeartbeatTimeoutMs = 0;
pKernelGsp->libosHeartbeatTimeoutMs = 0;
}
static NvBool
@@ -2392,10 +2399,7 @@ _kgspLogRpcTimeout
pHistoryEntry->data[0],
pHistoryEntry->data[1]);
if (errorNum == GSP_SLOWNESS)
{
_kgspDumpRmState(pGpu, pKernelGsp);
}
_kgspDumpRmState(pGpu, pKernelGsp);
_kgspLogGspTraceCrashBuffer(pGpu, pKernelGsp);
kflcnCoreDumpNondestructive(pGpu, pKernelFlcn, 2);
@@ -2640,6 +2644,36 @@ _kgspIsTimeoutFatal(
return errorNum != GSP_RPC_TIMEOUT;
}
/*!
* Check if there is any pending fatal HW error like GSP Poison Error that could have caused GSP to timeout
*/
static NvBool
_kgspCheckGspFatalHwError
(
OBJGPU *pGpu,
KernelGsp *pKernelGsp
)
{
NvU32 intrStatus;
KernelFalcon *pKernelFalcon = staticCast(pKernelGsp, KernelFalcon);
// Check if GSP has been poisoned. Mark device for reset if so.
intrStatus = kflcnGetPendingHostInterrupts(pGpu, pKernelFalcon);
if(kgspCheckGspPoisonError_HAL(pGpu, pKernelGsp, intrStatus))
{
//
// gpuCheckEccCounts_HAL should be able to detect and log Xid 140 (UNRECOVERABLE_ECC_ERROR_ESCAPE)
// but the functions it uses to get ecc error counts aren't wired to the right HAL for GB100+,
// bug 5816620 will fix it. Revisit this function and remove nvErrorLog_va once bug 5816620 is fixed.
//
nvErrorLog_va(pGpu, UNRECOVERABLE_ECC_ERROR_ESCAPE, "Poison error in GSP.");
gpuCheckEccCounts_HAL(pGpu);
gpuMarkDeviceForReset(pGpu);
return NV_TRUE;
}
return NV_FALSE;
}
/*!
* GSP client RM RPC poll routine
*/
@@ -2811,6 +2845,12 @@ _kgspRpcRecvPoll
_kgspRpcIncrementTimeoutCountAndRateLimitPrints(pGpu, pRpc);
if(_kgspCheckGspFatalHwError(pGpu, pKernelGsp))
{
// We don't have to classify timeouts since we know for sure it is a fatal HW error.
goto done;
}
isGspRmHeartbeatTimedOut = _kgspHeartbeatIsGspRmHeartbeatTimedOut(pGpu, pKernelGsp);
isLibosHeartbeatTimedOut = _kgspHeartbeatIsLibosHeartbeatTimedOut(pGpu, pKernelGsp);
@@ -3908,7 +3948,7 @@ static void _kgspDumpRmState(OBJGPU *pGpu, KernelGsp *pKernelGsp)
RMTIMEOUT timeout;
NV_STATUS status = NV_OK;
NvU32 i = 0;
NvU64 timeoutUs = pGpu->timeoutData.defaultus - pGpu->timeoutData.defaultus/2;
NvU64 timeoutUs = pGpu->timeoutData.defaultus / 10;
gpuSetTimeout(pGpu, timeoutUs, &timeout, GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE);
@@ -5015,12 +5055,6 @@ kgspInitRm_IMPL
goto done;
}
// GSP starts sending heartbeat after rminit, treat heartbeat values as valid at this point
if (kgspIsHeartbeatSupported(pGpu))
{
NV_ASSERT_OK_OR_GOTO(status, _kgspHeartbeatInit(pGpu, pKernelGsp), done);
}
// at this point we should be able to exchange RPCs with RM offload task
NV_RM_RPC_SET_GUEST_SYSTEM_INFO(pGpu, status);
if (status != NV_OK)
@@ -5095,6 +5129,12 @@ kgspUnloadRm_IMPL
NvBool bInPmTransition = (unloadMode != KGSP_UNLOAD_MODE_NORMAL);
NvBool bGc6Entering = (unloadMode == KGSP_UNLOAD_MODE_GC6_ENTER);
if (pKernelGsp->bGspRmForceUnloaded)
{
NV_PRINTF(LEVEL_ERROR, "skipping attempt to unload GSP-RM after force unload\n");
return NV_OK;
}
NV_PRINTF(LEVEL_INFO, "unloading GSP-RM\n");
NV_RM_RPC_UNLOADING_GUEST_DRIVER(pGpu, rpcStatus, bInPmTransition, bGc6Entering, newPmLevel);
@@ -5107,6 +5147,9 @@ kgspUnloadRm_IMPL
// Wait for GSP-RM processor to suspend
kgspWaitForProcessorSuspend_HAL(pGpu, pKernelGsp);
// Disable heartbeat checking for GSP-RM and Libos
_kgspHeartbeatDisable(pGpu, pKernelGsp);
// Dump GSP-RM logs and reset before proceeding with the rest of teardown
kgspDumpGspLogs(pKernelGsp, (pKernelGsp->preserveLogs != NV_REG_STR_RM_GSP_PRESERVE_UNLOAD_LOGS_DISABLE));
@@ -6069,6 +6112,12 @@ kgspWaitForRmInitDone_IMPL
pGpu->gspRmInitialized = NV_TRUE;
// GSP starts sending heartbeat after rminit, treat heartbeat values as valid at this point
if (kgspIsHeartbeatSupported(pGpu))
{
_kgspHeartbeatInit(pGpu, pKernelGsp);
}
// Set D3Hot info let Kernel-RM reports it to KMD
RPC_PARAMS(init_done, _v17_00);
NV_PRINTF(LEVEL_INFO, "GSP-RM reports bIsD3Hot = 0x%08x\n", rpc_params->bIsD3Hot);
src/nvidia/src/kernel/gpu/mem_mgr/dma.c
-33
View File
@@ -649,39 +649,6 @@ deviceCtrlCmdDmaUnsetPageDirectory_IMPL
return status;
}
//
// deviceCtrlCmdDmaSetPteInfo_IMPL
//
// Lock Requirements:
// Assert that API lock and GPUs lock held on entry
//
NV_STATUS
deviceCtrlCmdDmaSetPteInfo_IMPL
(
Device *pDevice,
NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS *pParams
)
{
OBJGPU *pGpu = GPU_RES_GET_GPU(pDevice);
OBJVASPACE *pVAS = NULL;
NV_STATUS status = NV_OK;
NV_ASSERT_OR_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner(), NV_ERR_INVALID_LOCK_STATE);
NV_CHECK_OK_OR_RETURN(LEVEL_WARNING,
vaspaceGetByHandleOrDeviceDefault(RES_GET_CLIENT(pDevice), RES_GET_HANDLE(pDevice),
pParams->hVASpace, &pVAS));
status = vaspaceSetPteInfo(pVAS, pGpu, pParams);
if (status != NV_OK)
{
NV_PRINTF(LEVEL_ERROR, "vaspaceGetPteInfo failed\n");
NV_ASSERT(0);
}
return status;
}
//
// deviceCtrlCmdDmaFlush_IMPL
//
src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c
+1
View File
@@ -642,6 +642,7 @@ subdeviceCtrlCmdGpuForceGspUnload_IMPL
rmStatus = kgspUnloadRm(pGpu, pKernelGsp, KGSP_UNLOAD_MODE_NORMAL, (GPU_STATE_FLAGS_FAST_UNLOAD|GPU_STATE_FLAGS_FORCE_GSP_UNLOAD));
pKernelGsp->bFatalError = NV_TRUE;
pKernelGsp->bGspRmForceUnloaded = NV_TRUE;
return rmStatus;;
}
src/nvidia/src/kernel/mem_mgr/fabric_vaspace.c
+14 -1
View File
@@ -410,7 +410,20 @@ fabricvaspaceAllocNonContiguous_IMPL
NV_ASSERT_OR_RETURN(NV_IS_ALIGNED64(align, pageSize), NV_ERR_INVALID_ARGUMENT);
NV_ASSERT_OR_RETURN(NV_IS_ALIGNED64(size, pageSize), NV_ERR_INVALID_ARGUMENT);
pageCount = (NvU32)(size / pageSize);
{
//
// Calculate page count and check for integer truncation.
// size / pageSize could exceed NvU32 max, causing undersized allocation.
//
NvU64 pageCount64 = size / pageSize;
if (pageCount64 > NV_U32_MAX)
{
NV_PRINTF(LEVEL_ERROR,
"Page count 0x%llx exceeds NvU32 max\n", pageCount64);
return NV_ERR_INVALID_ARGUMENT;
}
pageCount = (NvU32)pageCount64;
}
// Check if heap can satisfy the request.
NV_ASSERT_OK_OR_RETURN(fabricvaspaceGetFreeHeap(pFabricVAS, &freeSize));
src/nvidia/src/kernel/mem_mgr/mem_fabric_import_ref.c
+5
View File
@@ -203,6 +203,11 @@ memoryfabricimportedrefCtrlValidate_IMPL
(pMemoryFabricImportedRef->numUpdatedPfns >= pParams->totalPfns))
return NV_ERR_INVALID_ARGUMENT;
if (pParams->numPfns > NV_ARRAY_ELEMENTS(pParams->pfnArray))
{
return NV_ERR_INVALID_ARGUMENT;
}
if (!portSafeAddU64(pParams->offset, pParams->numPfns, &result) ||
(result > pParams->totalPfns))
return NV_ERR_OUT_OF_RANGE;
src/nvidia/src/kernel/platform/chipset/chipset_pcie.c
+15 -6
View File
@@ -268,7 +268,7 @@ objClInitPcieChipset(OBJGPU *pGpu, OBJCL *pCl)
{
domain = gpuGetDomain(pGpu);
if (clStoreBusTopologyCache(pCl, domain, PCI_MAX_BUSES) != NV_OK)
if (clStoreBusTopologyCache(pGpu, pCl, domain, PCI_MAX_BUSES) != NV_OK)
{
return NV_ERR_GENERIC;
}
@@ -1503,7 +1503,7 @@ clFindP2PBrdg_IMPL
}
// If the bus topology is not cached, do it here
if (clStoreBusTopologyCache(pCl, domain, secBus16) != NV_OK)
if (clStoreBusTopologyCache(pGpu, pCl, domain, secBus16) != NV_OK)
{
return NULL;
}
@@ -2584,9 +2584,10 @@ clFreeBusTopologyCache_IMPL(OBJCL *pCl)
NV_STATUS
clStoreBusTopologyCache_IMPL
(
OBJCL *pCl,
NvU32 domain,
NvU16 secBus
OBJGPU *pGpu,
OBJCL *pCl,
NvU32 domain,
NvU16 secBus
)
{
void *handle;
@@ -2595,6 +2596,12 @@ clStoreBusTopologyCache_IMPL
NvS8 device = 0, func = 0;
NvU16 pciSubBaseClass;
PBUSTOPOLOGYINFO pBusTopologyInfo = NULL, pBusTopologyInfoLast = NULL;
NvBool bGpuArchIsZeroFb = NV_FALSE;
if ((pGpu != NULL) && (pGpu->pGpuArch != NULL))
{
bGpuArchIsZeroFb = pGpu->pGpuArch->bGpuArchIsZeroFb;
}
if (pCl->pBusTopologyInfo)
{
@@ -2684,9 +2691,11 @@ clStoreBusTopologyCache_IMPL
pBusTopologyInfo->busInfo.subdeviceID = osPciReadWord(handle, PCI_COMMON_SUBSYSTEM_ID);
pBusTopologyInfo->busInfo.revisionID = osPciReadByte(handle, PCI_HEADER_TYPE0_REVISION_ID);
// Bug 5889487 - Allow 3D controller dGPU should be validated in rmCheckAioPreApprovedList
// The bGpuArchIsZeroFb is set only for iGPU.
if ((pciSubBaseClass == PCI_COMMON_CLASS_SUBBASECLASS_P2P) ||
(pciSubBaseClass == PCI_COMMON_CLASS_SUBBASECLASS_HOST) ||
(pciSubBaseClass == PCI_COMMON_CLASS_SUBBASECLASS_3DCTRL))
(bGpuArchIsZeroFb && (pciSubBaseClass == PCI_COMMON_CLASS_SUBBASECLASS_3DCTRL)))
{
pBusTopologyInfo->secBus = (NvU8)osPciReadByte(handle, PCI_TYPE_1_SECONDARY_BUS_NUMBER);
pBusTopologyInfo->bVgaAdapter = NV_FALSE;
src/nvidia/src/kernel/rmapi/nv_gpu_ops.c
+4 -1
View File
@@ -8991,7 +8991,10 @@ NV_STATUS nvGpuOpsSetPageDirectory(struct gpuAddressSpace *vaSpace,
// RM clients must not unmap this address, and instead rely on RM to unmap
// it when nvGpuOpsUnsetPageDirectory() is called.
//
*dmaAddress = memdescGetPhysAddr(vaspaceGetPageDirBase(pVAS, pGpu), AT_GPU, 0);
if (status == NV_OK)
{
*dmaAddress = memdescGetPhysAddr(vaspaceGetPageDirBase(pVAS, pGpu), AT_GPU, 0);
}
if (vaspaceIsExternallyOwned(pVAS))
{
src/nvidia/src/kernel/rmapi/rmapi_utils.c
+1
View File
@@ -238,6 +238,7 @@ NvBool rmapiutilSkipErrorMessageForUnsupportedVgpuGuestControl(OBJGPU *pGpu, NvU
case NV2080_CTRL_CMD_NVLINK_GET_PLATFORM_INFO:
case NV402C_CTRL_CMD_I2C_GET_PORT_SPEED:
case NV90E7_CTRL_CMD_BBX_GET_LAST_FLUSH_TIME:
case NV2080_CTRL_CMD_ECC_GET_REPAIR_STATUS:
case NV2080_CTRL_CMD_ECC_GET_UNREPAIRABLE_MEMORY_FLAG:
return NV_TRUE;
src/nvidia/src/libraries/resserv/src/rs_server.c
+4 -2
View File
@@ -1699,6 +1699,7 @@ serverCopyResource
status = clientGetResourceRef(pClientSrc, pParams->hResourceSrc, &pResourceRefSrc);
if (status != NV_OK)
{
NV_PRINTF(LEVEL_NOTICE, "Failed to find handle 0x%x under client 0x%x\n", pParams->hResourceSrc, pParams->hClientSrc);
goto done;
}
@@ -1711,7 +1712,8 @@ serverCopyResource
status = clientGetResourceRef(pClientDst, pParams->hParentDst, &pParams->pDstParentRef);
if (status != NV_OK)
{
return status;
NV_PRINTF(LEVEL_NOTICE, "Failed to find handle 0x%x under client 0x%x\n", pParams->hParentDst, pParams->hClientDst);
goto done;
}
if (!resCanCopy(pResourceRefSrc->pResource))
@@ -1730,7 +1732,7 @@ serverCopyResource
status = serverUpdateLockFlagsForCopy(pServer, pParams);
if (status != NV_OK)
return status;
goto done;
status = serverResLock_Prologue(pServer, LOCK_ACCESS_WRITE, pParams->pLockInfo, &releaseFlags, 0);
if (status != NV_OK)
version.mk
+2 -2
View File
@@ -1,5 +1,5 @@
NVIDIA_VERSION = 595.58.03
NVIDIA_NVID_VERSION = 595.58.03
NVIDIA_VERSION = 595.71.05
NVIDIA_NVID_VERSION = 595.71.05
NVIDIA_NVID_EXTRA =
# This file.