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610.57.04

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This commit is contained in:
Maneet Singh
2026-08-03 14:41:34 -07:00
parent 452cec62d8
commit e4a5faa256
114 changed files with 202606 additions and 201512 deletions
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README.md
+7 -3
View File
@@ -1,7 +1,7 @@
# NVIDIA Linux Open GPU Kernel Module Source
This is the source release of the NVIDIA Linux open GPU kernel modules,
version 610.43.03.
version 610.57.04.
## How to Build
@@ -17,7 +17,7 @@ as root:
Note that the kernel modules built here must be used with GSP
firmware and user-space NVIDIA GPU driver components from a corresponding
610.43.03 driver release. This can be achieved by installing
610.57.04 driver release. This can be achieved by installing
the NVIDIA GPU driver from the .run file using the `--no-kernel-modules`
option. E.g.,
@@ -185,7 +185,7 @@ table below).
For details on feature support and limitations, see the NVIDIA GPU driver
end user README here:
https://us.download.nvidia.com/XFree86/Linux-x86_64/610.43.03/README/kernel_open.html
https://us.download.nvidia.com/XFree86/Linux-x86_64/610.57.04/README/kernel_open.html
For vGPU support, please refer to the README.vgpu packaged in the vGPU Host
Package for more details.
@@ -1018,6 +1018,10 @@ Subsystem Device ID.
| NVIDIA RTX PRO 500 Blackwell Generation Laptop GPU | 2DB9 |
| NVIDIA GeForce RTX 5050 Laptop GPU | 2DD8 |
| NVIDIA RTX PRO 500 Blackwell Embedded GPU | 2DF9 |
| NVIDIA RTX Spark N1X (6144-core Blackwell RTX GPU) | 2E03 1043 1484 |
| NVIDIA RTX Spark N1X (6144-core Blackwell RTX GPU) | 2E03 1043 3309 |
| NVIDIA RTX Spark N1X (5120-core Blackwell RTX GPU) | 2E06 1043 1484 |
| NVIDIA RTX Spark N1X (5120-core Blackwell RTX GPU) | 2E06 1043 3309 |
| NVIDIA GB10 | 2E12 10DE 21EC |
| NVIDIA GeForce RTX 5070 | 2F04 |
| NVIDIA GeForce RTX 5060 | 2F06 |
kernel-open/Kbuild
+1 -1
View File
@@ -79,7 +79,7 @@ ccflags-y += -I$(src)/common/inc
ccflags-y += -I$(src)
ccflags-y += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-format-extra-args
ccflags-y += -D__KERNEL__ -DMODULE -DNVRM
ccflags-y += -DNV_VERSION_STRING=\"610.43.03\"
ccflags-y += -DNV_VERSION_STRING=\"610.57.04\"
# Include and link Tegra out-of-tree modules.
ifneq ($(wildcard /usr/src/nvidia/nvidia-public),)
kernel-open/common/inc/nv-linux.h
+39 -24
View File
@@ -169,6 +169,9 @@
#include <linux/efi.h> /* efi_enabled */
#include <linux/fb.h> /* fb_info struct */
#include <linux/screen_info.h> /* screen_info */
#if defined(NV_LINUX_SYSFB_H_PRESENT)
#include <linux/sysfb.h> /* sysfb_primary_display */
#endif
#if !defined(CONFIG_PCI)
#warning "Attempting to build driver for a platform with no PCI support!"
@@ -252,6 +255,10 @@ NV_STATUS nvos_forward_error_to_cray(struct pci_dev *, NvU32,
user_function, NULL, args)
#endif
#if defined(NV_LINUX_IOMMU_DMA_H_PRESENT)
#include <linux/iommu-dma.h>
#endif
#define NV_PAGE_COUNT(page) \
((unsigned int)page_count(page))
@@ -938,6 +945,11 @@ typedef struct nv_alloc_s {
*/
static inline NvBool nv_is_dma_direct(struct device *dev)
{
#if defined(NV_USE_DMA_IOMMU_PRESENT)
if (use_dma_iommu(dev))
return NV_FALSE;
#endif
return get_dma_ops(dev) == NULL;
}
@@ -1041,6 +1053,7 @@ typedef struct nv_dma_map_s {
NvU64 page_count;
NvBool contiguous;
NvU32 cache_type;
NvBool bReadOnlyDeviceMap;
struct sg_table *import_sgt;
union
@@ -1711,6 +1724,25 @@ typedef enum
#else
#include <linux/gpio/driver.h>
static inline int __to_hwgpio(const struct gpio_device *gdev,
const struct of_phandle_args *gpiospec)
{
#if defined(CONFIG_OF_GPIO)
/*
* Use the chip's of_xlate callback to translate the DT GPIO
* specifier into a linear offset. Tegra GPIO controllers encode
* port and pin in args[0] and of_xlate sums per-port pin counts
* to produce the real offset.
*/
struct gpio_chip *chip = gpio_device_get_chip(gdev);
if (chip->of_xlate)
return chip->of_xlate(chip, gpiospec, NULL);
#endif
return gpiospec->args[0];
}
/*
* of_get_named_gpio() was removed along with linux/of_gpio.h by commit
* 51aaf65bbd21 ("gpio: of: Remove <linux/of_gpio.h>"). Provide a compat
@@ -1722,7 +1754,7 @@ static inline int of_get_named_gpio(const struct device_node *np,
struct of_phandle_args gpiospec;
struct gpio_device *gdev;
struct gpio_desc *desc;
int ret;
int ret, hwgpio;
if (!np)
return -ENOENT;
@@ -1737,30 +1769,13 @@ static inline int of_get_named_gpio(const struct device_node *np,
if (!gdev)
return -EPROBE_DEFER;
/*
* Use the chip's of_xlate callback to translate the DT GPIO
* specifier into a linear offset. Tegra GPIO controllers encode
* port and pin in args[0] and of_xlate sums per-port pin counts
* to produce the real offset.
*/
{
struct gpio_chip *chip = gpio_device_get_chip(gdev);
int hwgpio;
#if defined(CONFIG_OF_GPIO)
if (chip->of_xlate)
hwgpio = chip->of_xlate(chip, &gpiospec, NULL);
else
#endif
hwgpio = gpiospec.args[0];
if (hwgpio < 0) {
gpio_device_put(gdev);
return hwgpio;
}
desc = gpio_device_get_desc(gdev, hwgpio);
hwgpio = __to_hwgpio(gdev, &gpiospec);
if (hwgpio < 0) {
gpio_device_put(gdev);
return hwgpio;
}
desc = gpio_device_get_desc(gdev, hwgpio);
gpio_device_put(gdev);
if (IS_ERR(desc))
kernel-open/common/inc/nv.h
+9 -2
View File
@@ -660,6 +660,8 @@ struct nv_file_private_t
nv_file_private_t * PORT_ATOMIC ctl_nvfp;
void *ctl_nvfp_priv;
PORT_ATOMIC NvU32 register_or_refcount;
// In-flight nv_post_event() calls using this file private.
PORT_ATOMIC NvS32 event_posting_refcount;
//
// True if a client or an event was ever allocated on this fd.
@@ -668,6 +670,11 @@ struct nv_file_private_t
NvBool bCleanupRmapi;
};
static inline NvS32 nv_event_posting_refcount_read(nv_file_private_t *nvfp)
{
return *((volatile NvS32 *)&nvfp->event_posting_refcount);
}
// Forward define the gpu ops structures
typedef struct gpuSession *nvgpuSessionHandle_t;
typedef struct gpuDevice *nvgpuDeviceHandle_t;
@@ -969,9 +976,9 @@ void NV_API_CALL nv_unregister_sgt (nv_state_t *, struct sg_table
NV_STATUS NV_API_CALL nv_register_phys_pages (nv_state_t *, NvU64 *, NvU64, NvU32, void **);
void NV_API_CALL nv_unregister_phys_pages (nv_state_t *, void *);
NV_STATUS NV_API_CALL nv_dma_map_sgt (nv_dma_device_t *, NvU64, NvU64 *, NvU32, void **);
NV_STATUS NV_API_CALL nv_dma_map_sgt (nv_dma_device_t *, NvU64, NvU64 *, NvU32, NvBool, void **);
NV_STATUS NV_API_CALL nv_dma_map_alloc (nv_dma_device_t *, NvU64, NvU64 *, NvBool, void **);
NV_STATUS NV_API_CALL nv_dma_map_alloc (nv_dma_device_t *, NvU64, NvU64 *, NvBool, NvBool, void **);
NV_STATUS NV_API_CALL nv_dma_unmap_alloc (nv_dma_device_t *, NvU64, NvU64 *, void **);
NV_STATUS NV_API_CALL nv_dma_map_peer (nv_dma_device_t *, nv_dma_device_t *, NvU8, NvU64, NvU64 *);
kernel-open/conftest.sh
+39 -4
View File
@@ -1175,14 +1175,15 @@ compile_test() {
#
CODE="
#include <linux/pci.h>
#if defined(NV_LINUX_NVGRACE_EGM_H_PRESENT)
#include <linux/nvgrace-egm.h>
#endif
void conftest_egm_module_helper_api_present() {
struct pci_dev *pdev = NULL;
register_egm_node(pdev);
unregister_egm_node(pdev);
register_egm_node();
unregister_egm_node();
}
"
compile_check_conftest "$CODE" "NV_EGM_MODULE_HELPER_API_PRESENT" "" "types"
compile_check_conftest "$CODE" "NV_EGM_MODULE_HELPER_API_PRESENT" "" "functions"
;;
egm_bad_pages_handling_support)
@@ -5216,6 +5217,40 @@ compile_test() {
compile_check_conftest "$CODE" "NV_DRM_COLOROP_HAS_FUNCS" "" "types"
;;
use_dma_iommu)
#
# Determine if use_dma_iommu() function is present.
#
# Added by commit 19156263cb1f ("dma-mapping: use IOMMU DMA
# calls for common alloc/free page calls") in 6.12
#
CODE="
#if defined(NV_LINUX_IOMMU_DMA_H_PRESENT)
#include <linux/iommu-dma.h>
#endif
void conftest_use_dma_iommu(void) {
use_dma_iommu();
}"
compile_check_conftest "$CODE" "NV_USE_DMA_IOMMU_PRESENT" "" "functions"
;;
drm_atomic_commit_struct_present)
#
# Determine if 'struct drm_atomic_state' has been renamed to
# 'struct drm_atomic_commit'.
#
# Renamed by commit 5164f7e7ff8e ("drm: Rename struct
# drm_atomic_state to drm_atomic_commit"), expected in Linux v7.2.
#
CODE="
#include <drm/drm_atomic.h>
struct drm_atomic_commit state;"
compile_check_conftest "$CODE" "NV_DRM_ATOMIC_COMMIT_STRUCT_PRESENT" "" "types"
;;
# When adding a new conftest entry, please use the correct format for
# specifying the relevant upstream Linux kernel commit. Please
# avoid specifying -rc kernels, and only use SHAs that actually exist
kernel-open/header-presence-tests.mk
+4 -1
View File
@@ -39,11 +39,14 @@ NV_HEADER_PRESENCE_TESTS = \
linux/stdarg.h \
linux/iosys-map.h \
linux/vfio_pci_core.h \
linux/nvgrace-egm.h \
linux/cc_platform.h \
linux/slub_def.h \
linux/of_gpio.h \
asm/cpufeature.h \
asm/mshyperv.h \
crypto/sig.h \
drm/drm_colorop.h
drm/drm_colorop.h \
linux/iommu-dma.h \
linux/sysfb.h
kernel-open/nvidia-drm/nvidia-drm-color-pipeline.c
+1 -1
View File
@@ -289,7 +289,7 @@ failed:
static int plane_update_state_from_colorops(struct drm_plane *plane,
struct drm_plane_state *plane_state)
{
struct drm_atomic_state *state = plane_state->state;
nv_drm_atomic_state_base_t *state = plane_state->state;
struct nv_drm_plane_state *nv_plane_state = to_nv_drm_plane_state(plane_state);
struct nv_drm_colorop *nv_colorop;
struct nv_drm_color_pipeline *pipeline;
kernel-open/nvidia-drm/nvidia-drm-connector.c
+1 -1
View File
@@ -500,7 +500,7 @@ static const NvU32 __nv_drm_connector_supported_colorspaces =
#if defined(NV_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY_PRESENT)
static int
__nv_drm_connector_atomic_check(struct drm_connector *connector,
struct drm_atomic_state *state)
nv_drm_atomic_state_base_t *state)
{
struct drm_connector_state *new_connector_state =
drm_atomic_get_new_connector_state(state, connector);
kernel-open/nvidia-drm/nvidia-drm-crtc.c
+6 -6
View File
@@ -1604,16 +1604,16 @@ static int __nv_drm_cursor_atomic_check(struct drm_plane *plane,
return 0;
}
#if defined(NV_DRM_PLANE_ATOMIC_CHECK_HAS_ATOMIC_STATE_ARG)
#if defined(NV_DRM_PLANE_ATOMIC_CHECK_HAS_FULL_STATE_ARG)
static int nv_drm_plane_atomic_check(struct drm_plane *plane,
struct drm_atomic_state *state)
nv_drm_atomic_state_base_t *state)
#else
static int nv_drm_plane_atomic_check(struct drm_plane *plane,
struct drm_plane_state *plane_state)
#endif
{
struct nv_drm_plane *nv_plane = to_nv_plane(plane);
#if defined(NV_DRM_PLANE_ATOMIC_CHECK_HAS_ATOMIC_STATE_ARG)
#if defined(NV_DRM_PLANE_ATOMIC_CHECK_HAS_FULL_STATE_ARG)
struct drm_plane_state *plane_state =
drm_atomic_get_new_plane_state(state, plane);
#endif
@@ -2608,15 +2608,15 @@ static int color_mgmt_config_set_luts(struct nv_drm_crtc_state *nv_crtc_state,
* the 'nv_drm_crtc_state::req_config', that is fine because 'nv_drm_crtc_state'
* will be discarded if ->atomic_check() fails.
*/
#if defined(NV_DRM_CRTC_ATOMIC_CHECK_HAS_ATOMIC_STATE_ARG)
#if defined(NV_DRM_CRTC_ATOMIC_CHECK_HAS_FULL_STATE_ARG)
static int nv_drm_crtc_atomic_check(struct drm_crtc *crtc,
struct drm_atomic_state *state)
nv_drm_atomic_state_base_t *state)
#else
static int nv_drm_crtc_atomic_check(struct drm_crtc *crtc,
struct drm_crtc_state *crtc_state)
#endif
{
#if defined(NV_DRM_CRTC_ATOMIC_CHECK_HAS_ATOMIC_STATE_ARG)
#if defined(NV_DRM_CRTC_ATOMIC_CHECK_HAS_FULL_STATE_ARG)
struct drm_crtc_state *crtc_state =
drm_atomic_get_new_crtc_state(state, crtc);
#endif
kernel-open/nvidia-drm/nvidia-drm-drv.c
+7 -7
View File
@@ -987,7 +987,7 @@ static void nv_drm_master_set(struct drm_device *dev,
static
int nv_drm_reset_input_colorspace(struct drm_device *dev)
{
struct drm_atomic_state *state;
nv_drm_atomic_state_base_t *state;
struct drm_plane_state *plane_state;
struct drm_plane *plane;
struct nv_drm_plane_state *nv_drm_plane_state;
@@ -996,7 +996,7 @@ int nv_drm_reset_input_colorspace(struct drm_device *dev)
bool do_reset = false;
NvU32 flags = 0;
state = drm_atomic_state_alloc(dev);
state = nv_drm_atomic_state_base_alloc(dev);
if (!state)
return -ENOMEM;
@@ -1027,7 +1027,7 @@ int nv_drm_reset_input_colorspace(struct drm_device *dev)
}
out:
drm_atomic_state_put(state);
nv_drm_atomic_state_base_put(state);
drm_modeset_drop_locks(&ctx);
drm_modeset_acquire_fini(&ctx);
@@ -1435,7 +1435,7 @@ static int nv_drm_grant_permission_ioctl(struct drm_device *dev, void *data,
}
static int
nv_drm_atomic_disable_connector(struct drm_atomic_state *state,
nv_drm_atomic_disable_connector(nv_drm_atomic_state_base_t *state,
struct nv_drm_connector *nv_connector)
{
struct drm_crtc_state *crtc_state;
@@ -1468,7 +1468,7 @@ static int nv_drm_revoke_modeset_permission(struct drm_device *dev,
struct drm_file *filep, NvU32 dpyId)
{
struct drm_modeset_acquire_ctx *pctx;
struct drm_atomic_state *state;
nv_drm_atomic_state_base_t *state;
struct drm_connector *connector;
struct drm_crtc *crtc;
int ret = 0;
@@ -1483,7 +1483,7 @@ static int nv_drm_revoke_modeset_permission(struct drm_device *dev,
pctx = dev->mode_config.acquire_ctx;
#endif
state = drm_atomic_state_alloc(dev);
state = nv_drm_atomic_state_base_alloc(dev);
if (!state) {
ret = -ENOMEM;
goto done;
@@ -1519,7 +1519,7 @@ static int nv_drm_revoke_modeset_permission(struct drm_device *dev,
ret = drm_atomic_commit(state);
done:
drm_atomic_state_put(state);
nv_drm_atomic_state_base_put(state);
#if NV_DRM_MODESET_LOCK_ALL_END_ARGUMENT_COUNT == 3
DRM_MODESET_LOCK_ALL_END(dev, ctx, ret);
kernel-open/nvidia-drm/nvidia-drm-helper.c
+3 -3
View File
@@ -91,7 +91,7 @@
int nv_drm_atomic_helper_disable_all(struct drm_device *dev,
struct drm_modeset_acquire_ctx *ctx)
{
struct drm_atomic_state *state;
nv_drm_atomic_state_base_t *state;
struct drm_connector_state *conn_state;
struct drm_connector *conn;
struct drm_plane_state *plane_state;
@@ -101,7 +101,7 @@ int nv_drm_atomic_helper_disable_all(struct drm_device *dev,
unsigned plane_mask = 0;
int ret, i;
state = drm_atomic_state_alloc(dev);
state = nv_drm_atomic_state_base_alloc(dev);
if (!state)
return -ENOMEM;
@@ -173,7 +173,7 @@ free:
}
}
drm_atomic_state_put(state);
nv_drm_atomic_state_base_put(state);
return ret;
}
kernel-open/nvidia-drm/nvidia-drm-helper.h
+86
View File
@@ -135,6 +135,92 @@ nv_drm_prime_pages_to_sg(struct drm_device *dev,
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
/*
* Linux commit 5164f7e7ff8e ("drm: Rename struct drm_atomic_state to
* drm_atomic_commit"), expected in Linux v7.2, renamed the top-level atomic
* commit object and its lifetime helpers.
*/
#if defined(NV_DRM_ATOMIC_COMMIT_STRUCT_PRESENT)
typedef struct drm_atomic_commit nv_drm_atomic_state_base_t;
#else
typedef struct drm_atomic_state nv_drm_atomic_state_base_t;
#endif
/*
* Linux commits 29b77ad7b9ca ("drm/atomic: Pass the full state to CRTC
* atomic_check") and 7c11b99a8e58 ("drm/atomic: Pass the full state to
* planes atomic_check") changed the CRTC and plane helper atomic_check
* callbacks from per-object state arguments to the full atomic transaction
* state. The existing conftests detect those full-state callback signatures
* when the argument type is still struct drm_atomic_state.
*
* Linux commit 5164f7e7ff8e ("drm: Rename struct drm_atomic_state to
* drm_atomic_commit"), expected in Linux v7.2, renamed that full transaction
* type. In those kernels, the callbacks still use the full atomic transaction
* state ABI, but the argument type is struct drm_atomic_commit. Either
* conftest means the helper callbacks take the full atomic transaction state.
*/
#if defined(NV_DRM_CRTC_ATOMIC_CHECK_HAS_ATOMIC_STATE_ARG) || \
defined(NV_DRM_ATOMIC_COMMIT_STRUCT_PRESENT)
#define NV_DRM_CRTC_ATOMIC_CHECK_HAS_FULL_STATE_ARG
#endif
#if defined(NV_DRM_PLANE_ATOMIC_CHECK_HAS_ATOMIC_STATE_ARG) || \
defined(NV_DRM_ATOMIC_COMMIT_STRUCT_PRESENT)
#define NV_DRM_PLANE_ATOMIC_CHECK_HAS_FULL_STATE_ARG
#endif
static inline nv_drm_atomic_state_base_t *
nv_drm_atomic_state_base_alloc(struct drm_device *dev)
{
#if defined(NV_DRM_ATOMIC_COMMIT_STRUCT_PRESENT)
return drm_atomic_commit_alloc(dev);
#else
return drm_atomic_state_alloc(dev);
#endif
}
static inline int
nv_drm_atomic_state_base_init(struct drm_device *dev,
nv_drm_atomic_state_base_t *state)
{
#if defined(NV_DRM_ATOMIC_COMMIT_STRUCT_PRESENT)
return drm_atomic_commit_init(dev, state);
#else
return drm_atomic_state_init(dev, state);
#endif
}
static inline void
nv_drm_atomic_state_base_put(nv_drm_atomic_state_base_t *state)
{
#if defined(NV_DRM_ATOMIC_COMMIT_STRUCT_PRESENT)
drm_atomic_commit_put(state);
#else
drm_atomic_state_put(state);
#endif
}
static inline void
nv_drm_atomic_state_base_default_clear(nv_drm_atomic_state_base_t *state)
{
#if defined(NV_DRM_ATOMIC_COMMIT_STRUCT_PRESENT)
drm_atomic_commit_default_clear(state);
#else
drm_atomic_state_default_clear(state);
#endif
}
static inline void
nv_drm_atomic_state_base_default_release(nv_drm_atomic_state_base_t *state)
{
#if defined(NV_DRM_ATOMIC_COMMIT_STRUCT_PRESENT)
drm_atomic_commit_default_release(state);
#else
drm_atomic_state_default_release(state);
#endif
}
int nv_drm_atomic_helper_disable_all(struct drm_device *dev,
struct drm_modeset_acquire_ctx *ctx);
kernel-open/nvidia-drm/nvidia-drm-modeset.c
+14 -12
View File
@@ -50,21 +50,23 @@
struct nv_drm_atomic_state {
struct NvKmsKapiRequestedModeSetConfig config;
struct drm_atomic_state base;
nv_drm_atomic_state_base_t base;
};
static inline struct nv_drm_atomic_state *to_nv_atomic_state(
struct drm_atomic_state *state)
nv_drm_atomic_state_base_t *state)
{
return container_of(state, struct nv_drm_atomic_state, base);
}
struct drm_atomic_state *nv_drm_atomic_state_alloc(struct drm_device *dev)
nv_drm_atomic_state_base_t *
nv_drm_atomic_state_alloc(struct drm_device *dev)
{
struct nv_drm_atomic_state *nv_state =
nv_drm_calloc(1, sizeof(*nv_state));
if (nv_state == NULL || drm_atomic_state_init(dev, &nv_state->base) < 0) {
if (nv_state == NULL ||
nv_drm_atomic_state_base_init(dev, &nv_state->base) < 0) {
nv_drm_free(nv_state);
return NULL;
}
@@ -72,16 +74,16 @@ struct drm_atomic_state *nv_drm_atomic_state_alloc(struct drm_device *dev)
return &nv_state->base;
}
void nv_drm_atomic_state_clear(struct drm_atomic_state *state)
void nv_drm_atomic_state_clear(nv_drm_atomic_state_base_t *state)
{
drm_atomic_state_default_clear(state);
nv_drm_atomic_state_base_default_clear(state);
}
void nv_drm_atomic_state_free(struct drm_atomic_state *state)
void nv_drm_atomic_state_free(nv_drm_atomic_state_base_t *state)
{
struct nv_drm_atomic_state *nv_state =
to_nv_atomic_state(state);
drm_atomic_state_default_release(state);
nv_drm_atomic_state_base_default_release(state);
nv_drm_free(nv_state);
}
@@ -178,7 +180,7 @@ __nv_drm_plane_fence_cb(
static int __nv_drm_convert_in_fences(
struct nv_drm_device *nv_dev,
struct drm_atomic_state *state,
nv_drm_atomic_state_base_t *state,
struct drm_crtc *crtc,
struct drm_crtc_state *crtc_state)
{
@@ -392,7 +394,7 @@ static int __nv_drm_get_syncpt_data(
*/
static int
nv_drm_atomic_apply_modeset_config(struct drm_device *dev,
struct drm_atomic_state *state,
nv_drm_atomic_state_base_t *state,
bool commit)
{
struct nv_drm_device *nv_dev = to_nv_device(dev);
@@ -527,7 +529,7 @@ nv_drm_atomic_apply_modeset_config(struct drm_device *dev,
}
int nv_drm_atomic_check(struct drm_device *dev,
struct drm_atomic_state *state)
nv_drm_atomic_state_base_t *state)
{
int ret = 0;
@@ -688,7 +690,7 @@ static void __nv_drm_handle_flip_event(struct nv_drm_crtc *nv_crtc)
}
int nv_drm_atomic_commit(struct drm_device *dev,
struct drm_atomic_state *state,
nv_drm_atomic_state_base_t *state,
bool nonblock)
{
int ret = -EBUSY;
kernel-open/nvidia-drm/nvidia-drm-modeset.h
+7 -6
View File
@@ -27,20 +27,21 @@
#if defined(NV_DRM_AVAILABLE)
#include "nvidia-drm-helper.h"
#include "nvkms-kapi.h"
struct drm_device;
struct drm_atomic_state;
struct drm_atomic_state *nv_drm_atomic_state_alloc(struct drm_device *dev);
void nv_drm_atomic_state_clear(struct drm_atomic_state *state);
void nv_drm_atomic_state_free(struct drm_atomic_state *state);
nv_drm_atomic_state_base_t *
nv_drm_atomic_state_alloc(struct drm_device *dev);
void nv_drm_atomic_state_clear(nv_drm_atomic_state_base_t *state);
void nv_drm_atomic_state_free(nv_drm_atomic_state_base_t *state);
int nv_drm_atomic_check(struct drm_device *dev,
struct drm_atomic_state *state);
nv_drm_atomic_state_base_t *state);
int nv_drm_atomic_commit(struct drm_device *dev,
struct drm_atomic_state *state, bool nonblock);
nv_drm_atomic_state_base_t *state, bool nonblock);
void nv_drm_handle_flip_occurred(struct nv_drm_device *nv_dev,
kernel-open/nvidia-drm/nvidia-drm-sources.mk
+1
View File
@@ -114,3 +114,4 @@ NV_CONFTEST_TYPE_COMPILE_TESTS += drm_fb_create_takes_format_info
NV_CONFTEST_TYPE_COMPILE_TESTS += drm_crtc_funcs_has_get_vblank_timestamp
NV_CONFTEST_TYPE_COMPILE_TESTS += drm_color_lut32_present
NV_CONFTEST_TYPE_COMPILE_TESTS += drm_colorop_has_funcs
NV_CONFTEST_TYPE_COMPILE_TESTS += drm_atomic_commit_struct_present
kernel-open/nvidia-modeset/nvidia-modeset-linux.c
-5
View File
@@ -664,11 +664,6 @@ int nvkms_strcmp(const char *s1, const char *s2)
return strcmp(s1, s2);
}
char* nvkms_strncpy(char *dest, const char *src, size_t n)
{
return strncpy(dest, src, n);
}
void nvkms_usleep(NvU64 usec)
{
if (usec < 1000) {
kernel-open/nvidia-modeset/nvidia-modeset-os-interface.h
-3
View File
@@ -149,9 +149,6 @@ int nvkms_memcmp (const void *s1,
size_t nvkms_strlen (const char *s);
int nvkms_strcmp (const char *s1,
const char *s2);
char* nvkms_strncpy (char *dest,
const char *src,
size_t n);
void nvkms_usleep (NvU64 usec);
NvU64 nvkms_get_usec (void);
int nvkms_copyin (void *kptr,
kernel-open/nvidia-uvm/uvm_ce_test.c
+15 -2
View File
@@ -40,6 +40,14 @@
#define CE_TEST_MEM_MIDDLE_OFFSET (CE_TEST_MEM_BEGIN_SIZE)
#define CE_TEST_MEM_END_OFFSET (CE_TEST_MEM_SIZE - CE_TEST_MEM_BEGIN_SIZE)
#define CE_TEST_MEM_COUNT 5
// Minimum payload size (bytes) for which the "ciphertext must differ from
// plaintext" sanity check is statistically meaningful. AES-CTR produces
// ciphertext = plaintext XOR keystream, so for tiny payloads (e.g. the 1-byte
// small_sizes case) the keystream byte can be 0x00, making ciphertext ==
// plaintext purely by chance (~1/256 per byte) even when encryption is
// correct. Below this size the heuristic is skipped; the authoritative
// correctness check remains the end-to-end roundtrip compare.
#define CE_TEST_MIN_CIPHERTEXT_DIFF_SIZE 16
static NV_STATUS test_non_pipelined(uvm_gpu_t *gpu)
{
@@ -1107,9 +1115,14 @@ static NV_STATUS test_cpu_to_gpu_roundtrip(uvm_gpu_t *gpu,
TEST_NV_CHECK_GOTO(uvm_push_end_and_wait(&push), out);
TEST_CHECK_GOTO(!mem_match(src_plain, src_cipher, size), out);
// Skip the "ciphertext must differ from plaintext" heuristic for tiny
// payloads; see CE_TEST_MIN_CIPHERTEXT_DIFF_SIZE above. The roundtrip
// compare below still verifies correctness for all sizes.
if (size >= CE_TEST_MIN_CIPHERTEXT_DIFF_SIZE) {
TEST_CHECK_GOTO(!mem_match(src_plain, src_cipher, size), out);
TEST_CHECK_GOTO(!mem_match(dst_cipher, src_plain, size), out);
TEST_CHECK_GOTO(!mem_match(dst_cipher, src_plain, size), out);
}
// CPU (encrypted) > CPU (decrypted), using CPU
if (decrypt_in_order) {
kernel-open/nvidia-uvm/uvm_gpu.c
+15 -2
View File
@@ -2923,7 +2923,7 @@ static NV_STATUS add_gpu(const NvProcessorUuid *gpu_uuid,
goto error;
if (alloc_parent) {
if (enable_devmem && !gpu->mem_info.numa.enabled && !gpu->parent->is_integrated_gpu) {
if (enable_devmem && uvm_gpu_supports_devmem(gpu)) {
status = uvm_devmem_init(parent_gpu);
if (status != NV_OK) {
UVM_ERR_PRINT("failed to intialize device private memory: %s, GPU %s\n",
@@ -2938,7 +2938,7 @@ static NV_STATUS add_gpu(const NvProcessorUuid *gpu_uuid,
#if UVM_IS_CONFIG_HMM()
// HMM was disabled when first initialising the parent so we can't support
// it now. Tell the caller to retry with it disabled.
else if (!parent_gpu->devmem && enable_devmem && !gpu->mem_info.numa.enabled && !gpu->parent->is_integrated_gpu) {
else if (!parent_gpu->devmem && enable_devmem && uvm_gpu_supports_devmem(gpu)) {
status = NV_ERR_BUSY_RETRY;
goto error;
}
@@ -3094,6 +3094,19 @@ static NV_STATUS gpu_retain_by_uuid_locked(const NvProcessorUuid *gpu_uuid,
if (status != NV_OK)
goto error_unregister;
}
#if UVM_IS_CONFIG_HMM()
// The GPU object already exists but was first brought up by a VA space with
// HMM disabled, so it has no devmem and can't service this HMM request.
// add_gpu(), which performs the same check, is not reached on this path, so
// repeat it here. Tell the caller to retry with HMM disabled. Nothing was
// retained, so there is nothing to undo.
// NUMA and integrated GPUs don't supoport ZONE_DEVICE memory so we don't
// need devmem to be initialised on those.
else if (!parent_gpu->devmem && enable_devmem && uvm_gpu_supports_devmem(gpu)) {
status = NV_ERR_BUSY_RETRY;
goto error_unregister;
}
#endif
else {
atomic64_inc(&gpu->retained_count);
}
kernel-open/nvidia-uvm/uvm_gpu.h
+14
View File
@@ -1613,6 +1613,20 @@ static bool uvm_parent_gpu_supports_full_coherence(uvm_parent_gpu_t *parent_gpu)
return parent_gpu->is_integrated_gpu;
}
// NUMA-attached and integrated GPUs don't support ZONE_DEVICE (devmem) memory,
// so pageable memory which uses ZONE_DEVICE can only be migrated to GPUs which
// have neither property.
//
// CDMM GPUs use a separate devmem mechanism that does not rely on
// DEVICE_PRIVATE pages, so UVM_CAN_USE_DEVICE_PRIVATE_MEMREMAP_PAGES() does
// not apply to them — uvm_devmem_init() handles this distinction internally.
static bool uvm_gpu_supports_devmem(uvm_gpu_t *gpu)
{
if (gpu->mem_info.numa.enabled || gpu->parent->is_integrated_gpu)
return false;
return gpu->parent->cdmm_enabled || UVM_CAN_USE_DEVICE_PRIVATE_MEMREMAP_PAGES();
}
// Returns a GPU peer pair index in the range [0 .. UVM_MAX_UNIQUE_GPU_PAIRS).
NvU32 uvm_gpu_pair_index(const uvm_gpu_id_t id0, const uvm_gpu_id_t id1);
kernel-open/nvidia-uvm/uvm_pmm_gpu.c
+3 -1
View File
@@ -2804,7 +2804,9 @@ static NV_STATUS init_chunk_split_cache_level(uvm_pmm_gpu_t *pmm, size_t level)
size_t size;
size_t align;
if (level == 0) {
strncpy(chunk_split_cache[level].name, "uvm_gpu_chunk_t", sizeof(chunk_split_cache[level].name) - 1);
snprintf(chunk_split_cache[level].name,
sizeof(chunk_split_cache[level].name),
"uvm_gpu_chunk_t");
size = sizeof(uvm_gpu_chunk_t);
align = __alignof__(uvm_gpu_chunk_t);
} else {
kernel-open/nvidia-uvm/uvm_tools.c
+10 -1
View File
@@ -304,8 +304,10 @@ static NV_STATUS map_user_pages(NvU64 user_va, NvU64 size, void **addr, struct p
}
*addr = vmap(*pages, num_pages, VM_MAP, PAGE_KERNEL);
if (*addr == NULL)
if (*addr == NULL) {
status = NV_ERR_NO_MEMORY;
goto fail;
}
return NV_OK;
@@ -2497,6 +2499,13 @@ static NV_STATUS tools_access_process_memory(uvm_va_space_t *va_space,
// Make sure a CPU resident page has an up to date struct page pointer.
if (uvm_va_block_is_hmm(block)) {
// Verify the target address is writable. This isn't needed for
// managed ranges since those are always RW. If the target is a
// CoW mapping that will be broken below in the residency update.
if (is_write && !(block_context->hmm.vma->vm_flags & VM_WRITE)) {
status = NV_ERR_INSUFFICIENT_PERMISSIONS;
goto unlock_and_exit;
}
status = uvm_hmm_va_block_update_residency_info_unlocked(block, mm, UVM_PAGE_ALIGN_DOWN(target_va_start), true);
if (status != NV_OK)
goto unlock_and_exit;
kernel-open/nvidia/export_nvswitch.h
-8
View File
@@ -807,14 +807,6 @@ nvswitch_os_strlen
const char *str
);
char*
nvswitch_os_strncpy
(
char *pDest,
const char *pSrc,
NvLength length
);
int
nvswitch_os_strncmp
(
kernel-open/nvidia/libspdm_ecc.c
+3 -1
View File
@@ -335,7 +335,8 @@ static bool lkca_ecdsa_verify_akcipher(void *ec_context, size_t hash_nid,
}
req = akcipher_request_alloc(tfm, GFP_KERNEL);
if (IS_ERR(req)) {
if (IS_ERR_OR_NULL(req)) {
err = IS_ERR(req) ? PTR_ERR(req) : -ENOMEM;
pr_info("akcipher_request_alloc failed in lkca_ecdsa_verify\n");
goto failTfm;
}
@@ -343,6 +344,7 @@ static bool lkca_ecdsa_verify_akcipher(void *ec_context, size_t hash_nid,
// We concatenate signature and hash and ship it to kernel
ber = kmalloc(ber_max_len + hash_size, GFP_KERNEL);
if (ber == NULL) {
err = -ENOMEM;
goto failReq;
}
kernel-open/nvidia/linux_nvswitch.c
+1 -12
View File
@@ -2059,7 +2059,7 @@ nvswitch_os_read_registry_dword
return -NVL_ERR_GENERIC;
}
strncpy(regkey_val, regkey_val_start, regkey_val_len);
memcpy(regkey_val, regkey_val_start, regkey_val_len);
regkey_val[regkey_val_len] = '\0';
if (nvswitch_os_strtouint(regkey_val, data) != 0)
@@ -2406,17 +2406,6 @@ nvswitch_os_strlen
return strlen(str);
}
char*
nvswitch_os_strncpy
(
char *dest,
const char *src,
NvLength length
)
{
return strncpy(dest, src, length);
}
int
nvswitch_os_strncmp
(
kernel-open/nvidia/nv-dma.c
+25 -6
View File
@@ -53,6 +53,14 @@ void nv_unmap_dma_map_scatterlist (nv_dma_map_t *dma_map);
static void nv_dma_unmap_contig (nv_dma_map_t *dma_map);
static void nv_dma_unmap_scatterlist (nv_dma_map_t *dma_map);
static enum dma_data_direction nv_dma_get_direction
(
nv_dma_map_t *dma_map
)
{
return dma_map->bReadOnlyDeviceMap ? DMA_TO_DEVICE : DMA_BIDIRECTIONAL;
}
static inline NvBool nv_dma_is_addressable(
nv_dma_device_t *dma_dev,
NvU64 start,
@@ -72,9 +80,11 @@ static NV_STATUS nv_dma_map_contig(
NvU64 *va
)
{
enum dma_data_direction direction = nv_dma_get_direction(dma_map);
*va = dma_map_page_attrs(dma_map->dev, dma_map->pages[0], 0,
dma_map->page_count * PAGE_SIZE,
DMA_BIDIRECTIONAL,
direction,
(dma_map->cache_type == NV_MEMORY_UNCACHED) ?
DMA_ATTR_SKIP_CPU_SYNC : 0);
if (dma_mapping_error(dma_map->dev, *va))
@@ -101,9 +111,11 @@ static NV_STATUS nv_dma_map_contig(
static void nv_dma_unmap_contig(nv_dma_map_t *dma_map)
{
enum dma_data_direction direction = nv_dma_get_direction(dma_map);
dma_unmap_page_attrs(dma_map->dev, dma_map->mapping.contig.dma_addr,
dma_map->page_count * PAGE_SIZE,
DMA_BIDIRECTIONAL,
direction,
(dma_map->cache_type == NV_MEMORY_UNCACHED) ?
DMA_ATTR_SKIP_CPU_SYNC : 0);
}
@@ -224,6 +236,7 @@ NV_STATUS nv_map_dma_map_scatterlist(nv_dma_map_t *dma_map)
NV_STATUS status = NV_OK;
nv_dma_submap_t *submap;
NvU64 i;
enum dma_data_direction direction = nv_dma_get_direction(dma_map);
NV_FOR_EACH_DMA_SUBMAP(dma_map, submap, i)
{
@@ -233,7 +246,7 @@ NV_STATUS nv_map_dma_map_scatterlist(nv_dma_map_t *dma_map)
dma_map_sg(dma_map->dev,
submap->sgt.sgl,
submap->sgt.orig_nents,
DMA_BIDIRECTIONAL);
direction);
if (submap->sg_map_count == 0)
{
status = NV_ERR_OPERATING_SYSTEM;
@@ -253,6 +266,7 @@ void nv_unmap_dma_map_scatterlist(nv_dma_map_t *dma_map)
{
nv_dma_submap_t *submap;
NvU64 i;
enum dma_data_direction direction = nv_dma_get_direction(dma_map);
NV_FOR_EACH_DMA_SUBMAP(dma_map, submap, i)
{
@@ -269,7 +283,7 @@ void nv_unmap_dma_map_scatterlist(nv_dma_map_t *dma_map)
dma_unmap_sg(dma_map->dev, submap->sgt.sgl,
submap->sgt.orig_nents,
DMA_BIDIRECTIONAL);
direction);
}
}
@@ -376,6 +390,7 @@ NV_STATUS NV_API_CALL nv_dma_map_sgt(
NvU64 page_count,
NvU64 *va_array,
NvU32 cache_type,
NvBool bReadOnlyDeviceMap,
void **priv
)
{
@@ -408,6 +423,7 @@ NV_STATUS NV_API_CALL nv_dma_map_sgt(
dma_map->page_count = page_count;
dma_map->contiguous = NV_FALSE;
dma_map->cache_type = cache_type;
dma_map->bReadOnlyDeviceMap = bReadOnlyDeviceMap;
dma_map->mapping.discontig.submap_count = 0;
status = nv_dma_map_scatterlist(dma_dev, dma_map, va_array);
@@ -453,6 +469,7 @@ static NV_STATUS NV_API_CALL nv_dma_map_pages(
NvU64 *va_array,
NvBool contig,
NvU32 cache_type,
NvBool bReadOnlyDeviceMap,
void **priv
)
{
@@ -489,6 +506,7 @@ static NV_STATUS NV_API_CALL nv_dma_map_pages(
dma_map->page_count = page_count;
dma_map->contiguous = contig;
dma_map->cache_type = cache_type;
dma_map->bReadOnlyDeviceMap = bReadOnlyDeviceMap;
if (dma_map->page_count > 1 && !dma_map->contiguous)
{
@@ -579,6 +597,7 @@ NV_STATUS NV_API_CALL nv_dma_map_alloc
NvU64 page_count,
NvU64 *va_array,
NvBool contig,
NvBool bReadOnlyDeviceMap,
void **priv
)
{
@@ -594,7 +613,7 @@ NV_STATUS NV_API_CALL nv_dma_map_alloc
{
*priv = at->import_sgt;
status = nv_dma_map_sgt(dma_dev, page_count, va_array, at->cache_type,
priv);
bReadOnlyDeviceMap, priv);
if (status != NV_OK)
{
*priv = at;
@@ -653,7 +672,7 @@ NV_STATUS NV_API_CALL nv_dma_map_alloc
*priv = pages;
status = nv_dma_map_pages(dma_dev, page_count, va_array, contig, cache_type,
priv);
bReadOnlyDeviceMap, priv);
if (status != NV_OK)
{
*priv = at;
kernel-open/nvidia/nv-dmabuf.c
+8 -2
View File
@@ -617,7 +617,7 @@ nv_dma_buf_get_phys_addresses (
nvidia_stack_t *sp = NULL;
NvBool api_lock_taken = NV_FALSE;
NvBool gpu_lock_taken = NV_FALSE;
NvU32 i;
NvU32 i = 0;
int rc = 0;
if (!nv_inc_and_check_one_phys_refcount(priv, start_index, handle_count))
@@ -693,6 +693,11 @@ nv_dma_buf_get_phys_addresses (
return NV_OK;
unmap_handles:
//
// Restore pre-call refcounts so nv_put_phys_addresses() can unmap handles
// that were first mapped by this call.
//
(void) nv_dec_and_check_zero_phys_refcount(priv, start_index, i);
nv_put_phys_addresses(sp, priv, start_index, i);
if (gpu_lock_taken)
@@ -710,7 +715,8 @@ free_sp:
nv_kmem_cache_free_stack(sp);
failed:
nv_reset_phys_refcount(priv, start_index, handle_count);
(void) nv_dec_and_check_zero_phys_refcount(priv, start_index + i,
handle_count - i);
return status;
}
kernel-open/nvidia/nv-mmap.c
+2 -2
View File
@@ -218,9 +218,9 @@ found:
ret = length;
if (write)
memcpy(kernel_mapping, buffer, length);
os_mem_copy(kernel_mapping, buffer, length);
else
memcpy(buffer, kernel_mapping, length);
os_mem_copy(buffer, kernel_mapping, length);
if (at == NULL && !has_pages)
{
kernel-open/nvidia/nv-procfs.c
+33 -7
View File
@@ -63,6 +63,7 @@ extern char *NVreg_TemporaryFilePath;
extern char *NVreg_ExcludedGpus;
static char nv_registry_keys[NV_MAX_REGISTRY_KEYS_LENGTH];
static struct semaphore nv_registry_keys_lock;
#if defined(CONFIG_PM)
nv_pm_action_depth_t nv_procfs_pm_action_depth = NV_PM_ACTION_DEPTH_DEFAULT;
@@ -397,16 +398,28 @@ nv_procfs_close_registry(
registry_keys = ((nvl != NULL) ?
nvl->registry_keys : nv_registry_keys);
if (strstr(registry_keys, key_name) != NULL)
goto done;
len = strlen(registry_keys);
if (nvl != NULL)
down(&nvl->ldata_lock);
else
down(&nv_registry_keys_lock);
if ((len + key_len + 2) <= NV_MAX_REGISTRY_KEYS_LENGTH)
// Keep the duplicate check, length check, and append atomic.
if (strstr(registry_keys, key_name) == NULL)
{
if (len != 0)
strcat(registry_keys, ", ");
strcat(registry_keys, key_name);
len = strlen(registry_keys);
if ((len + key_len + 2) <= NV_MAX_REGISTRY_KEYS_LENGTH)
{
if (len != 0)
strcat(registry_keys, ", ");
strcat(registry_keys, key_name);
}
}
if (nvl != NULL)
up(&nvl->ldata_lock);
else
up(&nv_registry_keys_lock);
}
done:
@@ -467,7 +480,18 @@ nv_procfs_read_registry(
registry_keys = ((nvl != NULL) ?
nvl->registry_keys : nv_registry_keys);
if (nvl != NULL)
down(&nvl->ldata_lock);
else
down(&nv_registry_keys_lock);
seq_printf(s, "Binary: \"%s\"\n", registry_keys);
if (nvl != NULL)
up(&nvl->ldata_lock);
else
up(&nv_registry_keys_lock);
return 0;
}
@@ -1329,6 +1353,8 @@ int nv_procfs_init(void)
nv_dir_name[sizeof(nv_dir_name) - 1] = '\0';
NV_INIT_MUTEX(&nv_registry_keys_lock);
proc_nvidia = NV_CREATE_PROC_DIR(nv_dir_name, NULL);
if (!proc_nvidia)
kernel-open/nvidia/nv.c
+38 -13
View File
@@ -1088,6 +1088,10 @@ static void nv_free_file_private(nv_linux_file_private_t *nvlfp)
if (nvlfp == NULL)
return;
// Event teardown can race in-flight posts that still use nvfp.
while (READ_ONCE(nvlfp->nvfp.event_posting_refcount) != 0)
cond_resched();
for (nvet = nvlfp->event_data_head; nvet != NULL; nvet = nvlfp->event_data_head)
{
nvlfp->event_data_head = nvlfp->event_data_head->next;
@@ -2396,10 +2400,8 @@ out:
return rc;
}
static NV_STATUS nv_validate_ioctls(unsigned int cmd)
static NV_STATUS nv_validate_ioctl_data(unsigned int arg_cmd, size_t arg_size)
{
size_t arg_size = _IOC_SIZE(cmd);
int arg_cmd = _IOC_NR(cmd);
int i;
NV_STATUS status;
static const struct {
@@ -2423,7 +2425,7 @@ static NV_STATUS nv_validate_ioctls(unsigned int cmd)
_NV_IOCTL_ENTRY(NV_ESC_SET_NUMA_STATUS, nv_ioctl_set_numa_status_t, NV_FALSE),
};
status = rm_validate_ioctls(cmd, arg_size);
status = rm_validate_ioctls(arg_cmd, arg_size);
if (status != NV_ERR_INVALID_COMMAND)
{
return status;
@@ -2452,6 +2454,11 @@ static NV_STATUS nv_validate_ioctls(unsigned int cmd)
return NV_ERR_INVALID_ARGUMENT;
}
static NV_STATUS nv_validate_ioctls(unsigned int cmd)
{
return nv_validate_ioctl_data(_IOC_NR(cmd), _IOC_SIZE(cmd));
}
int
nvidia_ioctl(
struct inode *inode,
@@ -2509,6 +2516,12 @@ nvidia_ioctl(
status = -EINVAL;
goto done_early;
}
if (nv_validate_ioctl_data(arg_cmd, arg_size) != NV_OK)
{
status = -EINVAL;
goto done_early;
}
}
NV_KMALLOC(arg_copy, arg_size);
@@ -6309,6 +6322,9 @@ void NV_API_CALL nv_get_screen_info(
NvU64 *pFbSize
)
{
#if NV_CHECK_EXPORT_SYMBOL(screen_info) || NV_CHECK_EXPORT_SYMBOL(sysfb_primary_display)
struct screen_info *sysfb_info;
#endif
nv_linux_state_t *nvl = NV_GET_NVL_FROM_NV_STATE(nv);
struct pci_dev *pci_dev = nvl->pci_dev;
int i;
@@ -6374,9 +6390,18 @@ void NV_API_CALL nv_get_screen_info(
*
* After commit b8466fe82b79 ("efi: move screen_info into efi init code")
* in v6.7, 'screen_info' is exported as GPL licensed symbol for ARM64.
*
* After commit a41e0ab394e4 ("sysfb: Replace screen_info with sysfb_primary_display")
* in v7.0, 'screen_info' is refactored as 'sysfb_primary_display.screen'.
*/
#if NV_CHECK_EXPORT_SYMBOL(screen_info)
#if NV_CHECK_EXPORT_SYMBOL(screen_info) || NV_CHECK_EXPORT_SYMBOL(sysfb_primary_display)
#if NV_CHECK_EXPORT_SYMBOL(sysfb_primary_display)
sysfb_info = &sysfb_primary_display.screen;
#else
sysfb_info = &screen_info;
#endif
/*
* If there is not a framebuffer console, return 0 size.
*
@@ -6384,13 +6409,13 @@ void NV_API_CALL nv_get_screen_info(
* initialization, and then will be set to a value, such as
* VIDEO_TYPE_VLFB or VIDEO_TYPE_EFI if an fbdev console is used.
*/
if (screen_info.orig_video_isVGA > 1)
if (sysfb_info->orig_video_isVGA > 1)
{
NvU64 physAddr = screen_info.lfb_base;
NvU64 physAddr = sysfb_info->lfb_base;
#if defined(VIDEO_CAPABILITY_64BIT_BASE)
if (screen_info.capabilities & VIDEO_CAPABILITY_64BIT_BASE)
if (sysfb_info->capabilities & VIDEO_CAPABILITY_64BIT_BASE)
{
physAddr |= (NvU64)screen_info.ext_lfb_base << 32;
physAddr |= (NvU64)sysfb_info->ext_lfb_base << 32;
}
#endif
/*
@@ -6402,10 +6427,10 @@ void NV_API_CALL nv_get_screen_info(
NV_IS_CONSOLE_MAPPED(nv, physAddr))
{
*pPhysicalAddress = physAddr;
*pFbWidth = screen_info.lfb_width;
*pFbHeight = screen_info.lfb_height;
*pFbDepth = screen_info.lfb_depth;
*pFbPitch = screen_info.lfb_linelength;
*pFbWidth = sysfb_info->lfb_width;
*pFbHeight = sysfb_info->lfb_height;
*pFbDepth = sysfb_info->lfb_depth;
*pFbPitch = sysfb_info->lfb_linelength;
*pFbSize = (NvU64)(*pFbHeight) * (NvU64)(*pFbPitch);
return;
}
kernel-open/nvidia/nvidia.Kbuild
+3
View File
@@ -164,6 +164,7 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += shrinker_alloc
NV_CONFTEST_FUNCTION_COMPILE_TESTS += vma_flags_set_word
NV_CONFTEST_FUNCTION_COMPILE_TESTS += vm_flags_set
NV_CONFTEST_FUNCTION_COMPILE_TESTS += get_dev_pagemap_has_pgmap_arg
NV_CONFTEST_FUNCTION_COMPILE_TESTS += use_dma_iommu
NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_gpl_sme_active
NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_swiotlb_map_sg_attrs
@@ -173,6 +174,8 @@ NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_close_fd
NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_pxm_to_node
NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_screen_info
NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_gpl_screen_info
NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_sysfb_primary_display
NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_gpl_sysfb_primary_display
NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_i2c_bus_status
NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_tegra_fuse_control_read
NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_pci_find_host_bridge
kernel-open/nvidia/os-interface.c
+4 -2
View File
@@ -770,8 +770,10 @@ NvU32 NV_API_CALL os_get_current_process(void)
void NV_API_CALL os_get_current_process_name(char *buf, NvU32 len)
{
task_lock(current);
strncpy(buf, current->comm, len - 1);
buf[len - 1] = '\0';
if (strscpy(buf, current->comm, len) < 0) {
// strscpy() returns -E2BIG on truncation, which is acceptable here.
}
task_unlock(current);
}
src/common/displayport/inc/dp_deviceimpl.h
+30 -2
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -548,6 +548,32 @@ namespace DisplayPort
bool tryRemote1XCaps;
bool bBKSVReadMessagePending;
bool bBCapsReadMessagePending;
bool bDestroying;
unsigned callbackDepth;
class CallbackGuard
{
DeviceHDCPDetection *owner;
CallbackGuard(const CallbackGuard &) = delete;
CallbackGuard &operator=(const CallbackGuard &) = delete;
public:
CallbackGuard(DeviceHDCPDetection *owner)
: owner(owner)
{
owner->beginCallback();
}
~CallbackGuard()
{
owner->endCallback();
}
};
void beginCallback(void);
void endCallback(void);
void requestDestroy(void);
void destroyNow(void);
public:
@@ -556,8 +582,9 @@ namespace DisplayPort
isBCapsHDCP(false), retriesRemoteBKSVReadMessage(0), retriesRemoteBCapsReadMessage(0),
retriesRemote22BCapsReadMessage(0), retryRemoteBKSVReadMessage(false),
retryRemoteBCapsReadMessage(false), retryRemote22BCapsReadMessage(false),
tryRemote1XCaps(false),
bBKSVReadMessagePending(false), bBCapsReadMessagePending(false)
,bDestroying(false), callbackDepth(0)
{
this->parent = parent;
this->messageManager = messageManager;
@@ -565,6 +592,7 @@ namespace DisplayPort
}
~DeviceHDCPDetection();
void destroy(void);
void expired(const void * tag);
void start();
void waivePendingHDCPCapDoneNotification();
src/common/displayport/src/dp_connectorimpl.cpp
+9 -6
View File
@@ -7339,16 +7339,19 @@ void ConnectorImpl::disconnectDeviceList()
{
for (Device * d = enumDevices(0); d; d = enumDevices(d))
{
((DeviceImpl*)d)->plugged = false;
DeviceImpl* device = (DeviceImpl*)d;
device->plugged = false;
// Clear the active bit (payload_allocate)
((DeviceImpl*)d)->payloadAllocated = false;
device->payloadAllocated = false;
// Deallocate object which may go stale after long pulse handling.
if (((DeviceImpl*)d)->isDeviceHDCPDetectionAlive)
if (device->isDeviceHDCPDetectionAlive)
{
delete ((DeviceImpl*)d)->deviceHDCPDetection;
((DeviceImpl*)d)->deviceHDCPDetection = NULL;
((DeviceImpl*)d)->isHDCPCap = False;
device->deviceHDCPDetection->destroy();
device->isHDCPCap = False;
device->deviceHDCPDetection = NULL;
device->isDeviceHDCPDetectionAlive = false;
}
}
}
src/common/displayport/src/dp_deviceimpl.cpp
+111 -16
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -3385,6 +3385,73 @@ bool DeviceImpl::setModeList(DisplayPort::DpModesetParams *modeList, unsigned nu
}
void
DeviceHDCPDetection::beginCallback(void)
{
callbackDepth++;
}
void
DeviceHDCPDetection::endCallback(void)
{
DP_ASSERT(callbackDepth > 0);
if (callbackDepth > 0)
{
callbackDepth--;
}
if (bDestroying && (callbackDepth == 0))
{
destroyNow();
}
}
void
DeviceHDCPDetection::destroy(void)
{
if (parent)
{
parent->isDeviceHDCPDetectionAlive = false;
if (parent->deviceHDCPDetection == this)
{
parent->deviceHDCPDetection = NULL;
}
parent = NULL;
}
requestDestroy();
}
void
DeviceHDCPDetection::requestDestroy(void)
{
if (bDestroying)
{
return;
}
bDestroying = true;
if (callbackDepth == 0)
{
destroyNow();
}
}
void
DeviceHDCPDetection::destroyNow(void)
{
if (parent)
{
parent->isDeviceHDCPDetectionAlive = false;
if (parent->deviceHDCPDetection == this)
{
parent->deviceHDCPDetection = NULL;
}
}
delete this;
}
void
DeviceHDCPDetection::start()
{
@@ -3503,6 +3570,13 @@ DeviceHDCPDetection::handleRemoteDpcdReadDownReply
MessageManager::Message *from
)
{
if (bDestroying)
{
return;
}
CallbackGuard callbackGuard(this);
NvU8 i2cBcaps;
unsigned dataCompleted;
unsigned defaultReason;
@@ -3525,8 +3599,7 @@ DeviceHDCPDetection::handleRemoteDpcdReadDownReply
// Destruct only when no message is pending
if (!(bBKSVReadMessagePending || bBCapsReadMessagePending))
{
parent->isDeviceHDCPDetectionAlive = false;
delete this;
requestDestroy();
}
return;
}
@@ -3573,8 +3646,7 @@ DeviceHDCPDetection::handleRemoteDpcdReadDownReply
// Destruct only when no message is pending
if (!(bBKSVReadMessagePending || bBCapsReadMessagePending))
{
parent->isDeviceHDCPDetectionAlive = false;
delete this;
requestDestroy();
}
return;
}
@@ -3606,8 +3678,7 @@ DeviceHDCPDetection::handleRemoteDpcdReadDownReply
// Destruct only when no message is pending
if (!(bBKSVReadMessagePending || bBCapsReadMessagePending))
{
parent->isDeviceHDCPDetectionAlive = false;
delete this;
requestDestroy();
}
return;
}
@@ -3632,6 +3703,10 @@ DeviceHDCPDetection::handleRemoteDpcdReadDownReply
parent->transaction(AuxBus::read, AuxBus::i2cMot, HDCP_I2C_CLIENT_ADDR, &i2cBcaps,
1, &dataCompleted, &defaultReason, HDCP_BCAPS_DDC_OFFSET, 1);
if (bDestroying)
{
return;
}
DP_PRINTF(DP_NOTICE, "DP-QM> Device at '%s' is with DDC BACPS: %x",
parent->address.toString(sb), i2cBcaps);
@@ -3668,8 +3743,8 @@ DeviceHDCPDetection::handleRemoteDpcdReadDownReply
// Destruct only when no message is pending
if (!(bBKSVReadMessagePending || bBCapsReadMessagePending))
{
parent->isDeviceHDCPDetectionAlive = false;
delete this;
requestDestroy();
return;
}
}
else
@@ -3716,6 +3791,13 @@ DeviceHDCPDetection::messageFailed
NakData *nakData
)
{
if (bDestroying)
{
return;
}
CallbackGuard callbackGuard(this);
if (from == &remoteBKSVReadMessage)
{
if ((retriesRemoteBKSVReadMessage < DPCD_REMOTE_DPCD_READ_MESSAGE_RETRIES) &&
@@ -3791,7 +3873,7 @@ DeviceHDCPDetection::messageFailed
// Destruct only when no message is pending
if (!(bBKSVReadMessagePending || bBCapsReadMessagePending))
{
parent->isDeviceHDCPDetectionAlive = false;
// Becareful below is ! ..
// Complete remote HDCP probe and check if can power down again.
if (parent->connector)
@@ -3800,7 +3882,7 @@ DeviceHDCPDetection::messageFailed
parent->connector->isNoActiveStreamAndPowerdown();
}
delete this;
requestDestroy();
}
}
@@ -3810,6 +3892,13 @@ DeviceHDCPDetection::expired
const void *tag
)
{
if (bDestroying)
{
return;
}
CallbackGuard callbackGuard(this);
// Clear stale HDCP states when monitor instance is already destroyed
if (!parent->plugged)
{
@@ -3837,8 +3926,7 @@ DeviceHDCPDetection::expired
if (!(bBKSVReadMessagePending || bBCapsReadMessagePending))
{
parent->isDeviceHDCPDetectionAlive = false;
delete this;
requestDestroy();
}
return;
}
@@ -3900,7 +3988,14 @@ DeviceHDCPDetection::expired
DeviceHDCPDetection::~DeviceHDCPDetection()
{
parent->isDeviceHDCPDetectionAlive = false;
if (parent)
{
parent->isDeviceHDCPDetectionAlive = false;
if (parent->deviceHDCPDetection == this)
{
parent->deviceHDCPDetection = NULL;
}
}
// Clear all pending callbacks/messages
if (this->timer)
@@ -3921,6 +4016,6 @@ DeviceHDCPDetection::waivePendingHDCPCapDoneNotification()
{
// Waive the pendingHDCPCapDone notification
parent->shadow.hdcpCapDone = true;
parent->isDeviceHDCPDetectionAlive = false;
delete this;
requestDestroy();
}
src/common/inc/nvBldVer.h
+10 -10
View File
@@ -36,25 +36,25 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r610_45
#define NV_BUILD_BRANCH r610_85
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r610_45
#define NV_PUBLIC_BRANCH r610_85
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r610/r610_45-163"
#define NV_BUILD_CHANGELIST_NUM (38429115)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r610/r610_85-4"
#define NV_BUILD_CHANGELIST_NUM (38610010)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r610/r610_45-163"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (38429115)
#define NV_BUILD_NAME "rel/gpu_drv/r610/r610_85-4"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (38610010)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r610_45-6"
#define NV_BUILD_CHANGELIST_NUM (38273252)
#define NV_BUILD_BRANCH_VERSION "r610_85-151"
#define NV_BUILD_CHANGELIST_NUM (38566155)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "610.62"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (38273252)
#define NV_BUILD_NAME "610.88"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (38566155)
#define NV_BUILD_BRANCH_BASE_VERSION R610
#endif
// End buildmeister python edited section
src/common/inc/nvUnixVersion.h
+1 -1
View File
@@ -5,7 +5,7 @@
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1) || \
defined(NV_DCECORE)
#define NV_VERSION_STRING "610.43.03"
#define NV_VERSION_STRING "610.57.04"
#else
src/common/inc/swref/published/blackwell/gb202/dev_xtl_ep_pcfg_gpu.h
+5
View File
@@ -46,6 +46,11 @@
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CAS_COMPLETER_128BIT_SUPPORTED 0x00000001 /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CAS_COMPLETER_128BIT_OVERRIDEABLE 1 /* */
#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_2 0x00000088 /* RW-4R */
#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_VALUES 3:0 /* RWIVF */
#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_VALUES_DEFAULT 0x00000000 /* RWI-V */
#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_DISABLE 4:4 /* RWIVF */
#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_DISABLE_ENABLED 0x00000000 /* RWI-V */
#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_DISABLE_DISABLED 0x00000001 /* RW--V */
#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_2_LTR_ENABLE 10:10 /* RWIVF */
#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_2_LTR_ENABLE_DEFAULT 0x00000000 /* RWI-V */
#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS 0x00000004 /* RW-4R */
src/common/nvlink/inband/interface/nvlink_inband_msg.h
+2
View File
@@ -91,6 +91,8 @@ typedef struct
#define NVLINK_INBAND_GPU_PROBE_CAPS_GPU_PROBE_REQUEST_ACTION NVBIT(7)
#define NVLINK_INBAND_GPU_PROBE_CAPS_MC_RETRY NVBIT(8)
#define NVLINK_INBAND_GPU_PROBE_CAPS_PROBE_UPDATE_V2 NVBIT(9)
/* Bits 10-12 reserved */
#define NVLINK_INBAND_GPU_PROBE_CAPS_ADAPTIVE_BANDWIDTH_AND_LINK_RETRAIN_FIX NVBIT(13)
/* Add more caps as need in the future */
src/common/nvswitch/interface/export_nvswitch.h
-8
View File
@@ -803,14 +803,6 @@ nvswitch_os_strlen
const char *str
);
char*
nvswitch_os_strncpy
(
char *pDest,
const char *pSrc,
NvLength length
);
int
nvswitch_os_strncmp
(
src/common/nvswitch/kernel/ls10/smbpbi_ls10.c
+3 -4
View File
@@ -178,10 +178,9 @@ nvswitch_smbpbi_send_init_data_ls10
cmd.hdr.size = RM_SOE_CMD_SIZE(SMBPBI, INIT_DATA);
cmd.cmd.smbpbiCmd.cmdType = RM_SOE_SMBPBI_CMD_ID_INIT_DATA;
nvswitch_os_strncpy((char *)pInitDataCmd->driverVersionString,
NV_VERSION_STRING,
sizeof(pInitDataCmd->driverVersionString));
pInitDataCmd->driverVersionString[sizeof(pInitDataCmd->driverVersionString) - 1] = 0;
nvswitch_os_memcpy(pInitDataCmd->driverVersionString,
NV_VERSION_STRING,
sizeof(NV_VERSION_STRING));
nvswitch_timeout_create(NVSWITCH_INTERVAL_1SEC_IN_NS, &timeout);
status = flcnQueueCmdPostBlocking(device, pFlcn,
src/common/nvswitch/kernel/nvswitch.c
+1 -1
View File
@@ -729,7 +729,7 @@ nvswitch_lib_check_api_version
}
nvswitch_os_memset(kernel_version, 0x0, length);
nvswitch_os_strncpy(kernel_version, NV_VERSION_STRING, VERSION_LENGTH);
nvswitch_os_memcpy(kernel_version, NV_VERSION_STRING, VERSION_LENGTH);
kernel_version[length - 1] = '\0';
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h
+1
View File
@@ -164,6 +164,7 @@ typedef struct NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS {
NvU32 comptaglineAllocationPolicy;
NV_DECLARE_ALIGNED(NvU64 privRegionStartOffset, 8);
NvU32 cbcCoveragePerSlice;
NV_DECLARE_ALIGNED(NvU64 cbcRegionSize, 8);
} NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS;
#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_UNKNOWN 0 // ADDR_UNKNOWN
src/nvidia-modeset/kapi/src/nvkms-kapi.c
+4 -2
View File
@@ -475,10 +475,12 @@ static NvBool KmsAllocateDevice(struct NvKmsKapiDevice *device)
/* Allocate NVKMS device */
nvkms_strncpy(
ct_assert(sizeof(NV_VERSION_STRING) <=
sizeof(paramsAlloc->request.versionString));
nvkms_memcpy(
paramsAlloc->request.versionString,
NV_VERSION_STRING,
sizeof(paramsAlloc->request.versionString));
sizeof(NV_VERSION_STRING));
paramsAlloc->request.deviceId.rmDeviceId = device->deviceInstance;
paramsAlloc->request.deviceId.migDevice = device->migDevice;
src/nvidia-modeset/os-interface/include/nvidia-modeset-os-interface.h
-3
View File
@@ -149,9 +149,6 @@ int nvkms_memcmp (const void *s1,
size_t nvkms_strlen (const char *s);
int nvkms_strcmp (const char *s1,
const char *s2);
char* nvkms_strncpy (char *dest,
const char *src,
size_t n);
void nvkms_usleep (NvU64 usec);
NvU64 nvkms_get_usec (void);
int nvkms_copyin (void *kptr,
src/nvidia-modeset/src/dp/nvdp-device.cpp
+4 -1
View File
@@ -124,7 +124,10 @@ void nvDPGetDpyGUID(NVDpyEvoPtr pDpyEvo)
str = nvkmsDisplayPort::nvDPGetDeviceGUIDStr(pDpLibDevice->device);
if (str != NULL) {
nvkms_strncpy(pDpyEvo->dp.guid.str, str, sizeof(pDpyEvo->dp.guid.str));
nvkms_snprintf(pDpyEvo->dp.guid.str,
sizeof(pDpyEvo->dp.guid.str),
"%s",
str);
} else {
pDpyEvo->dp.guid.valid = FALSE;
}
src/nvidia-modeset/src/nvkms-dpy.c
+5 -4
View File
@@ -2311,10 +2311,11 @@ static void PatchAndParseEdid(
for (i = 0; i < NVT_EDID_MAX_LONG_DISPLAY_DESCRIPTOR; i++) {
if (pParsedEdid->info.ldd[i].tag == NVT_EDID_DISPLAY_DESCRIPTOR_DPSN) {
nvkms_strncpy(
pParsedEdid->serialNumberString,
(const char *)pParsedEdid->info.ldd[i].u.serial_number.str,
sizeof(pParsedEdid->serialNumberString));
ct_assert(sizeof(pParsedEdid->info.ldd[i].u.serial_number.str) <
sizeof(pParsedEdid->serialNumberString));
nvkms_memcpy(pParsedEdid->serialNumberString,
pParsedEdid->info.ldd[i].u.serial_number.str,
sizeof(pParsedEdid->info.ldd[i].u.serial_number.str));
pParsedEdid->serialNumberString[
sizeof(pParsedEdid->serialNumberString) - 1] = '\0';
break;
src/nvidia-modeset/src/nvkms-modepool.c
+4 -3
View File
@@ -522,9 +522,10 @@ ValidateModeIndexEdid(NVDpyEvoPtr pDpyEvo,
if (description != NULL) {
nvAssert(nvkms_strlen(description) < sizeof(pReply->description));
nvkms_strncpy(pReply->description, description,
sizeof(pReply->description));
pReply->description[sizeof(pReply->description) - 1] = '\0';
nvkms_snprintf(pReply->description,
sizeof(pReply->description),
"%s",
description);
}
nvBuildModeName(kmsMode.timings.hVisible, kmsMode.timings.vVisible,
src/nvidia/arch/nvalloc/unix/include/nv.h
+9 -2
View File
@@ -660,6 +660,8 @@ struct nv_file_private_t
nv_file_private_t * PORT_ATOMIC ctl_nvfp;
void *ctl_nvfp_priv;
PORT_ATOMIC NvU32 register_or_refcount;
// In-flight nv_post_event() calls using this file private.
PORT_ATOMIC NvS32 event_posting_refcount;
//
// True if a client or an event was ever allocated on this fd.
@@ -668,6 +670,11 @@ struct nv_file_private_t
NvBool bCleanupRmapi;
};
static inline NvS32 nv_event_posting_refcount_read(nv_file_private_t *nvfp)
{
return *((volatile NvS32 *)&nvfp->event_posting_refcount);
}
// Forward define the gpu ops structures
typedef struct gpuSession *nvgpuSessionHandle_t;
typedef struct gpuDevice *nvgpuDeviceHandle_t;
@@ -969,9 +976,9 @@ void NV_API_CALL nv_unregister_sgt (nv_state_t *, struct sg_table
NV_STATUS NV_API_CALL nv_register_phys_pages (nv_state_t *, NvU64 *, NvU64, NvU32, void **);
void NV_API_CALL nv_unregister_phys_pages (nv_state_t *, void *);
NV_STATUS NV_API_CALL nv_dma_map_sgt (nv_dma_device_t *, NvU64, NvU64 *, NvU32, void **);
NV_STATUS NV_API_CALL nv_dma_map_sgt (nv_dma_device_t *, NvU64, NvU64 *, NvU32, NvBool, void **);
NV_STATUS NV_API_CALL nv_dma_map_alloc (nv_dma_device_t *, NvU64, NvU64 *, NvBool, void **);
NV_STATUS NV_API_CALL nv_dma_map_alloc (nv_dma_device_t *, NvU64, NvU64 *, NvBool, NvBool, void **);
NV_STATUS NV_API_CALL nv_dma_unmap_alloc (nv_dma_device_t *, NvU64, NvU64 *, void **);
NV_STATUS NV_API_CALL nv_dma_map_peer (nv_dma_device_t *, nv_dma_device_t *, NvU8, NvU64, NvU64 *);
src/nvidia/arch/nvalloc/unix/src/dynamic-power.c
+10 -3
View File
@@ -2343,6 +2343,7 @@ NV_STATUS RmGcxPowerManagement(
NvBool *bTryAgain
)
{
MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu);
KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu);
nv_state_t *nv = NV_GET_NV_STATE(pGpu);
nv_priv_t *nvp = NV_GET_NV_PRIV(nv);
@@ -2364,7 +2365,6 @@ NV_STATUS RmGcxPowerManagement(
if (bEnter)
{
MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu);
NvU64 usedFbSize = 0;
NvBool bCanUseGc6 = NV_FALSE;
NV_STATUS fbsrStatus = NV_ERR_GENERIC;
@@ -2429,7 +2429,11 @@ NV_STATUS RmGcxPowerManagement(
* might not be freed.
*/
fbsrFreeReservedSysMemoryForPowerMgmt(pMemoryManager->pFbsr[FBSR_TYPE_DMA]);
pKernelMemorySystem->bPreserveComptagBackingStoreOnSuspend = NV_FALSE;
if (!pMemoryManager->bUseVirtualCopyOnSuspend)
{
pKernelMemorySystem->bPreserveComptagBackingStoreOnSuspend = nv->preserve_vidmem_allocations;
}
}
}
else if (bCanUseGc6)
@@ -2503,7 +2507,10 @@ NV_STATUS RmGcxPowerManagement(
{
status = RmPowerManagement(pGpu, NV_PM_ACTION_RESUME);
pGpu->setProperty(pGpu, PDB_PROP_GPU_GCOFF_STATE_ENTERED, NV_FALSE);
pKernelMemorySystem->bPreserveComptagBackingStoreOnSuspend = NV_FALSE;
if (!pMemoryManager->bUseVirtualCopyOnSuspend)
{
pKernelMemorySystem->bPreserveComptagBackingStoreOnSuspend = nv->preserve_vidmem_allocations;
}
}
else if (pGpu->getProperty(pGpu, PDB_PROP_GPU_RG_STATE_ENTERED))
{
src/nvidia/arch/nvalloc/unix/src/escape.c
+13 -7
View File
@@ -138,6 +138,8 @@ static void RmCreateOsDescriptor(NVOS32_PARAMETERS *pApi, API_SECURITY_INFO secI
NvU32 flags = 0;
NvU64 allocSize, pageCount, *pPteArray = NULL;
void *pDescriptor, *pPageArray = NULL;
NVOS32_PARAMETERS allocApi = *pApi;
NVOS32_PARAMETERS *pAllocApi = &allocApi;
pDescriptor = NvP64_VALUE(pApi->data.AllocOsDesc.descriptor);
if (((NvUPtr)pDescriptor & ~os_page_mask) != 0)
@@ -162,26 +164,30 @@ static void RmCreateOsDescriptor(NVOS32_PARAMETERS *pApi, API_SECURITY_INFO secI
rmStatus = os_lock_user_pages(pDescriptor, pageCount, &pPageArray, flags);
if (rmStatus == NV_OK)
{
pApi->data.AllocOsDesc.descriptor = (NvP64)(NvUPtr)pPageArray;
pApi->data.AllocOsDesc.descriptorType = NVOS32_DESCRIPTOR_TYPE_OS_PAGE_ARRAY;
pAllocApi->data.AllocOsDesc.descriptor = (NvP64)(NvUPtr)pPageArray;
pAllocApi->data.AllocOsDesc.descriptorType = NVOS32_DESCRIPTOR_TYPE_OS_PAGE_ARRAY;
}
else if (rmStatus == NV_ERR_INVALID_ADDRESS)
{
rmStatus = os_lookup_user_io_memory(pDescriptor, pageCount, &pPteArray);
if (rmStatus == NV_OK)
{
pApi->data.AllocOsDesc.descriptor = (NvP64)(NvUPtr)pPteArray;
pApi->data.AllocOsDesc.descriptorType = NVOS32_DESCRIPTOR_TYPE_OS_IO_MEMORY;
pAllocApi->data.AllocOsDesc.descriptor = (NvP64)(NvUPtr)pPteArray;
pAllocApi->data.AllocOsDesc.descriptorType = NVOS32_DESCRIPTOR_TYPE_OS_IO_MEMORY;
}
}
if (rmStatus != NV_OK)
goto done;
Nv04VidHeapControlWithSecInfo(pApi, secInfo);
Nv04VidHeapControlWithSecInfo(pAllocApi, secInfo);
if (pApi->status != NV_OK)
pApi->status = pAllocApi->status;
pApi->data.AllocOsDesc.hMemory = pAllocApi->data.AllocOsDesc.hMemory;
if ((pAllocApi->status != NV_OK) &&
(pAllocApi->data.AllocOsDesc.descriptor != NvP64_NULL))
{
switch (pApi->data.AllocOsDesc.descriptorType)
switch (pAllocApi->data.AllocOsDesc.descriptorType)
{
default:
break;
src/nvidia/arch/nvalloc/unix/src/os.c
+82 -16
View File
@@ -1450,6 +1450,57 @@ void osUnmapGPU(
}
}
static NV_STATUS referenceEventForPost(
nv_event_t *event,
NvBool bDoRefCount,
nv_event_t *eventSnapshot,
nv_file_private_t **ppNvfp
)
{
nv_state_t *nv = nv_get_ctl_state();
portSyncSpinlockAcquire(nv->event_spinlock);
if (event->active == 0)
{
portSyncSpinlockRelease(nv->event_spinlock);
return NV_ERR_INVALID_EVENT;
}
if (bDoRefCount)
++event->refcount;
// Snapshot while event_spinlock still protects the event lifetime.
*eventSnapshot = *event;
*ppNvfp = eventSnapshot->nvfp;
portAtomicIncrementS32(&(*ppNvfp)->event_posting_refcount);
portSyncSpinlockRelease(nv->event_spinlock);
return NV_OK;
}
static void dereferenceEventForPost(
nv_event_t *event,
NvBool bDoRefCount,
nv_file_private_t *nvfp
)
{
if (bDoRefCount)
{
nv_state_t *nv = nv_get_ctl_state();
portSyncSpinlockAcquire(nv->event_spinlock);
NV_ASSERT(event->refcount > 0);
if (--event->refcount == 0 && !event->active)
portMemFree(event);
portSyncSpinlockRelease(nv->event_spinlock);
}
portAtomicDecrementS32(&nvfp->event_posting_refcount);
}
static void postEvent(
nv_event_t *event,
NvU32 hEvent,
@@ -1460,23 +1511,20 @@ static void postEvent(
NvBool bDoRefCount
)
{
if (bDoRefCount)
{
if (osReferenceObjectCount(event) != NV_OK)
return;
}
else
{
// Best effort. Can be changed in parallel by free_os_event.
if (event->active == 0)
return;
}
nv_event_t *eventToPost = event;
nv_post_event(event, hEvent, notifyIndex,
nv_file_private_t *nvfp = NULL;
nv_event_t eventSnapshot;
if (referenceEventForPost(event, bDoRefCount, &eventSnapshot, &nvfp) != NV_OK)
return;
eventToPost = &eventSnapshot;
nv_post_event(eventToPost, hEvent, notifyIndex,
info32, info16, dataValid);
if (bDoRefCount)
osDereferenceObjectCount(event);
dereferenceEventForPost(bDoRefCount ? event : NULL, bDoRefCount, nvfp);
}
NvU32 osSetEvent
@@ -3570,6 +3618,22 @@ static NvBool skipIovaMappingForTegra
return NV_FALSE;
}
static NvBool osMemDescRequiresReadOnlyDeviceDmaMap
(
MEMORY_DESCRIPTOR *pMemDesc
)
{
//
// MEMDESC_FLAGS_USER_READ_ONLY is also used by RM-owned buffers that the
// kernel writes and user/GSP reads. Restrict RO DMA direction to external
// OS descriptor mappings.
//
return memdescGetFlag(pMemDesc, MEMDESC_FLAGS_EXT_PAGE_ARRAY_MEM) &&
!memdescGetFlag(pMemDesc, MEMDESC_FLAGS_KERNEL_MODE) &&
(memdescGetFlag(pMemDesc, MEMDESC_FLAGS_USER_READ_ONLY) ||
memdescGetFlag(pMemDesc, MEMDESC_FLAGS_DEVICE_READ_ONLY));
}
/*!
* @brief Map memory into an IOVA space according to the given mapping info.
*
@@ -3730,11 +3794,14 @@ osIovaMap
if (!bIsBar0 && (!bIsFbOffset || bIsIndirectPeerMapping))
{
NvBool bReadOnlyDeviceMap =
osMemDescRequiresReadOnlyDeviceDmaMap(pIovaMapping->pPhysMemDesc);
status = nv_dma_map_alloc(
osGetDmaDeviceForMemDesc(nv, pIovaMapping->pPhysMemDesc),
osPageCount,
&pIovaMapping->iovaArray[0],
bIsContig, &pPriv);
bIsContig, bReadOnlyDeviceMap, &pPriv);
if (status != NV_OK)
{
NV_PRINTF(LEVEL_ERROR,
@@ -6290,4 +6357,3 @@ osCxlSetCaching
nv_pci_cxl_set_caching(nv, bEnableCache);
}
src/nvidia/arch/nvalloc/unix/src/osapi.c
+64 -12
View File
@@ -23,6 +23,7 @@
#include <nv_ref.h>
#include <nv.h>
#include <nv_escape.h>
@@ -643,7 +644,7 @@ done:
}
else
{
NV_PRINTF(LEVEL_ERROR, "failed to allocate OS event: 0x%08x\n", status);
NV_PRINTF(LEVEL_INFO, "failed to allocate OS event: 0x%08x\n", status);
status = NV_ERR_INSUFFICIENT_RESOURCES;
portMemFree(new_event);
}
@@ -945,7 +946,12 @@ static NV_STATUS RmAccessRegistry(
break;
case NVOS38_ACCESS_TYPE_WRITE_DWORD:
if (isDevice && osIsAdministrator())
if (!osIsAdministrator())
{
RmStatus = NV_ERR_INSUFFICIENT_PERMISSIONS;
break;
}
if (isDevice)
{
while ((pGpu = gpumgrGetNextGpu(gpuMask, &gpuInstance)) != NULL)
{
@@ -977,7 +983,12 @@ static NV_STATUS RmAccessRegistry(
break;
case NVOS38_ACCESS_TYPE_WRITE_BINARY:
if (isDevice && osIsAdministrator())
if (!osIsAdministrator())
{
RmStatus = NV_ERR_INSUFFICIENT_PERMISSIONS;
break;
}
if (isDevice)
{
while ((pGpu = gpumgrGetNextGpu(gpuMask, &gpuInstance)) != NULL)
{
@@ -1123,6 +1134,30 @@ done:
return status;
}
static void RmSanitizeLogString(
char *pString,
NvU32 stringLength
)
{
NvU32 i;
if (pString == NULL)
return;
for (i = 0; i < stringLength; i++)
{
NvU8 ch = (NvU8)pString[i];
if (ch == '\0')
return;
if ((ch < 0x20) || (ch == 0x7f))
{
pString[i] = '?';
}
}
}
static NV_STATUS RmPerformVersionCheck(
void *pData,
NvU32 dataSize
@@ -1217,6 +1252,9 @@ static NV_STATUS RmPerformVersionCheck(
procId = os_get_current_process();
os_get_current_process_name(procName, sizeof(procName));
RmSanitizeLogString(pParams->versionString, NV_RM_API_VERSION_STRING_LENGTH);
RmSanitizeLogString(procName, sizeof(procName));
nv_printf(NV_DBG_ERRORS,
"NVRM: API mismatch: the client '%s' (pid %u)\n"
"NVRM: has the version %s, but this kernel module has\n"
@@ -1404,6 +1442,10 @@ RmDmabufVerifyMemHandle(
}
pMemDesc = pSrcMemory->pMemDesc;
if (pMemDesc == NULL)
{
return NV_ERR_INVALID_STATE;
}
//
// We skip the partitionable heap check when the source memory is in
@@ -1582,7 +1624,7 @@ static NV_STATUS RmP2PDmaMapPages(
if (pageSize == os_page_size)
{
status = nv_dma_map_alloc(peer, pageCount, pDmaAddresses, NV_FALSE, ppPriv);
status = nv_dma_map_alloc(peer, pageCount, pDmaAddresses, NV_FALSE, NV_FALSE, ppPriv);
goto put_pgmap;
}
@@ -1617,7 +1659,7 @@ static NV_STATUS RmP2PDmaMapPages(
}
}
status = nv_dma_map_alloc(peer, osPageCount, pOsDmaAddresses, NV_FALSE, ppPriv);
status = nv_dma_map_alloc(peer, osPageCount, pOsDmaAddresses, NV_FALSE, NV_FALSE, ppPriv);
if (status != NV_OK)
{
goto failed;
@@ -5585,13 +5627,14 @@ NV_STATUS NV_API_CALL rm_dma_buf_dup_mem_handle(
)
{
MEMORY_DESCRIPTOR *pMemDesc;
THREAD_STATE_NODE threadState;
NV_STATUS rmStatus;
THREAD_STATE_NODE *pThreadState;
NV_STATUS rmStatus = NV_ERR_NO_MEMORY;
OBJGPU *pGpu;
void *fp;
NV_ENTER_RM_RUNTIME(sp,fp);
threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
pThreadState = threadStateAlloc(THREAD_STATE_FLAGS_NONE);
NV_ASSERT_OR_GOTO(pThreadState != NULL, Done);
pGpu = NV_GET_NV_PRIV_PGPU(nv);
@@ -5660,7 +5703,9 @@ NV_STATUS NV_API_CALL rm_dma_buf_dup_mem_handle(
(memdescGetAddressSpace(pMemDesc) == ADDR_FBMEM));
}
threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
Done:
if (pThreadState != NULL)
threadStateFree(pThreadState, THREAD_STATE_FLAGS_NONE);
NV_EXIT_RM_RUNTIME(sp,fp);
return rmStatus;
@@ -5718,14 +5763,20 @@ NV_STATUS NV_API_CALL rm_dma_buf_map_mem_handle(
MemoryArea *pMemArea
)
{
THREAD_STATE_NODE threadState;
THREAD_STATE_NODE *pThreadState;
NV_STATUS rmStatus = NV_ERR_INVALID_ARGUMENT;
OBJGPU *pGpu;
MEMORY_DESCRIPTOR *pMemDesc;
void *fp;
NV_ENTER_RM_RUNTIME(sp,fp);
threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
pThreadState = threadStateAlloc(THREAD_STATE_FLAGS_NONE);
if (pThreadState == NULL)
{
NV_ASSERT(0);
rmStatus = NV_ERR_NO_MEMORY;
goto Done;
}
NV_ASSERT_OR_GOTO(((pMemArea != NULL) &&
(pMemInfo != NULL)) &&
@@ -5844,7 +5895,8 @@ NV_STATUS NV_API_CALL rm_dma_buf_map_mem_handle(
}
Done:
threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
if (pThreadState != NULL)
threadStateFree(pThreadState, THREAD_STATE_FLAGS_NONE);
NV_EXIT_RM_RUNTIME(sp,fp);
return rmStatus;
src/nvidia/arch/nvalloc/unix/src/osmemdesc.c
+11
View File
@@ -212,6 +212,17 @@ osCreateMemdescFromPages
bUnprotected = NV_TRUE;
}
if (FLD_TEST_DRF(OS02, _FLAGS, _ALLOC_USER_READ_ONLY, _YES, flags))
{
memdescFlags |= MEMDESC_FLAGS_USER_READ_ONLY;
memdescFlags |= MEMDESC_FLAGS_DEVICE_READ_ONLY;
}
if (FLD_TEST_DRF(OS02, _FLAGS, _ALLOC_DEVICE_READ_ONLY, _YES, flags))
{
memdescFlags |= MEMDESC_FLAGS_DEVICE_READ_ONLY;
}
rmStatus = memdescCreate(ppMemDesc, pGpu, size, 0,
NV_MEMORY_NONCONTIGUOUS, ADDR_SYSMEM,
cacheType, memdescFlags);
src/nvidia/generated/g_bindata_kgspGetBinArchiveConcatenatedFMC_GB100.c
+26553 -26553
View File
File diff suppressed because it is too large Load Diff
src/nvidia/generated/g_bindata_kgspGetBinArchiveConcatenatedFMC_GB202.c
+29901 -29901
View File
File diff suppressed because it is too large Load Diff
src/nvidia/generated/g_bindata_kgspGetBinArchiveConcatenatedFMC_GH100.c
+25769 -25769
View File
File diff suppressed because it is too large Load Diff
src/nvidia/generated/g_bindata_kgspGetBinArchiveConcatenatedFMC_GR100.c
+26574 -26574
View File
File diff suppressed because it is too large Load Diff
src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c
+20634 -20634
View File
File diff suppressed because it is too large Load Diff
src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GB100.c
+12229 -12229
View File
File diff suppressed because it is too large Load Diff
src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GB202.c
+16069 -16069
View File
File diff suppressed because it is too large Load Diff
src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100.c
+10439 -10439
View File
File diff suppressed because it is too large Load Diff
src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GR100.c
+12229 -12229
View File
File diff suppressed because it is too large Load Diff
src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100.c
+10336 -10336
View File
File diff suppressed because it is too large Load Diff
src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100.c
+10359 -10359
View File
File diff suppressed because it is too large Load Diff
src/nvidia/generated/g_gpu_nvoc.c
+11
View File
@@ -563,6 +563,17 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) {
}
pThis->setProperty(pThis, PDB_PROP_GPU_HFRP_IS_KERNEL_OBJECT_ACTIVE_WAR, NV_FALSE);
// NVOC Property Hal field -- PDB_PROP_GPU_WAR_5656465_SUPPORTED
if (( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000006UL) )) /* ChipHal: GB202 | GB203 */
{
pThis->setProperty(pThis, PDB_PROP_GPU_WAR_5656465_SUPPORTED, NV_TRUE);
}
// default
else
{
pThis->setProperty(pThis, PDB_PROP_GPU_WAR_5656465_SUPPORTED, NV_FALSE);
}
pThis->deviceInstance = 32;
// Hal field -- isVirtual
src/nvidia/generated/g_gpu_nvoc.h
+4 -1
View File
@@ -1109,7 +1109,7 @@ struct OBJGPU {
NvU32 (*__gpuGetXtlBaseAddr__)(struct OBJGPU * /*this*/); // halified (3 hals) body
NvU32 (*__gpuGetPrimaryFuseBaseAddr__)(struct OBJGPU * /*this*/); // halified (2 hals) body
// 127 PDB properties
// 128 PDB properties
NvBool PDB_PROP_GPU_HIGH_SPEED_BRIDGE_CONNECTED;
NvBool PDB_PROP_GPU_IN_STANDBY;
NvBool PDB_PROP_GPU_IN_HIBERNATE;
@@ -1237,6 +1237,7 @@ struct OBJGPU {
NvBool PDB_PROP_GPU_RUSD_DISABLE_CLK_PUBLIC_DOMAIN_INFO;
NvBool PDB_PROP_GPU_ALLOC_ISO_SYS_MEM_FROM_CARVEOUT;
NvBool PDB_PROP_GPU_HFRP_IS_KERNEL_OBJECT_ACTIVE_WAR;
NvBool PDB_PROP_GPU_WAR_5656465_SUPPORTED;
// Data members
NvBool bVideoLinkDisabled;
@@ -1734,6 +1735,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU;
#define PDB_PROP_GPU_ALLOC_ISO_SYS_MEM_FROM_CARVEOUT_BASE_NAME PDB_PROP_GPU_ALLOC_ISO_SYS_MEM_FROM_CARVEOUT
#define PDB_PROP_GPU_HFRP_IS_KERNEL_OBJECT_ACTIVE_WAR_BASE_CAST
#define PDB_PROP_GPU_HFRP_IS_KERNEL_OBJECT_ACTIVE_WAR_BASE_NAME PDB_PROP_GPU_HFRP_IS_KERNEL_OBJECT_ACTIVE_WAR
#define PDB_PROP_GPU_WAR_5656465_SUPPORTED_BASE_CAST
#define PDB_PROP_GPU_WAR_5656465_SUPPORTED_BASE_NAME PDB_PROP_GPU_WAR_5656465_SUPPORTED
NV_STATUS __nvoc_objCreateDynamic_OBJGPU(Dynamic**, Dynamic*, NvU32, va_list);
src/nvidia/generated/g_kernel_bif_nvoc.c
+14 -3
View File
@@ -551,6 +551,17 @@ static void __nvoc_init_funcTable_KernelBif_1(KernelBif *pThis, GpuHalspecOwner
pThis->__kbifPollBarFirewallDisengage__ = &kbifPollBarFirewallDisengage_ac1694;
}
// kbifUpdateCplToWar5656465 -- halified (2 hals) body
if (( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000006UL) )) /* ChipHal: GB202 | GB203 */
{
pThis->__kbifUpdateCplToWar5656465__ = &kbifUpdateCplToWar5656465_GB202;
}
// default
else
{
pThis->__kbifUpdateCplToWar5656465__ = &kbifUpdateCplToWar5656465_d44104;
}
// kbifGetXveStatusBits -- halified (4 hals) body
if (( ((chipHal_HalVarIdx >> 5) == 3UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000e000UL) )) /* ChipHal: T234D | T239D | T264D */
{
@@ -1534,13 +1545,13 @@ static void __nvoc_init_funcTable_KernelBif_1(KernelBif *pThis, GpuHalspecOwner
{
pThis->__kbifDoCxlReset__ = &kbifDoCxlReset_395e98;
}
} // End __nvoc_init_funcTable_KernelBif_1 with approximately 221 basic block(s).
} // End __nvoc_init_funcTable_KernelBif_1 with approximately 223 basic block(s).
// Initialize vtable(s) for 85 virtual method(s).
// Initialize vtable(s) for 86 virtual method(s).
void __nvoc_init_funcTable_KernelBif(KernelBif *pThis, GpuHalspecOwner *pGpuhalspecowner, RmHalspecOwner *pRmhalspecowner) {
// Initialize vtable(s) with 72 per-object function pointer(s).
// Initialize vtable(s) with 73 per-object function pointer(s).
__nvoc_init_funcTable_KernelBif_1(pThis, pGpuhalspecowner, pRmhalspecowner);
}
src/nvidia/generated/g_kernel_bif_nvoc.h
+15 -1
View File
@@ -259,7 +259,7 @@ struct KernelBif {
struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; // engstate super
struct KernelBif *__nvoc_pbase_KernelBif; // kbif
// Vtable with 72 per-object function pointers
// Vtable with 73 per-object function pointers
NV_STATUS (*__kbifStatePostLoad__)(struct OBJGPU *, struct KernelBif * /*this*/, NvU32); // virtual halified (2 hals) override (engstate) base (engstate) body
void (*__kbifDestruct__)(struct KernelBif * /*this*/); // halified (2 hals) override (engstate) base (engstate) body
void (*__kbifInitLtr__)(struct OBJGPU *, struct KernelBif * /*this*/); // halified (3 hals) body
@@ -272,6 +272,7 @@ struct KernelBif {
NV_STATUS (*__kbifSavePcieConfigRegistersFn1__)(struct OBJGPU *, struct KernelBif * /*this*/, const PKBIF_XVE_REGMAP_REF, NvU32); // halified (2 hals) body
NV_STATUS (*__kbifRestorePcieConfigRegistersFn1__)(struct OBJGPU *, struct KernelBif * /*this*/, const PKBIF_XVE_REGMAP_REF, NvU32); // halified (2 hals) body
NV_STATUS (*__kbifPollBarFirewallDisengage__)(struct OBJGPU *, struct KernelBif * /*this*/); // halified (2 hals) body
void (*__kbifUpdateCplToWar5656465__)(struct OBJGPU *, struct KernelBif * /*this*/); // halified (2 hals) body
NV_STATUS (*__kbifGetXveStatusBits__)(struct OBJGPU *, struct KernelBif * /*this*/, NvU32 *, NvU32 *); // halified (4 hals) body
NV_STATUS (*__kbifClearXveStatus__)(struct OBJGPU *, struct KernelBif * /*this*/, NvU32 *); // halified (4 hals) body
NV_STATUS (*__kbifGetXveAerBits__)(struct OBJGPU *, struct KernelBif * /*this*/, NvU32 *); // halified (4 hals) body
@@ -720,6 +721,9 @@ static inline NV_STATUS kbifResetFromTimeoutFullChip(struct OBJGPU *pGpu, struct
#define kbifPollBarFirewallDisengage_FNPTR(pKernelBif) pKernelBif->__kbifPollBarFirewallDisengage__
#define kbifPollBarFirewallDisengage(pGpu, pKernelBif) kbifPollBarFirewallDisengage_DISPATCH(pGpu, pKernelBif)
#define kbifPollBarFirewallDisengage_HAL(pGpu, pKernelBif) kbifPollBarFirewallDisengage_DISPATCH(pGpu, pKernelBif)
#define kbifUpdateCplToWar5656465_FNPTR(pKernelBif) pKernelBif->__kbifUpdateCplToWar5656465__
#define kbifUpdateCplToWar5656465(pGpu, pKernelBif) kbifUpdateCplToWar5656465_DISPATCH(pGpu, pKernelBif)
#define kbifUpdateCplToWar5656465_HAL(pGpu, pKernelBif) kbifUpdateCplToWar5656465_DISPATCH(pGpu, pKernelBif)
#define kbifClearConfigErrors_HAL(pGpu, pKernelBif, arg3, arg4) kbifClearConfigErrors(pGpu, pKernelBif, arg3, arg4)
#define kbifGetXveStatusBits_FNPTR(pKernelBif) pKernelBif->__kbifGetXveStatusBits__
#define kbifGetXveStatusBits(pGpu, pKernelBif, pBits, pStatus) kbifGetXveStatusBits_DISPATCH(pGpu, pKernelBif, pBits, pStatus)
@@ -985,6 +989,10 @@ static inline NV_STATUS kbifPollBarFirewallDisengage_DISPATCH(struct OBJGPU *pGp
return pKernelBif->__kbifPollBarFirewallDisengage__(pGpu, pKernelBif);
}
static inline void kbifUpdateCplToWar5656465_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) {
pKernelBif->__kbifUpdateCplToWar5656465__(pGpu, pKernelBif);
}
static inline NV_STATUS kbifGetXveStatusBits_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pBits, NvU32 *pStatus) {
return pKernelBif->__kbifGetXveStatusBits__(pGpu, pKernelBif, pBits, pStatus);
}
@@ -1324,6 +1332,8 @@ NV_STATUS kbifRestorePcieConfigRegistersFn1_GB202(struct OBJGPU *pGpu, struct Ke
NV_STATUS kbifPollBarFirewallDisengage_GB202(struct OBJGPU *pGpu, struct KernelBif *pKernelBif);
void kbifUpdateCplToWar5656465_GB202(struct OBJGPU *pGpu, struct KernelBif *pKernelBif);
void kbifClearConfigErrors_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvBool arg3, NvU32 arg4);
NV_STATUS kbifGetXveStatusBits_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pBits, NvU32 *pStatus);
@@ -1609,6 +1619,10 @@ static inline NV_STATUS kbifPollBarFirewallDisengage_ac1694(struct OBJGPU *pGpu,
return NV_OK;
}
static inline void kbifUpdateCplToWar5656465_d44104(struct OBJGPU *pGpu, struct KernelBif *pKernelBif){
return;
}
static inline NV_STATUS kbifGetXveStatusBits_ac1694(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pBits, NvU32 *pStatus){
return NV_OK;
}
src/nvidia/generated/g_kernel_channel_nvoc.h
+1
View File
@@ -1595,6 +1595,7 @@ NV_STATUS kchannelGetNotifierInfo(struct OBJGPU *pGpu,
NvHandle hErrorContext,
MEMORY_DESCRIPTOR **ppMemDesc,
ErrorNotifierType *pNotifierType,
RsResourceRef **ppNotifierRef,
NvU64 *pOffset);
// Utils to iterate over ChannelDescendants on one Channels
src/nvidia/generated/g_nv_name_released.h
+4
View File
@@ -854,6 +854,10 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x2DB9, 0x0000, 0x0000, "NVIDIA RTX PRO 500 Blackwell Generation Laptop GPU" },
{ 0x2DD8, 0x0000, 0x0000, "NVIDIA GeForce RTX 5050 Laptop GPU" },
{ 0x2DF9, 0x0000, 0x0000, "NVIDIA RTX PRO 500 Blackwell Embedded GPU" },
{ 0x2E03, 0x1484, 0x1043, "NVIDIA RTX Spark N1X (6144-core Blackwell RTX GPU)" },
{ 0x2E03, 0x3309, 0x1043, "NVIDIA RTX Spark N1X (6144-core Blackwell RTX GPU)" },
{ 0x2E06, 0x1484, 0x1043, "NVIDIA RTX Spark N1X (5120-core Blackwell RTX GPU)" },
{ 0x2E06, 0x3309, 0x1043, "NVIDIA RTX Spark N1X (5120-core Blackwell RTX GPU)" },
{ 0x2E12, 0x21ec, 0x10de, "NVIDIA GB10" },
{ 0x2F04, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070" },
{ 0x2F06, 0x0000, 0x0000, "NVIDIA GeForce RTX 5060" },
src/nvidia/generated/g_subdevice_nvoc.c
+5 -5
View File
@@ -2305,11 +2305,11 @@ static NV_STATUS subdeviceCtrlCmdEventSetTrigger__EXPORT(void *pSubdevice) {
}
#endif // !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x00000008u)
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x00000009u)
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x00000109u)
static NV_STATUS subdeviceCtrlCmdEventSetTriggerFifo__EXPORT(void *pSubdevice, void *pTriggerFifoParams) {
return subdeviceCtrlCmdEventSetTriggerFifo_IMPL(pSubdevice, pTriggerFifoParams);
}
#endif // !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x00000009u)
#endif // !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x00000109u)
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x00010118u)
static NV_STATUS subdeviceCtrlCmdEventSetNotification__EXPORT(void *pSubdevice, void *pSetEventParams) {
@@ -5609,12 +5609,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
#endif
},
{ /* [108] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x9u)
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x109u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
/*pFunc=*/ (void (*)(void)) &subdeviceCtrlCmdEventSetTriggerFifo__EXPORT,
#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x9u)
/*flags=*/ 0x9u,
#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x109u)
/*flags=*/ 0x109u,
/*accessRight=*/0x0u,
/*methodId=*/ 0x20800308u,
/*paramSize=*/ sizeof(NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS),
src/nvidia/interface/deprecated/rmapi_deprecated_vidheapctrl.c
+2
View File
@@ -576,5 +576,7 @@ _nvos32FunctionAllocOsDesc
&allocParams,
sizeof(allocParams));
pArgs->data.AllocOsDesc.descriptor = allocParams.descriptor;
return status;
}
src/nvidia/src/kernel/compute/fabric.c
-3
View File
@@ -270,10 +270,7 @@ static NV_STATUS
_fabricNotifyEvent(Fabric *pFabric)
{
if (pFabric->pOsImexEvent == NULL)
{
NV_PRINTF(LEVEL_ERROR, "Unable to notify ImexSessionApi\n");
return NV_ERR_NOT_READY;
}
osSetEvent(NULL, pFabric->pOsImexEvent);
src/nvidia/src/kernel/diagnostics/ucode_instrumentation_ctrl.c
+34
View File
@@ -38,6 +38,24 @@
#include "core/system.h"
#include "kernel/vgpu/rpc.h"
#include "diagnostics/instrumentation_manager.h"
#include "virtualization/common_vgpu_mgr.h"
static NV_STATUS
_diagapiCtrlCmdUcodeInstrumentationValidateGfid
(
NvU32 ucode,
NvU32 gfid
)
{
if (ucode == NV208F_UCODE_INSTRUMENTATION_GSP_TASK_VGPU)
{
NV_CHECK_OR_RETURN(LEVEL_ERROR,
gfid > 0 && gfid <= VGPU_MAX_GFID,
NV_ERR_INVALID_ARGUMENT);
}
return NV_OK;
}
NV_STATUS
diagapiCtrlCmdUcodeInstrumentationGetState_IMPL
@@ -54,6 +72,9 @@ diagapiCtrlCmdUcodeInstrumentationGetState_IMPL
return NV_ERR_NOT_SUPPORTED;
}
NV_CHECK_OK_OR_RETURN(LEVEL_ERROR,
_diagapiCtrlCmdUcodeInstrumentationValidateGfid(pParams->ucode, pParams->gfid));
internalParams.ucode = pParams->ucode;
internalParams.gfid = pParams->gfid;
internalParams.bEnabled = pParams->bEnabled;
@@ -91,6 +112,9 @@ diagapiCtrlCmdUcodeInstrumentationSetState_IMPL
return NV_ERR_NOT_SUPPORTED;
}
NV_CHECK_OK_OR_RETURN(LEVEL_ERROR,
_diagapiCtrlCmdUcodeInstrumentationValidateGfid(pParams->ucode, pParams->gfid));
internalParams.ucode = pParams->ucode;
internalParams.gfid = pParams->gfid;
internalParams.bEnabled = pParams->bEnabled;
@@ -132,6 +156,9 @@ diagapiCtrlCmdUcodeInstrumentationGetData_IMPL
return NV_ERR_NOT_SUPPORTED;
}
NV_CHECK_OK_OR_RETURN(LEVEL_ERROR,
_diagapiCtrlCmdUcodeInstrumentationValidateGfid(pParams->ucode, pParams->gfid));
pInternalParams = portMemAllocNonPaged(sizeof(*pInternalParams));
if (pInternalParams == NULL)
{
@@ -170,6 +197,13 @@ diagapiCtrlCmdUcodeInstrumentationGetData_IMPL
OBJSYS *pSys = SYS_GET_INSTANCE();
NvU8 *pBuffer;
if ((pParams->offset > BULLSEYE_GSP_RM_COVERAGE_SIZE) ||
(pParams->dataSize > (BULLSEYE_GSP_RM_COVERAGE_SIZE - pParams->offset)))
{
portMemFree(pInternalParams);
return NV_ERR_INVALID_ARGUMENT;
}
// Merge this chunk of data into the instrumentation buffer
instrumentationmanagerMerge(pSys->pInstrumentationManager,
pParams->gfid,
src/nvidia/src/kernel/gpu/bif/arch/blackwell/kernel_bif_gb202.c
+40
View File
@@ -28,6 +28,46 @@
#include "published/blackwell/gb202/dev_xtl_ep_pcfg_gpu.h"
#include "published/blackwell/gb202/dev_xtl_ep_pri.h"
/*!
* @brief Safety net for updating completion timeout value
*
* @param[in] pGpu GPU object pointer
* @param[in] pKernelBif Kernel BIF object pointer
*/
void
kbifUpdateCplToWar5656465_GB202
(
OBJGPU *pGpu,
KernelBif *pKernelBif
)
{
NvU32 regVal = 0;
NvU32 rangeC = 0x9;
if (gpuIsGeforceBranded(pGpu))
{
return;
}
if (GPU_BUS_CFG_CYCLE_RD32(pGpu, NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_2, &regVal) != NV_OK)
{
NV_PRINTF(LEVEL_ERROR, "Unable to read NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_2\n");
return;
}
if (FLD_TEST_DRF(_EP_PCFG_GPU, _DEVICE_CONTROL_STATUS_2, _CPL_TIMEOUT_VALUES, _DEFAULT, regVal))
{
regVal = FLD_SET_DRF_NUM(_EP_PCFG_GPU, _DEVICE_CONTROL_STATUS_2, _CPL_TIMEOUT_VALUES, rangeC, regVal);
if (GPU_BUS_CFG_CYCLE_WR32(pGpu, NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_2, regVal) != NV_OK)
{
NV_PRINTF(LEVEL_ERROR,
"Unable to write NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_2\n");
return;
}
}
}
/*!
* @brief Save PCIe Config space for Fn1
*
src/nvidia/src/kernel/gpu/bif/kernel_bif.c
+3
View File
@@ -162,6 +162,9 @@ kbifStateLoad_IMPL
{
NV_PRINTF(LEVEL_INFO, "BIF DMA Caps: %08x\n", kbifGetDmaCaps(pGpu, pKernelBif));
// Apply CPL TO value safety net
kbifUpdateCplToWar5656465_HAL(pGpu, pKernelBif);
// Apply C73 chipset WAR
kbifExecC73War_HAL(pGpu, pKernelBif);
src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c
+5 -3
View File
@@ -644,14 +644,16 @@ kbusRestoreBar2_GM107
if (status == NV_OK)
break;
else if (status == NV_ERR_TIMEOUT)
if (gpuCheckTimeout(pGpu, &timeout) == NV_ERR_TIMEOUT)
{
NV_PRINTF(LEVEL_ERROR, "kbusVerifyBar2_HAL() keeps failing.\n");
NV_PRINTF(LEVEL_ERROR,
"kbusVerifyBar2_HAL() keeps failing, bailout with status 0x%08x.\n",
status);
DBG_BREAKPOINT();
break;
}
status = gpuCheckTimeout(pGpu, &timeout);
osSpinLoop();
} while (1);
}
src/nvidia/src/kernel/gpu/ce/arch/blackwell/kernel_ce_gb100.c
+11
View File
@@ -235,6 +235,13 @@ kceGetMappingsForMIGGpuInstance_GB100
NvU32 i;
NVLINK_TOPOLOGY_PARAMS *pTopoParams;
if ((lceAvailableMask & shimLceMask) == 0x0)
{
// No LCEs to map on this shim instance
NV_PRINTF(LEVEL_INFO, "No LCEs available to map\n");
return NV_OK;
}
//
// Initialize the pceAvailableMask to include all PCEs.
// Iterate over all HSHUBs in both shims to generate a mask of PCEs available.
@@ -312,6 +319,8 @@ kceGetMappingsForMIGGpuInstance_GB100
pcesLocalAvailable = pcesLocalAvailable & ~NVBIT32(pceIdx);
pcesForEvenLces = pcesForEvenLces & ~NVBIT32(pceIdx);
pLocalPceLceMap[pceIdx] = lceIdx % NV_KCE_GROUP_ID_STRIDE;
NV_PRINTF(LEVEL_INFO, "GPU%d Mapping PCE %d to LCE %d\n",
gpuGetInstance(pGpu), pceIdx, lceIdx);
}
}
numLcesMapped++;
@@ -353,6 +362,8 @@ kceGetMappingsForMIGGpuInstance_GB100
pLocalPceLceMap[pceIdx] = lceIdx % NV_KCE_GROUP_ID_STRIDE; //shim consideration
numPcesMapped++;
NV_PRINTF(LEVEL_INFO, "GPU%d Mapping PCE %d to LCE %d\n",
gpuGetInstance(pGpu), pceIdx, lceIdx);
// Due to FS limitations regardless of min PCE request, only assign half the PCEs
if (numPcesMapped >= (numMinPcesPerLce / 2))
{
src/nvidia/src/kernel/gpu/device.c
+38
View File
@@ -54,6 +54,8 @@
static NV_STATUS _deviceTeardown(Device *pDevice, CALL_CONTEXT *pCallContext);
static NV_STATUS _deviceTeardownRef(Device *pDevice, CALL_CONTEXT *pCallContext);
static NV_STATUS _deviceValidateClientShare(Device *pDevice, CALL_CONTEXT *pCallContext,
NvHandle hClientShare);
static NV_STATUS _deviceInit(Device *pDevice, CALL_CONTEXT *pCallContext,
NvHandle hClient, NvHandle hDevice, NvU32 deviceInst,
NvHandle hClientShare, NvHandle hTargetClient, NvHandle hTargetDevice,
@@ -193,6 +195,38 @@ deviceConstruct_IMPL
return rmStatus;
} // end of deviceConstruct_IMPL
static NV_STATUS
_deviceValidateClientShare
(
Device *pDevice,
CALL_CONTEXT *pCallContext,
NvHandle hClientShare
)
{
OBJGPU *pGpu = GPU_RES_GET_GPU(pDevice);
RsClient *pClientShare = NULL;
NV_STATUS status;
if ((hClientShare == NV01_NULL_OBJECT) ||
(hClientShare == pCallContext->pClient->hClient))
{
return NV_OK;
}
if (IS_VIRTUAL_WITH_SRIOV(pGpu) &&
gpuIsSplitVasManagementServerClientRmEnabled(pGpu) &&
(hClientShare == pGpu->hDefaultClientShare))
{
return NV_OK;
}
status = serverGetClientUnderLock(&g_resServ, hClientShare, &pClientShare);
if (status != NV_OK)
return status;
return clientValidate(pClientShare, &pCallContext->secInfo);
}
void
deviceDestruct_IMPL
(
@@ -410,6 +444,10 @@ _deviceInit
}
}
status = _deviceValidateClientShare(pDevice, pCallContext, hClientShare);
if (status != NV_OK)
goto done;
status = deviceSetClientShare(pDevice, hClientShare, vaSize,
vaStartInternal, vaLimitInternal, allocFlags);
if (NV_OK != status)
src/nvidia/src/kernel/gpu/device_share.c
+31
View File
@@ -21,6 +21,8 @@
* DEALINGS IN THE SOFTWARE.
*/
#include "core/core.h"
#include "os/os.h"
#include "mem_mgr/virt_mem_mgr.h"
@@ -83,6 +85,31 @@ deviceSetClientShare_IMPL
return NV_OK;
}
static NvBool
deviceIsClientShareRoot
(
Device *pDevice,
NvHandle hClientShare
)
{
OBJGPU *pGpu = GPU_RES_GET_GPU(pDevice);
if ((hClientShare == NV01_NULL_OBJECT) ||
(hClientShare == RES_GET_CLIENT_HANDLE(pDevice)))
{
return NV_TRUE;
}
if (IS_VIRTUAL_WITH_SRIOV(pGpu) &&
gpuIsSplitVasManagementServerClientRmEnabled(pGpu) &&
(hClientShare == pGpu->hDefaultClientShare))
{
return NV_TRUE;
}
return NV_FALSE;
}
/*!
* @brief Initialize the device VASPACE
*/
@@ -270,6 +297,10 @@ deviceInitClientShare
// Init target share if needed
if (pShareDevice->pVASpace == NULL)
{
// Only lazily initialize concrete VASpace roots, not share chains.
if (!deviceIsClientShareRoot(pShareDevice, pShareDevice->hClientShare))
return NV_ERR_INVALID_ARGUMENT;
status = deviceInitClientShare(pShareDevice,
pShareDevice->hClientShare,
pShareDevice->vaSize,
src/nvidia/src/kernel/gpu/falcon/kernel_crashcat_engine.c
+3 -3
View File
@@ -101,6 +101,8 @@ MEMORY_DESCRIPTOR *kcrashcatEngineGetQueueMemDesc_IMPL(KernelCrashCatEngine *pKe
void kcrashcatEngineUnload_IMPL(KernelCrashCatEngine *pKernelCrashCatEng)
{
crashcatEngineUnload_IMPL(staticCast(pKernelCrashCatEng, CrashCatEngine));
if (pKernelCrashCatEng->pQueueMemDesc != NULL)
{
kcrashcatEngineUnregisterCrashBuffer(pKernelCrashCatEng, pKernelCrashCatEng->pQueueMemDesc);
@@ -108,8 +110,6 @@ void kcrashcatEngineUnload_IMPL(KernelCrashCatEngine *pKernelCrashCatEng)
memdescDestroy(pKernelCrashCatEng->pQueueMemDesc);
pKernelCrashCatEng->pQueueMemDesc = NULL;
}
crashcatEngineUnload_IMPL(staticCast(pKernelCrashCatEng, CrashCatEngine));
}
NvU32 kcrashcatEnginePriRead_IMPL
@@ -348,4 +348,4 @@ void kcrashcatEngineSetErrorId_IMPL
)
{
pKernelCrashCatEng->errorId = errorId;
}
}
src/nvidia/src/kernel/gpu/fifo/kernel_channel.c
+52 -8
View File
@@ -137,7 +137,10 @@ kchannelConstruct_IMPL
RmClient *pRmClient = NULL;
RsResourceRef *pResourceRef = pCallContext->pResourceRef;
RsResourceRef *pKernelCtxShareRef = NULL;
RsResourceRef *pErrorContextRef = NULL;
RsResourceRef *pEccErrorContextRef = NULL;
NV_STATUS status;
NV_STATUS notifierStatus;
RM_API *pRmApi = NULL;
NvHandle hClient = pRsClient->hClient;
NvHandle hParent = pResourceRef->pParentRef->hResource;
@@ -163,6 +166,8 @@ kchannelConstruct_IMPL
NvBool bRpcAllocated = NV_FALSE;
NvBool bFullSriov = IS_VIRTUAL_WITH_SRIOV(pGpu) && !gpuIsWarBug200577889SriovHeavyEnabled(pGpu);
NvBool bAddedToGroup = NV_FALSE;
NvBool bErrorContextDepAdded = NV_FALSE;
NvBool bEccErrorContextDepAdded = NV_FALSE;
NvU32 callingContextGfid;
Device *pDevice;
NvBool bUvmOwnedFlag;
@@ -517,13 +522,25 @@ kchannelConstruct_IMPL
}
else if (!(RMCFG_FEATURE_PLATFORM_GSP && !pKernelChannel->bGspOwned))
{
NV_ASSERT_OK(kchannelGetNotifierInfo(pGpu, pDevice,
notifierStatus = kchannelGetNotifierInfo(pGpu, pDevice,
pKernelChannel->hErrorContext,
&pKernelChannel->pErrContextMemDesc,
&pKernelChannel->errorContextType,
&pKernelChannel->errorContextOffset));
NV_ASSERT(pKernelChannel->errorContextType !=
ERROR_NOTIFIER_TYPE_NONE);
&pErrorContextRef,
&pKernelChannel->errorContextOffset);
NV_ASSERT_OK(notifierStatus);
if (notifierStatus == NV_OK)
{
if (pErrorContextRef != NULL)
{
NV_ASSERT_OK_OR_GOTO(status,
refAddDependant(pErrorContextRef, pResourceRef),
cleanup);
bErrorContextDepAdded = NV_TRUE;
}
NV_ASSERT(pKernelChannel->errorContextType !=
ERROR_NOTIFIER_TYPE_NONE);
}
}
if (pKernelChannel->hEccErrorContext == NV01_NULL_OBJECT)
{
@@ -531,13 +548,26 @@ kchannelConstruct_IMPL
}
else if (!(RMCFG_FEATURE_PLATFORM_GSP && !pKernelChannel->bGspOwned))
{
NV_ASSERT_OK(kchannelGetNotifierInfo(pGpu, pDevice,
notifierStatus = kchannelGetNotifierInfo(pGpu, pDevice,
pKernelChannel->hEccErrorContext,
&pKernelChannel->pEccErrContextMemDesc,
&pKernelChannel->eccErrorContextType,
&pKernelChannel->eccErrorContextOffset));
NV_ASSERT(pKernelChannel->eccErrorContextType !=
ERROR_NOTIFIER_TYPE_NONE);
&pEccErrorContextRef,
&pKernelChannel->eccErrorContextOffset);
NV_ASSERT_OK(notifierStatus);
if (notifierStatus == NV_OK)
{
if ((pEccErrorContextRef != NULL) &&
(pEccErrorContextRef != pErrorContextRef))
{
NV_ASSERT_OK_OR_GOTO(status,
refAddDependant(pEccErrorContextRef, pResourceRef),
cleanup);
bEccErrorContextDepAdded = NV_TRUE;
}
NV_ASSERT(pKernelChannel->eccErrorContextType !=
ERROR_NOTIFIER_TYPE_NONE);
}
}
if (IS_GSP_CLIENT(pGpu) || bFullSriov)
@@ -1076,6 +1106,14 @@ cleanup:
if (status != NV_OK)
{
// Remove any dependencies we may have added; we don't want our destructor called when freeing anything below
if (bEccErrorContextDepAdded)
{
refRemoveDependant(pEccErrorContextRef, pResourceRef);
}
if (bErrorContextDepAdded)
{
refRemoveDependant(pErrorContextRef, pResourceRef);
}
if (pKernelGraphicsContext != NULL)
{
refRemoveDependant(RES_GET_REF(pKernelGraphicsContext), pResourceRef);
@@ -1878,6 +1916,7 @@ kchannelGetNotifierInfo
NvHandle hErrorContext,
MEMORY_DESCRIPTOR **ppMemDesc,
ErrorNotifierType *pNotifierType,
RsResourceRef **ppNotifierRef,
NvU64 *pOffset
)
{
@@ -1887,9 +1926,11 @@ kchannelGetNotifierInfo
NV_ASSERT_OR_RETURN(ppMemDesc != NULL, NV_ERR_INVALID_PARAMETER);
NV_ASSERT_OR_RETURN(pNotifierType != NULL, NV_ERR_INVALID_PARAMETER);
NV_ASSERT_OR_RETURN(ppNotifierRef != NULL, NV_ERR_INVALID_PARAMETER);
*ppMemDesc = NULL;
*pNotifierType = ERROR_NOTIFIER_TYPE_UNKNOWN;
*ppNotifierRef = NULL;
*pOffset = 0;
if (hErrorContext == NV01_NULL_OBJECT)
@@ -1958,12 +1999,14 @@ kchannelGetNotifierInfo
*ppMemDesc = pDmaMappingInfo->pMemDesc;
// The notifier format here is struct NOTIFICATION, same as ctxdma
*pNotifierType = ERROR_NOTIFIER_TYPE_CTXDMA;
*ppNotifierRef = RES_GET_REF(pMemory);
*pOffset = offset;
}
else
{
*ppMemDesc = pMemory->pMemDesc;
*pNotifierType = ERROR_NOTIFIER_TYPE_MEMORY;
*ppNotifierRef = RES_GET_REF(pMemory);
}
return NV_OK;
}
@@ -1972,6 +2015,7 @@ kchannelGetNotifierInfo
{
*ppMemDesc = pContextDma->pMemDesc;
*pNotifierType = ERROR_NOTIFIER_TYPE_CTXDMA;
*ppNotifierRef = RES_GET_REF(pContextDma);
return NV_OK;
}
src/nvidia/src/kernel/gpu/fifo/kernel_fifo_ctrl.c
+53 -18
View File
@@ -30,6 +30,9 @@
#include "kernel/gpu/mem_mgr/mem_mgr.h"
#include "kernel/virtualization/hypervisor/hypervisor.h"
#include "kernel/core/locks.h"
#include "kernel/core/system.h"
#include "kernel/rmapi/client.h"
#include "kernel/rmapi/rs_utils.h"
#include "lib/base_utils.h"
#include "platform/sli/sli.h"
@@ -45,6 +48,35 @@
#include "kernel/gpu/conf_compute/conf_compute.h"
static NV_STATUS _kfifoGetCaps(OBJGPU *pGpu, NvU8 *pKfifoCaps);
static NV_STATUS
_kfifoValidateTargetClient
(
NvHandle hClient
)
{
CALL_CONTEXT *pCallContext = resservGetTlsCallContext();
OBJSYS *pSys = SYS_GET_INSTANCE();
NV_ASSERT_OR_RETURN(pCallContext != NULL, NV_ERR_INVALID_STATE);
NV_ASSERT_OR_RETURN(pCallContext->pClient != NULL, NV_ERR_INVALID_CLIENT);
NV_ASSERT_OR_RETURN(pSys != NULL, NV_ERR_INVALID_STATE);
if (pCallContext->pClient->hClient == hClient)
{
return NV_OK;
}
if ((pCallContext->secInfo.privLevel >= RS_PRIV_LEVEL_USER_ROOT) ||
!pSys->getProperty(pSys, PDB_PROP_SYS_VALIDATE_CLIENT_HANDLE))
{
return NV_OK;
}
return osValidateClientTokens(
(void *)rmclientGetSecurityTokenByHandle(pCallContext->pClient->hClient),
(void *)rmclientGetSecurityTokenByHandle(hClient));
}
/*!
* @brief deviceCtrlCmdFifoGetChannelList
*/
@@ -602,15 +634,17 @@ diagapiCtrlCmdFifoGetChannelState_IMPL
)
{
OBJGPU *pGpu = GPU_RES_GET_GPU(pDiagApi);
RsClient *pChannelClient;
RsResourceRef *pResourceRef;
KernelChannel *pKernelChannel;
NV_CHECK_OK_OR_RETURN(LEVEL_INFO,
serverGetClientUnderLock(&g_resServ, pChannelStateParams->hClient,
&pChannelClient));
_kfifoValidateTargetClient(pChannelStateParams->hClient));
NV_CHECK_OK_OR_RETURN(LEVEL_INFO,
CliGetKernelChannel(pChannelClient, pChannelStateParams->hChannel, &pKernelChannel));
serverutilGetResourceRefWithType(pChannelStateParams->hClient,
pChannelStateParams->hChannel,
classId(KernelChannel),
&pResourceRef));
pKernelChannel = dynamicCast(pResourceRef->pResource, KernelChannel);
NV_CHECK_OK_OR_RETURN(LEVEL_INFO,
kchannelGetChannelPhysicalState(pGpu, pKernelChannel, pChannelStateParams));
@@ -1008,7 +1042,6 @@ subdeviceCtrlCmdFifoQueryChannelUniqueId_IMPL
NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS *pGetChannelUidParams
)
{
RsClient *pRsClient = NULL;
RsResourceRef *pResourceRef = NULL;
KernelChannel *pKernelChannel = NULL;
NvU32 i;
@@ -1021,11 +1054,12 @@ subdeviceCtrlCmdFifoQueryChannelUniqueId_IMPL
{
NV_CHECK_OK_OR_RETURN(LEVEL_INFO,
serverGetClientUnderLock(&g_resServ, pGetChannelUidParams->hClients[i], &pRsClient));
_kfifoValidateTargetClient(pGetChannelUidParams->hClients[i]));
NV_CHECK_OK_OR_RETURN(LEVEL_INFO,
clientGetResourceRefByType(pRsClient, pGetChannelUidParams->hChannels[i],
classId(KernelChannel), &pResourceRef));
serverutilGetResourceRefWithType(pGetChannelUidParams->hClients[i],
pGetChannelUidParams->hChannels[i],
classId(KernelChannel),
&pResourceRef));
pKernelChannel = dynamicCast(pResourceRef->pResource, KernelChannel);
pGetChannelUidParams->channelUniqueIDs[i] = kchannelGetCid(pKernelChannel);
}
@@ -1039,7 +1073,6 @@ subdeviceCtrlCmdFifoGetChannelGroupUniqueIdInfo_IMPL
NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS *pGetCidGrpParams
)
{
RsClient *pRsClient = NULL;
RsResourceRef *pResourceRef = NULL;
KernelChannelGroupApi *pKernelChannelGroupApi = NULL;
KernelChannelGroup *pKernelChannelGroup = NULL;
@@ -1047,18 +1080,20 @@ subdeviceCtrlCmdFifoGetChannelGroupUniqueIdInfo_IMPL
NV_STATUS status;
NV_CHECK_OK_OR_RETURN(LEVEL_INFO,
serverGetClientUnderLock(&g_resServ, pGetCidGrpParams->hClient, &pRsClient));
_kfifoValidateTargetClient(pGetCidGrpParams->hClient));
status = clientGetResourceRefByType(pRsClient, pGetCidGrpParams->hChannelOrTsg,
classId(KernelChannelGroupApi),
&pResourceRef);;
status = serverutilGetResourceRefWithType(pGetCidGrpParams->hClient,
pGetCidGrpParams->hChannelOrTsg,
classId(KernelChannelGroupApi),
&pResourceRef);
if (status != NV_OK)
{
// if its not a channel Group, check if its a Kernel Channel.
NV_CHECK_OK_OR_RETURN(LEVEL_INFO,
clientGetResourceRefByType(pRsClient, pGetCidGrpParams->hChannelOrTsg,
classId(KernelChannel),
&pResourceRef));
serverutilGetResourceRefWithType(pGetCidGrpParams->hClient,
pGetCidGrpParams->hChannelOrTsg,
classId(KernelChannel),
&pResourceRef));
pKernelChannel = dynamicCast(pResourceRef->pResource, KernelChannel);
src/nvidia/src/kernel/gpu/gr/kernel_sm_debugger_session_ctrl.c
+4 -1
View File
@@ -120,6 +120,10 @@ _nv8deCtrlCmdReadWriteSurface
NV_ERR_INVALID_ARGUMENT);
NvU64 offsetInMapping = virtAddr - pDmaMappingInfo->DmaOffset;
// Validate offset is within mapping bounds to prevent integer underflow
NV_CHECK_OR_RETURN(LEVEL_ERROR,
offsetInMapping < pDmaMappingInfo->pMemDesc->Size,
NV_ERR_INVALID_OFFSET);
curSize = NV_MIN(curSize, pDmaMappingInfo->pMemDesc->Size - offsetInMapping);
TRANSFER_SURFACE surf = { .pMemDesc = pDmaMappingInfo->pMemDesc, .offset = offsetInMapping };
@@ -870,4 +874,3 @@ ksmdbgssnCtrlCmdDebugReadMMUFaultInfo_IMPL
return NV_OK;
}
src/nvidia/src/kernel/gpu/gsp/kernel_gsp_trace_rats.c
+14 -1
View File
@@ -27,6 +27,7 @@
*/
#include "gpu/gsp/kernel_gsp_trace_rats.h"
#include "nvport/nvport.h"
#include "rmapi/client.h"
#include "rmapi/event_api.h"
@@ -41,6 +42,8 @@
#include "gpu/mem_mgr/mem_mgr.h"
#include "gpu/timer/objtmr.h"
#define GSP_TRACE_BUFFER_ALLOC_SIZE_MAX (1 * 1024 * 1024) // 1 MB
static
NV_STATUS
_gspTraceEventBufferAdd
@@ -259,7 +262,17 @@ gspTraceAddBindpoint
if (IS_VIRTUAL(pGpu))
{
NvU32 allocBufferSize = gspTracingBufferSize * sizeof(NV_RATS_GSP_TRACE_RECORD) + sizeof(NV_RATS_VGPU_GSP_TRACING_BUFFER);
NvU32 allocBufferSize;
NvU32 mulResult;
NV_CHECK_OR_RETURN(LEVEL_ERROR,
portSafeMulU32(gspTracingBufferSize, (NvU32)sizeof(NV_RATS_GSP_TRACE_RECORD), &mulResult),
NV_ERR_INVALID_ARGUMENT);
NV_CHECK_OR_RETURN(LEVEL_ERROR,
portSafeAddU32(mulResult, (NvU32)sizeof(NV_RATS_VGPU_GSP_TRACING_BUFFER), &allocBufferSize),
NV_ERR_INVALID_ARGUMENT);
NV_CHECK_OR_RETURN(LEVEL_ERROR, allocBufferSize <= GSP_TRACE_BUFFER_ALLOC_SIZE_MAX,
NV_ERR_INVALID_ARGUMENT);
NV_ASSERT_OK_OR_GOTO(status,
memdescCreate(&(pBind->pMemDesc),
pGpu,
src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/virt_mem_allocator_gm107.c
+3 -1
View File
@@ -219,6 +219,7 @@ static NV_STATUS _dmaGetMaxVAPageSize
// RM will look to make sure that:
// 1. The page size aligned down vaAddr does not underflow the VA surface.
// 2. The physical size of the allocation, when aligned up to the page size does not overflow the end of the VA surface.
// 3. The provided GPU VA is aligned to chosen page size, or GPU VA is aligned to page size after phys offset adjustment.
//
// Passing both checks ensures that the VA surface is compatible for mapping the surface
// at the selected (and smaller) page size(s).
@@ -232,7 +233,8 @@ static NV_STATUS _dmaGetMaxVAPageSize
if ((alignedVA >= targetSpaceBase) &&
(NV_ALIGN_UP64(alignedVA + physOffset + physSize, pageSize) - 1) <= targetSpaceLimit &&
(NV_ALIGN_UP64(physOffset + physSize, pageSize)) <= memDescribedSize &&
((physStartAddr - physOffset) >= memDescribedStartAddr))
((physStartAddr - physOffset) >= memDescribedStartAddr) &&
((vaAddr - alignedVA) == 0 || (vaAddr - alignedVA) == physOffset))
{
vaMaxPageSize = pageSize;
bFoundPageSize = NV_TRUE;
src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_pwr_mgmt.c
+1 -1
View File
@@ -370,7 +370,7 @@ _memmgrAllocFbsrReservedRanges
sizeof(compbitStoreInfoParams)),
fail);
size += compbitStoreInfoParams.Size;
size += compbitStoreInfoParams.cbcRegionSize;
}
// Allocate the System memory
src/nvidia/src/kernel/gpu/mem_mgr/sem_surf.c
+10
View File
@@ -1727,6 +1727,11 @@ semsurfCtrlCmdRegisterWaiter_IMPL
notificationHandle,
bKernel);
if (rmStatus != NV_OK && !bKernel && notificationHandle != 0)
{
osDereferenceObjectCount(NvP64_VALUE(notificationHandle));
}
return rmStatus;
}
@@ -1877,6 +1882,11 @@ semsurfCtrlCmdUnregisterWaiter_IMPL
notificationHandle,
bKernel);
if (!bKernel && notificationHandle != 0)
{
osDereferenceObjectCount(NvP64_VALUE(notificationHandle));
}
return rmStatus;
}
src/nvidia/src/kernel/gpu/mig_mgr/arch/hopper/kmigmgr_gh100.c
+9 -2
View File
@@ -128,6 +128,7 @@ kmigmgrApplyMIGGpuInstanceCeMapping_GH100
NvU32 *pLocalPceLceMap = NULL;
NvU32 lceAvailableMask = 0;
NvU32 i;
NV_STATUS status = NV_OK;
RM_ENGINE_TYPE ceEngineType;
ENGTYPE_BIT_VECTOR ceEngines;
@@ -154,16 +155,22 @@ kmigmgrApplyMIGGpuInstanceCeMapping_GH100
{
pLocalPceLceMap[i] = NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_INVALID_LCE;
}
kceGetMappingsForMIGGpuInstance_HAL(pGpu, pKCe, lceAvailableMask, pLocalPceLceMap);
NV_CHECK_OK_OR_ELSE(status,
LEVEL_ERROR,
kceGetMappingsForMIGGpuInstance_HAL(pGpu, pKCe, lceAvailableMask, pLocalPceLceMap),
goto cleanup;);
if (!kceApplyMIGMappings(pGpu, pKCe, pLocalPceLceMap, lceAvailableMask))
{
NV_PRINTF(LEVEL_ERROR, "Failed to apply MIG Mappings on LCE mask 0x%x\n", lceAvailableMask);
status = NV_ERR_INVALID_STATE;
goto cleanup;
}
KCE_ITER_END;
cleanup:
portMemFree(pLocalPceLceMap);
return NV_OK;
return status;
}
/*!
src/nvidia/src/kernel/gpu/mig_mgr/gpu_instance_subscription.c
+8
View File
@@ -449,6 +449,14 @@ gisubscriptionCtrlCmdExecPartitionsCreate_IMPL
// Only continue if execution partition creation succeeded in the host
NV_ASSERT_OK_OR_RETURN(status);
// Validate execPartId values returned by RPC before using as array indices
for (i = 0; i < pParams->execPartCount; i++)
{
NV_CHECK_OR_RETURN(LEVEL_ERROR,
pParams->execPartId[i] < KMIGMGR_MAX_COMPUTE_INSTANCES,
NV_ERR_INVALID_DATA);
}
}
if (!IS_GSP_CLIENT(pGpu))
src/nvidia/src/kernel/gpu/mig_mgr/kernel_mig_manager.c
+35 -4
View File
@@ -3299,6 +3299,22 @@ kmigmgrPrintGPUInstanceInfo_IMPL
RM_ENGINE_TYPE_GR(0));
NvU32 ceCount = kmigmgrCountEnginesInRange(&pKernelMIGGpuInstance->resourceAllocation.engines,
kmigmgrGetAsyncCERange_HAL(pGpu, pKernelMIGManager));
// update CE count to what is actually mapped versus total CEs available
KernelCE *pKCe = NULL;
NvU32 unused;
NvU32 ceMappedCount;
kceFindFirstInstance(pGpu, &pKCe);
if (pKCe != NULL)
{
kceGetPceConfigForLceMIGGpuInstance(pGpu, pKCe, 0, ceCount, &unused, &ceMappedCount, &unused, &unused);
if (ceMappedCount != 0)
{
ceCount = ceMappedCount;
}
}
NvU32 decCount = kmigmgrCountEnginesOfType(&pKernelMIGGpuInstance->resourceAllocation.engines,
RM_ENGINE_TYPE_NVDEC(0));
NvU32 encCount = kmigmgrCountEnginesOfType(&pKernelMIGGpuInstance->resourceAllocation.engines,
@@ -5933,11 +5949,14 @@ kmigmgrConfigureGPUInstance_IMPL
//
// Return an error if there are any channels on any engines targeted by this
// request
// request. Skip this check for GSP fast unload codepath, since we may have channels on engines
// but with no active workloads.
//
NV_CHECK_OR_RETURN(LEVEL_SILENT,
!kfifoEngineListHasChannel(pGpu, pKernelFifo, checkGrs, checkGrCount),
NV_ERR_STATE_IN_USE);
{
NV_CHECK_OR_RETURN(LEVEL_SILENT,
!kfifoEngineListHasChannel(pGpu, pKernelFifo, checkGrs, checkGrCount),
NV_ERR_STATE_IN_USE);
}
if (!bAssigning)
{
@@ -6225,6 +6244,12 @@ kmigmgrInvalidateGPUInstance_IMPL
osRmCapUnregister(&pKernelMIGGpuInstance->pOsRmCaps);
}
if (!IS_VIRTUAL(pGpu))
{
// Clear CE Mappings on this MIG GPU Instance
kmigmgrClearMIGGpuInstanceCeMapping_HAL(pGpu, pKernelMIGManager, pKernelMIGGpuInstance);
}
// Remove GR->GPC mappings in GPU instance Info
FOR_EACH_IN_BITVECTOR(&pKernelMIGGpuInstance->resourceAllocation.engines, rmEngineType)
{
@@ -6942,6 +6967,12 @@ kmigmgrCreateGPUInstance_IMPL
NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_ERROR,
kmigmgrInitGPUInstancePool(pGpu, pKernelMIGManager, pKernelMIGGpuInstance), invalidate);
if (!IS_VIRTUAL(pGpu))
{
// Apply CE Mappings on this partition
kmigmgrApplyMIGGpuInstanceCeMapping_HAL(pGpu, pKernelMIGManager, pKernelMIGGpuInstance);
}
// Init gpu instance scrubber
NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_ERROR,
kmigmgrInitGPUInstanceScrubber(pGpu, pKernelMIGManager, pKernelMIGGpuInstance), invalidate);
src/nvidia/src/kernel/gpu/nvenc/nvencsession.c
+17
View File
@@ -118,6 +118,21 @@ nvencsessionConstruct_IMPL
pNvencSession->pMemory = NULL;
return status;
}
// Free the session before the stats Memory so pMemory remains valid while unmapping.
status = refAddDependant(RES_GET_REF(pNvencSession->pMemory),
RES_GET_REF(pNvencSession));
if (status != NV_OK)
{
memdescUnmap(pNvencSession->pMemory->pMemDesc,
NV_TRUE,
pNvencSession->pSessionStatsBuffer,
pNvencSession->pPriv);
pNvencSession->pMemory = NULL;
pNvencSession->pSessionStatsBuffer = NvP64_NULL;
pNvencSession->pPriv = NvP64_NULL;
return status;
}
}
else
{
@@ -199,6 +214,8 @@ nvencsessionDestruct_IMPL
NV_TRUE,
pNvencSession->pSessionStatsBuffer,
pNvencSession->pPriv);
refRemoveDependant(RES_GET_REF(pNvencSession->pMemory),
RES_GET_REF(pNvencSession));
}
if (IS_VIRTUAL(pGpu))
src/nvidia/src/kernel/gpu/nvenc/nvencsessionctrl.c
+1 -1
View File
@@ -109,7 +109,7 @@ _nvencsessionCtrlCmdNvencSwSessionUpdateInfo
rpcParams.timestampBufferSize = 0;
NV_RM_RPC_CONTROL(pGpu, pRmCtrlParams->hClient, pRmCtrlParams->hObject, pRmCtrlParams->cmd,
&rpcParams, pRmCtrlParams->paramsSize, status);
&rpcParams, sizeof(rpcParams), status);
}
}
else if (pNvencSession->version == NVA0BC_ALLOC_PARAMS_VER_1)
src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_event_kernel.c
+6
View File
@@ -182,6 +182,12 @@ subdeviceCtrlCmdEventSetMemoryNotifies_IMPL
NV_CHECK_OK_OR_RETURN(LEVEL_SILENT,
memGetByHandle(pClient, pSetMemoryNotifiesParams->hMemory, &pMemory));
if (pMemory->pDevice != pSubdevice->pDevice)
{
NV_PRINTF(LEVEL_INFO, "subdeviceCtrlCmdEventSetMemoryNotifies: rejecting memory not associated with this device\n");
return NV_ERR_INVALID_ARGUMENT;
}
if (pMemory->pMemDesc->Size < sizeof(NvNotification) * NV2080_NOTIFIERS_MAXCOUNT)
{
return NV_ERR_INVALID_LIMIT;
src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_nvd.c
+4 -1
View File
@@ -220,6 +220,7 @@ subdeviceCtrlCmdNvdGetNocatJournalRpt_IMPL
return status;
}
/*!
* @brief Set the NOCAT TDR data collected by KMD in the NOCAT journal record
*
@@ -303,6 +304,9 @@ subdeviceCtrlCmdNvdInsertNocatJournalRecord_IMPL
portMemSet(&newEntry, 0, sizeof(newEntry));
pRecordParams->nocatJournalRecord.source[sizeof(pRecordParams->nocatJournalRecord.source) - 1] = '\0';
pRecordParams->nocatJournalRecord.faultingEngine[sizeof(pRecordParams->nocatJournalRecord.faultingEngine) - 1] = '\0';
// fill in the newEntry structure with the data from the insertData.
newEntry.timestamp = pRecordParams->nocatJournalRecord.timestamp;
newEntry.recType = pRecordParams->nocatJournalRecord.recType;
@@ -320,4 +324,3 @@ subdeviceCtrlCmdNvdInsertNocatJournalRecord_IMPL
return NV_OK;
}
src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c
+4
View File
@@ -4353,6 +4353,8 @@ gpumgrCacheCreateComputeInstance_IMPL(OBJGPU *pGpu, NvU32 swizzId, NvU32 ciId)
NV_ASSERT_OR_GOTO(pGpuInstances != NULL, done);
NV_ASSERT_OR_GOTO(ciId < GPUMGR_MAX_COMPUTE_INSTANCES, done);
for (i = 0; i < GPUMGR_MAX_GPU_INSTANCES; i++)
{
if (pGpuInstances[i].bValid &&
@@ -4390,6 +4392,8 @@ gpumgrCacheDestroyComputeInstance_IMPL(OBJGPU *pGpu, NvU32 swizzId, NvU32 ciId)
NV_ASSERT_OR_GOTO(pGpuInstances != NULL, done);
NV_ASSERT_OR_GOTO(ciId < GPUMGR_MAX_COMPUTE_INSTANCES, done);
for (i = 0; i < GPUMGR_MAX_GPU_INSTANCES; i++)
{
if (pGpuInstances[i].bValid &&
src/nvidia/src/kernel/mem_mgr/gpu_vaspace.c
+5 -1
View File
@@ -4296,7 +4296,11 @@ gvaspaceCopyServerReservedPdes_IMPL
aperture = ADDR_SYSMEM;
break;
default:
NV_ASSERT_OR_GOTO(0, done);
NV_ASSERT(0);
NV_PRINTF(LEVEL_ERROR, "Unknown aperture: level %d aperture=%u\n",
i, pCopyServerReservedPdesParams->levels[i].aperture);
status = NV_ERR_INVALID_ARGUMENT;
goto done;
}
status = memdescCreate(&pMemDescNew, pGpu,
src/nvidia/src/kernel/mem_mgr/os_desc_mem.c
+31 -1
View File
@@ -71,6 +71,20 @@ osdescConstruct_IMPL
limit = pUserParams->limit;
//
// Keep OS descriptor imports consistent with the legacy NVOS02 path:
// CPU read-only backing memory must also be read-only to the GPU.
//
if (FLD_TEST_DRF(OS32, _ATTR2, _PROTECTION_USER, _READ_ONLY,
pUserParams->attr2) ||
(pUserParams->flags & NVOS32_ALLOC_FLAGS_USER_READ_ONLY))
{
pUserParams->attr2 =
FLD_SET_DRF(OS32, _ATTR2, _PROTECTION_DEVICE, _READ_ONLY,
pUserParams->attr2);
pUserParams->flags |= NVOS32_ALLOC_FLAGS_DEVICE_READ_ONLY;
}
//
// Bug 860684: osCreateMemFromOsDescriptor expects OS02 flags
// from the old NvRmAllocMemory64() interface so we need to
@@ -91,6 +105,16 @@ osdescConstruct_IMPL
}
}
//
// OS_PAGE_ARRAY must come from the Unix escape layer after user pages are
// pinned and the descriptor pointer has been replaced with a kernel pointer.
//
if ((pUserParams->descriptorType == NVOS32_DESCRIPTOR_TYPE_OS_PAGE_ARRAY) &&
(pCallContext->secInfo.paramLocation != PARAM_LOCATION_KERNEL))
{
return NV_ERR_NOT_SUPPORTED;
}
if (pUserParams->descriptorType == NVOS32_DESCRIPTOR_TYPE_OS_IO_MEMORY)
{
//
@@ -128,6 +152,13 @@ osdescConstruct_IMPL
pUserParams->descriptorType,
pRmAllocParams->pSecInfo->privLevel));
if ((pUserParams->descriptorType == NVOS32_DESCRIPTOR_TYPE_OS_PAGE_ARRAY) ||
(pUserParams->descriptorType == NVOS32_DESCRIPTOR_TYPE_OS_IO_MEMORY))
{
// The memdesc cleanup path now owns this import backing.
pUserParams->descriptor = NvP64_NULL;
}
if (!memdescGetContiguity(pMemDesc, AT_PA))
{
os02Flags = FLD_SET_DRF(OS02, _FLAGS, _PHYSICALITY, _NONCONTIGUOUS, os02Flags);
@@ -280,4 +311,3 @@ osdescCanCopy_IMPL
// In case of MODS the caller is responsible for not freeing the memory.
return (RMCFG_FEATURE_PLATFORM_UNIX || RMCFG_FEATURE_PLATFORM_MODS);
}
src/nvidia/src/kernel/mem_mgr/video_mem.c
+16 -10
View File
@@ -461,10 +461,18 @@ vidmemCopyConstruct
)
{
Memory *pMemorySrc = dynamicCast(pParams->pSrcRef->pResource, Memory);
OBJGPU *pGpu = pMemorySrc->pGpu;
OBJGPU *pGpu = pMemorySrc->pMemDesc->pGpu;
MEMORY_DESCRIPTOR *pMemDesc = pMemorySrc->pMemDesc;
NV_STATUS status = NV_ERR_INVALID_ARGUMENT;
KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu);
NvBool bSrcLockAcquired = NV_FALSE;
if (!rmDeviceGpuLockIsOwner(pGpu->gpuInstance) && !rmGpuLockIsOwner())
{
NV_ASSERT_OK_OR_RETURN(rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_MEM));
bSrcLockAcquired = NV_TRUE;
}
// No flags specified on the initial static BAR1 mapping
status = kbusIncreaseStaticBar1Refcount_HAL(pGpu, pKernelBus,
@@ -510,6 +518,12 @@ vidmemCopyConstruct
memacctIncrementChargeRefCount(pMemory->pCharge);
}
if (bSrcLockAcquired)
{
// UNLOCK: release GPUs lock
rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL);
}
return status;
}
@@ -585,15 +599,7 @@ vidmemConstruct_IMPL
if (RS_IS_COPY_CTOR(pParams))
{
if (!rmDeviceGpuLockIsOwner(pGpu->gpuInstance) && !rmGpuLockIsOwner())
{
NV_ASSERT_OK_OR_GOTO(rmStatus,
rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_MEM),
done);
bLockAcquired = NV_TRUE;
}
// No need to lock this GPU
rmStatus = vidmemCopyConstruct(pVideoMemory, pCallContext, pParams);
goto done;
}

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