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Common: Switch g1 and g3 SIMD to auto SSE/AVX

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This commit is contained in:
TellowKrinkle
2025-08-10 00:12:15 -05:00
committed by TellowKrinkle
parent 59125c9b12
commit 08b9037781
4 changed files with 63 additions and 21 deletions
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14
common/emitter/groups.cpp
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@@ -92,12 +92,12 @@ namespace x86Emitter
}
}
const xImpl_G1Logic xAND = {{G1Type_AND}, {0x00, 0x54}, {0x66, 0x54}};
const xImpl_G1Logic xOR = {{G1Type_OR}, {0x00, 0x56}, {0x66, 0x56}};
const xImpl_G1Logic xXOR = {{G1Type_XOR}, {0x00, 0x57}, {0x66, 0x57}};
const xImpl_G1Logic xAND = {{G1Type_AND}, {SIMDInstructionInfo(0x54).commutative()}, {SIMDInstructionInfo(0x54).commutative().p66()}};
const xImpl_G1Logic xOR = {{G1Type_OR}, {SIMDInstructionInfo(0x56).commutative()}, {SIMDInstructionInfo(0x56).commutative().p66()}};
const xImpl_G1Logic xXOR = {{G1Type_XOR}, {SIMDInstructionInfo(0x57).commutative()}, {SIMDInstructionInfo(0x57).commutative().p66()}};
const xImpl_G1Arith xADD = {{G1Type_ADD}, {0x00, 0x58}, {0x66, 0x58}, {0xf3, 0x58}, {0xf2, 0x58}};
const xImpl_G1Arith xSUB = {{G1Type_SUB}, {0x00, 0x5c}, {0x66, 0x5c}, {0xf3, 0x5c}, {0xf2, 0x5c}};
const xImpl_G1Arith xADD = {{G1Type_ADD}, {SIMDInstructionInfo(0x58).commutative()}, {SIMDInstructionInfo(0x58).commutative().p66()}, {SIMDInstructionInfo(0x58).pf3()}, {SIMDInstructionInfo(0x58).pf2()}};
const xImpl_G1Arith xSUB = {{G1Type_SUB}, {SIMDInstructionInfo(0x5c)}, {SIMDInstructionInfo(0x5c).p66()}, {SIMDInstructionInfo(0x5c).pf3()}, {SIMDInstructionInfo(0x5c).pf2()}};
const xImpl_Group1 xADC = {G1Type_ADC};
const xImpl_Group1 xSBB = {G1Type_SBB};
@@ -212,8 +212,8 @@ namespace x86Emitter
const xImpl_Group3 xUMUL = {G3Type_MUL};
const xImpl_Group3 xUDIV = {G3Type_DIV};
const xImpl_iDiv xDIV = {{G3Type_iDIV}, {0x00, 0x5e}, {0x66, 0x5e}, {0xf3, 0x5e}, {0xf2, 0x5e}};
const xImpl_iMul xMUL = {{G3Type_iMUL}, {0x00, 0x59}, {0x66, 0x59}, {0xf3, 0x59}, {0xf2, 0x59}};
const xImpl_iDiv xDIV = {{G3Type_iDIV}, {SIMDInstructionInfo(0x5e)}, {SIMDInstructionInfo(0x5e).p66()}, {SIMDInstructionInfo(0x5e).pf3()}, {SIMDInstructionInfo(0x5e).pf2()}};
const xImpl_iMul xMUL = {{G3Type_iMUL}, {SIMDInstructionInfo(0x59).commutative()}, {SIMDInstructionInfo(0x59).commutative().p66()}, {SIMDInstructionInfo(0x59).pf3()}, {SIMDInstructionInfo(0x59).pf2()}};
// =====================================================================================================
// Group 8 Instructions

12
common/emitter/implement/group1.h
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@@ -39,8 +39,8 @@ namespace x86Emitter
//
struct xImpl_G1Logic : public xImpl_Group1
{
xImplSimd_DestRegSSE PS; // packed single precision
xImplSimd_DestRegSSE PD; // packed double precision
xImplSimd_3Arg PS; // packed single precision
xImplSimd_3Arg PD; // packed double precision
};
// ------------------------------------------------------------------------
@@ -48,10 +48,10 @@ namespace x86Emitter
//
struct xImpl_G1Arith : public xImpl_Group1
{
xImplSimd_DestRegSSE PS; // packed single precision
xImplSimd_DestRegSSE PD; // packed double precision
xImplSimd_DestRegSSE SS; // scalar single precision
xImplSimd_DestRegSSE SD; // scalar double precision
xImplSimd_3Arg PS; // packed single precision
xImplSimd_3Arg PD; // packed double precision
xImplSimd_3Arg SS; // scalar single precision
xImplSimd_3Arg SD; // scalar double precision
};
} // End namespace x86Emitter

16
common/emitter/implement/group3.h
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@@ -32,10 +32,10 @@ namespace x86Emitter
// --------------------------------------------------------------------------------------
struct xImpl_iDiv : public xImpl_Group3
{
const xImplSimd_DestRegSSE PS;
const xImplSimd_DestRegSSE PD;
const xImplSimd_DestRegSSE SS;
const xImplSimd_DestRegSSE SD;
const xImplSimd_3Arg PS;
const xImplSimd_3Arg PD;
const xImplSimd_3Arg SS;
const xImplSimd_3Arg SD;
};
// --------------------------------------------------------------------------------------
@@ -58,9 +58,9 @@ namespace x86Emitter
void operator()(const xRegister16& to, const xRegister16& from, s16 imm) const;
void operator()(const xRegister16& to, const xIndirectVoid& from, s16 imm) const;
const xImplSimd_DestRegSSE PS;
const xImplSimd_DestRegSSE PD;
const xImplSimd_DestRegSSE SS;
const xImplSimd_DestRegSSE SD;
const xImplSimd_3Arg PS;
const xImplSimd_3Arg PD;
const xImplSimd_3Arg SS;
const xImplSimd_3Arg SD;
};
} // namespace x86Emitter