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Common: Add auto-switching AVX/SSE emitter functions
This commit is contained in:
TellowKrinkle
committed by
TellowKrinkle
TellowKrinkle
parent
5561884126
commit
de022ab68d
@@ -10,6 +10,153 @@ namespace x86Emitter
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// xImpl_SIMD Types (template free!)
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// =====================================================================================================
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struct SIMDInstructionInfo {
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/// The prefix byte of a simd instruction. These match up with their (E)VEX encodings.
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enum class Prefix : u32 {
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None = 0,
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P66 = 1,
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PF3 = 2,
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PF2 = 3,
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};
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/// The opcode map of a simd instruction. These match up with their (E)VEX encodings.
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enum class Map : u32 {
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M0F = 1,
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M0F38 = 2,
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M0F3A = 3,
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};
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/// Whether an operation operates on float (ss, ps), integer (b, w, d, q), or double (sd, pd) data.
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/// May be used to choose an appropriate mov instruction if one is needed.
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enum class Type : u32 {
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Float, Integer, Double
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};
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/// The main opcode
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u32 opcode : 8;
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/// Prefix byte
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Prefix prefix : 2;
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/// Opcode map
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Map map : 5;
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/// Information about the data this operation operates on. Ignored for instructions where the SSE4 and AVX versions have the same number of arguments.
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Type type : 2;
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/// For instructions like pslld, the data that should go into the reg field in place of the first src
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u32 ext : 3;
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/// If true, the two inputs to the function can be swapped without changing its result.
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u32 is_commutative : 1;
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/// If true, the dst and src1 must be the same in AVX (e.g. mov instructions, pshufd)
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u32 is_mov : 1;
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/// If true, get `W` from dst register instead of `w_bit`
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u32 dst_w : 1;
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/// If true, get `W` from src register instead of `w_bit`
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u32 src_w : 1;
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/// If true, the instruction has the VEX W bit set
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u32 w_bit : 1;
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constexpr SIMDInstructionInfo(u8 opcode_, u8 ext_ = 0)
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: opcode(opcode_), prefix(Prefix::None), map(Map::M0F), type(Type::Float), ext(ext_)
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, is_commutative(false), is_mov(false), dst_w(false), src_w(false), w_bit(false)
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{
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}
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// For configuration using in a builder-style
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constexpr SIMDInstructionInfo p66() const { SIMDInstructionInfo copy = *this; copy.prefix = Prefix::P66; return copy; }
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constexpr SIMDInstructionInfo pf3() const { SIMDInstructionInfo copy = *this; copy.prefix = Prefix::PF3; return copy; }
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constexpr SIMDInstructionInfo pf2() const { SIMDInstructionInfo copy = *this; copy.prefix = Prefix::PF2; return copy; }
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constexpr SIMDInstructionInfo m0f38() const { SIMDInstructionInfo copy = *this; copy.map = Map::M0F38; return copy; }
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constexpr SIMDInstructionInfo m0f3a() const { SIMDInstructionInfo copy = *this; copy.map = Map::M0F3A; return copy; }
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constexpr SIMDInstructionInfo f() const { SIMDInstructionInfo copy = *this; copy.type = Type::Float; return copy; }
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constexpr SIMDInstructionInfo i() const { SIMDInstructionInfo copy = *this; copy.type = Type::Integer; return copy; }
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constexpr SIMDInstructionInfo d() const { SIMDInstructionInfo copy = *this; copy.type = Type::Double; return copy; }
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constexpr SIMDInstructionInfo w() const { SIMDInstructionInfo copy = *this; copy.w_bit = true; return copy; }
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constexpr SIMDInstructionInfo dstw() const { SIMDInstructionInfo copy = *this; copy.dst_w = true; return copy; }
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constexpr SIMDInstructionInfo srcw() const { SIMDInstructionInfo copy = *this; copy.src_w = true; return copy; }
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constexpr SIMDInstructionInfo commutative() const { SIMDInstructionInfo copy = *this; copy.is_commutative = true; return copy; }
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constexpr SIMDInstructionInfo mov() const { SIMDInstructionInfo copy = *this; copy.is_mov = true; return copy; }
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};
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// ------------------------------------------------------------------------
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// For implementing SSE/AVX logic operations that have two arguments in both SSE and AVX
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// like MOVAPS, CVTPS2DQ, etc
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//
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struct xImplSimd_2Arg
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{
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SIMDInstructionInfo info;
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constexpr xImplSimd_2Arg(SIMDInstructionInfo info_): info(info_.mov()) {}
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void operator()(const xRegisterSSE& dst, const xRegisterSSE& src) const;
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void operator()(const xRegisterSSE& dst, const xIndirectVoid& src) const;
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};
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// ------------------------------------------------------------------------
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// For implementing SSE/AVX logic operations that have two arguments in both SSE and AVX, plus an immediate
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// like PSHUFD
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//
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struct xImplSimd_2ArgImm
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{
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SIMDInstructionInfo info;
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constexpr xImplSimd_2ArgImm(SIMDInstructionInfo info_): info(info_.mov()) {}
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void operator()(const xRegisterSSE& dst, const xRegisterSSE& src, u8 imm) const;
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void operator()(const xRegisterSSE& dst, const xIndirectVoid& src, u8 imm) const;
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};
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// ------------------------------------------------------------------------
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// For implementing SSE/AVX logic operations that have three arguments AVX and two in SSE
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// like ANDPS, ANDPD, etc
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//
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struct xImplSimd_3Arg
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{
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SIMDInstructionInfo info;
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void operator()(const xRegisterSSE& dst, const xRegisterSSE& src) const { (*this)(dst, dst, src); }
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void operator()(const xRegisterSSE& dst, const xIndirectVoid& src) const { (*this)(dst, dst, src); }
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void operator()(const xRegisterSSE& dst, const xRegisterSSE& src1, const xRegisterSSE& src2) const;
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void operator()(const xRegisterSSE& dst, const xRegisterSSE& src1, const xIndirectVoid& src2) const;
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};
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// ------------------------------------------------------------------------
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// For implementing SSE/AVX logic operations that have three arguments AVX and two in SSE
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// like SHUFPS, INSERTPS, etc
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//
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struct xImplSimd_3ArgImm
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{
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SIMDInstructionInfo info;
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void operator()(const xRegisterSSE& dst, const xRegisterSSE& src, u8 imm) const { (*this)(dst, dst, src, imm); }
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void operator()(const xRegisterSSE& dst, const xIndirectVoid& src, u8 imm) const { (*this)(dst, dst, src, imm); }
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void operator()(const xRegisterSSE& dst, const xRegisterSSE& src1, const xRegisterSSE& src2, u8 imm) const;
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void operator()(const xRegisterSSE& dst, const xRegisterSSE& src1, const xIndirectVoid& src2, u8 imm) const;
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};
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// ------------------------------------------------------------------------
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// For implementing SSE/AVX logic operations that have three arguments AVX and two in SSE
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// like SHUFPS, INSERTPS, etc
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//
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struct xImplSimd_3ArgCmp
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{
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SIMDInstructionInfo info;
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void operator()(const xRegisterSSE& dst, const xRegisterSSE& src, SSE2_ComparisonType imm) const { (*this)(dst, dst, src, imm); }
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void operator()(const xRegisterSSE& dst, const xIndirectVoid& src, SSE2_ComparisonType imm) const { (*this)(dst, dst, src, imm); }
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void operator()(const xRegisterSSE& dst, const xRegisterSSE& src1, const xRegisterSSE& src2, SSE2_ComparisonType imm) const;
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void operator()(const xRegisterSSE& dst, const xRegisterSSE& src1, const xIndirectVoid& src2, SSE2_ComparisonType imm) const;
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};
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// ------------------------------------------------------------------------
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// For implementing SSE/AVX logic operations that have four arguments AVX and two in SSE (with an implicit xmm0)
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// like PBLENDVB, BLENDVPS, etc
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//
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struct xImplSimd_4ArgBlend
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{
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SIMDInstructionInfo info;
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void operator()(const xRegisterSSE& dst, const xRegisterSSE& src) const { (*this)(dst, dst, src, xmm0); }
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void operator()(const xRegisterSSE& dst, const xIndirectVoid& src) const { (*this)(dst, dst, src, xmm0); }
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void operator()(const xRegisterSSE& dst, const xRegisterSSE& src1, const xRegisterSSE& src2, const xRegisterSSE& src3) const;
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void operator()(const xRegisterSSE& dst, const xRegisterSSE& src1, const xIndirectVoid& src2, const xRegisterSSE& src3) const;
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};
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// ------------------------------------------------------------------------
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// For implementing SSE-only logic operations that have xmmreg,xmmreg/rm forms only,
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// like ANDPS/ANDPD
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@@ -10,6 +10,7 @@ namespace x86Emitter
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{
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#define OpWriteSSE(pre, op) xOpWrite0F(pre, op, to, from)
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#define OpWriteSIMDMovOp(op) EmitSIMD(op.mov(), to, to, from)
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extern void SimdPrefix(u8 prefix, u16 opcode);
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extern void EmitSibMagic(uint regfield, const void* address, int extraRIPOffset = 0);
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@@ -25,6 +26,9 @@ namespace x86Emitter
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extern void EmitRex(const xRegisterBase& reg1, const xRegisterBase& reg2);
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extern void EmitRex(const xRegisterBase& reg1, const void* src);
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extern void EmitRex(const xRegisterBase& reg1, const xIndirectVoid& sib);
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extern void EmitRex(SIMDInstructionInfo info, u32 reg1, const xRegisterBase& reg2);
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extern void EmitRex(SIMDInstructionInfo info, const xRegisterBase& reg1, const xRegisterBase& reg2);
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extern void EmitRex(SIMDInstructionInfo info, const xRegisterBase& reg1, const xIndirectVoid& sib);
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extern void _xMovRtoR(const xRegisterInt& to, const xRegisterInt& from);
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@@ -171,4 +175,44 @@ namespace x86Emitter
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xWrite8(opcode);
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EmitSibMagic(param1, param3);
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}
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void EmitVEX(SIMDInstructionInfo info, const xRegisterBase& dst, u8 src1, const xRegisterBase& src2, int extraRipOffset = 0);
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void EmitVEX(SIMDInstructionInfo info, const xRegisterBase& dst, u8 src1, const xIndirectVoid& src2, int extraRipOffset = 0);
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void EmitVEX(SIMDInstructionInfo info, u32 ext, u8 dst, const xRegisterBase& src2, int extraRipOffset = 0);
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template <typename S2>
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__emitinline static void EmitVEX(SIMDInstructionInfo info, const xRegisterBase& dst, const xRegisterBase& src1, const S2& src2, int extraRipOffset = 0)
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{
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EmitVEX(info, dst, src1.GetId(), src2, extraRipOffset);
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}
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// Emitter helpers for SIMD operations
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// These will dispatch to either SSE or AVX implementations
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void EmitSIMDImpl(SIMDInstructionInfo info, const xRegisterBase& dst, const xRegisterBase& src1, int extraRipOffset);
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void EmitSIMDImpl(SIMDInstructionInfo info, const xRegisterBase& dst, const xRegisterBase& src1, const xRegisterBase& src2, int extraRipOffset);
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void EmitSIMDImpl(SIMDInstructionInfo info, const xRegisterBase& dst, const xRegisterBase& src1, const xIndirectVoid& src2, int extraRipOffset);
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void EmitSIMD(SIMDInstructionInfo info, const xRegisterBase& dst, const xRegisterBase& src1, const xRegisterBase& src2, const xRegisterBase& src3);
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void EmitSIMD(SIMDInstructionInfo info, const xRegisterBase& dst, const xRegisterBase& src1, const xIndirectVoid& src2, const xRegisterBase& src3);
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__emitinline static void EmitSIMD(SIMDInstructionInfo info, const xRegisterBase& dst, const xRegisterBase& src1)
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{
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EmitSIMDImpl(info, dst, src1, 0);
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}
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__emitinline static void EmitSIMD(SIMDInstructionInfo info, const xRegisterBase& dst, const xRegisterBase& src1, u8 imm)
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{
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EmitSIMDImpl(info, dst, src1, 1);
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xWrite8(imm);
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}
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template <typename S2>
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__emitinline static void EmitSIMD(SIMDInstructionInfo info, const xRegisterBase& dst, const xRegisterBase& src1, const S2& src2)
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{
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EmitSIMDImpl(info, dst, src1, src2, 0);
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}
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template <typename S2>
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__emitinline static void EmitSIMD(SIMDInstructionInfo info, const xRegisterBase& dst, const xRegisterBase& src1, const S2& src2, u8 imm)
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{
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EmitSIMDImpl(info, dst, src1, src2, 1);
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xWrite8(imm);
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}
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} // namespace x86Emitter
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@@ -6,6 +6,171 @@
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namespace x86Emitter
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{
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__emitinline static u8 getSSE(SIMDInstructionInfo::Prefix prefix)
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{
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switch (prefix) {
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case SIMDInstructionInfo::Prefix::P66: return 0x66;
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case SIMDInstructionInfo::Prefix::PF3: return 0xf3;
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case SIMDInstructionInfo::Prefix::PF2: return 0xf2;
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case SIMDInstructionInfo::Prefix::None:
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default:
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pxAssert(0);
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return 0;
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}
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}
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__emitinline static u16 getSSE(SIMDInstructionInfo::Map map)
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{
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switch (map) {
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case SIMDInstructionInfo::Map::M0F38: return 0x380f;
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case SIMDInstructionInfo::Map::M0F3A: return 0x3a0f;
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case SIMDInstructionInfo::Map::M0F:
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default:
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pxAssert(0);
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return 0;
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}
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}
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__emitinline static SIMDInstructionInfo getMov(SIMDInstructionInfo::Type type)
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{
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switch (type) {
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#ifndef ALWAYS_USE_MOVAPS
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case SIMDInstructionInfo::Type::Integer:
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return SIMDInstructionInfo(0x6f).p66().mov();
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case SIMDInstructionInfo::Type::Double:
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return SIMDInstructionInfo(0x28).p66().mov();
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#endif
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default:
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case SIMDInstructionInfo::Type::Float:
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return SIMDInstructionInfo(0x28).mov();
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}
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}
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template <typename T1, typename T2>
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__emitinline static void xOpWrite0F(SIMDInstructionInfo info, T1 dst, const T2& src, int extraRIPOffset)
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{
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if (info.prefix != SIMDInstructionInfo::Prefix::None)
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xWrite8(getSSE(info.prefix));
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pxAssert(!info.w_bit); // Only used by AVX
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EmitRex(info, dst, src);
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if (info.map == SIMDInstructionInfo::Map::M0F)
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{
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xWrite16(0x0F | (info.opcode << 8));
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}
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else
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{
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xWrite16(getSSE(info.map));
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xWrite8(info.opcode);
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}
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EmitSibMagic(dst, src, extraRIPOffset);
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}
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template <typename S2>
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__emitinline static void EmitSimdOp(SIMDInstructionInfo info, const xRegisterBase& dst, const xRegisterBase& src1, const S2& src2, int extraRIPOffset)
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{
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if (x86Emitter::use_avx)
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{
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EmitVEX(info, dst, info.is_mov ? 0 : src1.GetId(), src2, extraRIPOffset);
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}
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else
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{
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if (dst.GetId() != src1.GetId())
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{
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pxAssert(!info.is_mov);
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// Generate a mov to copy from src1 to dst
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xOpWrite0F(getMov(info.type), dst, src1, 0);
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}
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xOpWrite0F(info, dst, src2, extraRIPOffset);
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}
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}
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void EmitSIMDImpl(SIMDInstructionInfo info, const xRegisterBase& dst, const xRegisterBase& src1, int extraRipOffset)
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{
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pxAssert(!info.is_mov);
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if (x86Emitter::use_avx)
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{
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EmitVEX(info, info.ext, dst.GetId(), src1, extraRipOffset);
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}
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else
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{
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if (dst.GetId() != src1.GetId())
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{
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// Generate a mov to copy from src1 to dst
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xOpWrite0F(getMov(info.type), dst, src1, 0);
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}
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xOpWrite0F(info, info.ext, dst, extraRipOffset);
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}
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}
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void EmitSIMDImpl(SIMDInstructionInfo info, const xRegisterBase& dst, const xRegisterBase& src1, const xRegisterBase& src2, int extraRipOffset)
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{
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pxAssert(!info.is_mov || dst.GetId() == src1.GetId());
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const xRegisterBase* ps1 = &src1;
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const xRegisterBase* ps2 = &src2;
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if (x86Emitter::use_avx)
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{
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if (info.is_commutative && info.map == SIMDInstructionInfo::Map::M0F && src2.IsExtended() && !src1.IsExtended())
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{
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// We can use a C5 op instead of a C4 op if we swap the inputs
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std::swap(ps1, ps2);
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}
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}
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else if (dst.GetId() != src1.GetId() && dst.GetId() == src2.GetId())
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{
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if (info.is_commutative)
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std::swap(ps1, ps2);
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else
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pxAssertRel(0, "SSE4 auto mov would destroy the second source!");
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}
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EmitSimdOp(info, dst, *ps1, *ps2, extraRipOffset);
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}
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void EmitSIMDImpl(SIMDInstructionInfo info, const xRegisterBase& dst, const xRegisterBase& src1, const xIndirectVoid& src2, int extraRipOffset)
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{
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pxAssert(!info.is_mov || dst.GetId() == src1.GetId());
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if (!x86Emitter::use_avx && info.is_commutative && dst.GetId() != src1.GetId())
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{
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// Do load, op instead of mov, op+load
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// No processors differentiate between loads, so always use movaps
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EmitSimdOp(getMov(SIMDInstructionInfo::Type::Float), dst, dst, src2, 0);
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EmitSimdOp(info, dst, dst, src1, extraRipOffset);
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}
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else
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{
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EmitSimdOp(info, dst, src1, src2, extraRipOffset);
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}
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}
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void EmitSIMD(SIMDInstructionInfo info, const xRegisterBase& dst, const xRegisterBase& src1, const xRegisterBase& src2, const xRegisterBase& src3)
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{
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pxAssert(!info.is_mov);
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pxAssertMsg(!info.is_commutative, "I don't think any blend instructions are commutative...");
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if (x86Emitter::use_avx)
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{
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EmitSimdOp(info, dst, src1, src2, 1);
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xWrite8(src3.GetId());
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}
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else
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{
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pxAssertRel(src3.GetId() == 0, "SSE4 requires the third source to be xmm0!");
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if (dst.GetId() != src1.GetId() && dst.GetId() == src2.GetId())
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pxAssertRel(0, "SSE4 auto mov would destroy the second source!");
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EmitSimdOp(info, dst, src1, src2, 0);
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}
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}
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void EmitSIMD(SIMDInstructionInfo info, const xRegisterBase& dst, const xRegisterBase& src1, const xIndirectVoid& src2, const xRegisterBase& src3)
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{
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pxAssert(!info.is_mov);
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pxAssertMsg(!info.is_commutative, "I don't think any blend instructions are commutative...");
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if (x86Emitter::use_avx)
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{
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EmitSimdOp(info, dst, src1, src2, 1);
|
||||
xWrite8(src3.GetId());
|
||||
}
|
||||
else
|
||||
{
|
||||
pxAssertRel(src3.GetId() == 0, "SSE4 requires the third source to be xmm0!");
|
||||
EmitSimdOp(info, dst, src1, src2, 0);
|
||||
}
|
||||
}
|
||||
|
||||
// ------------------------------------------------------------------------
|
||||
// SimdPrefix - If the lower byte of the opcode is 0x38 or 0x3a, then the opcode is
|
||||
@@ -107,6 +272,19 @@ namespace x86Emitter
|
||||
|
||||
// ------------------------------------------------------------------------
|
||||
|
||||
void xImplSimd_2Arg::operator()(const xRegisterSSE& dst, const xRegisterSSE& src) const { EmitSIMD(info, dst, dst, src); }
|
||||
void xImplSimd_2Arg::operator()(const xRegisterSSE& dst, const xIndirectVoid& src) const { EmitSIMD(info, dst, dst, src); }
|
||||
void xImplSimd_2ArgImm::operator()(const xRegisterSSE& dst, const xRegisterSSE& src, u8 imm) const { EmitSIMD(info, dst, dst, src, imm); }
|
||||
void xImplSimd_2ArgImm::operator()(const xRegisterSSE& dst, const xIndirectVoid& src, u8 imm) const { EmitSIMD(info, dst, dst, src, imm); }
|
||||
void xImplSimd_3Arg::operator()(const xRegisterSSE& dst, const xRegisterSSE& src1, const xRegisterSSE& src2) const { EmitSIMD(info, dst, src1, src2); }
|
||||
void xImplSimd_3Arg::operator()(const xRegisterSSE& dst, const xRegisterSSE& src1, const xIndirectVoid& src2) const { EmitSIMD(info, dst, src1, src2); }
|
||||
void xImplSimd_3ArgImm::operator()(const xRegisterSSE& dst, const xRegisterSSE& src1, const xRegisterSSE& src2, u8 imm) const { EmitSIMD(info, dst, src1, src2, imm); }
|
||||
void xImplSimd_3ArgImm::operator()(const xRegisterSSE& dst, const xRegisterSSE& src1, const xIndirectVoid& src2, u8 imm) const { EmitSIMD(info, dst, src1, src2, imm); }
|
||||
void xImplSimd_3ArgCmp::operator()(const xRegisterSSE& dst, const xRegisterSSE& src1, const xRegisterSSE& src2, SSE2_ComparisonType imm) const { EmitSIMD(info, dst, src1, src2, imm); }
|
||||
void xImplSimd_3ArgCmp::operator()(const xRegisterSSE& dst, const xRegisterSSE& src1, const xIndirectVoid& src2, SSE2_ComparisonType imm) const { EmitSIMD(info, dst, src1, src2, imm); }
|
||||
void xImplSimd_4ArgBlend::operator()(const xRegisterSSE& dst, const xRegisterSSE& src1, const xRegisterSSE& src2, const xRegisterSSE& src3) const { EmitSIMD(info, dst, src1, src2, src3); }
|
||||
void xImplSimd_4ArgBlend::operator()(const xRegisterSSE& dst, const xRegisterSSE& src1, const xIndirectVoid& src2, const xRegisterSSE& src3) const { EmitSIMD(info, dst, src1, src2, src3); }
|
||||
|
||||
void xImplSimd_DestRegSSE::operator()(const xRegisterSSE& to, const xRegisterSSE& from) const { OpWriteSSE(Prefix, Opcode); }
|
||||
void xImplSimd_DestRegSSE::operator()(const xRegisterSSE& to, const xIndirectVoid& from) const { OpWriteSSE(Prefix, Opcode); }
|
||||
|
||||
|
||||
@@ -51,6 +51,8 @@
|
||||
thread_local u8* x86Ptr;
|
||||
thread_local XMMSSEType g_xmmtypes[iREGCNT_XMM] = {XMMT_INT};
|
||||
|
||||
bool x86Emitter::use_avx;
|
||||
|
||||
namespace x86Emitter
|
||||
{
|
||||
|
||||
@@ -502,6 +504,46 @@ const xRegister32
|
||||
EmitRex(w, r, x, b, reg1.IsExtended8Bit());
|
||||
}
|
||||
|
||||
void EmitRex(SIMDInstructionInfo info, const xRegisterBase& reg1, const xRegisterBase& reg2)
|
||||
{
|
||||
bool w = false;
|
||||
if (info.dst_w)
|
||||
w |= reg1.IsWide();
|
||||
if (info.src_w)
|
||||
w |= reg2.IsWide();
|
||||
bool r = reg1.IsExtended();
|
||||
bool x = false;
|
||||
bool b = reg2.IsExtended();
|
||||
EmitRex(w, r, x, b, reg2.IsExtended8Bit());
|
||||
}
|
||||
|
||||
void EmitRex(SIMDInstructionInfo info, const xRegisterBase& reg1, const xIndirectVoid& sib)
|
||||
{
|
||||
bool w = false;
|
||||
if (info.dst_w)
|
||||
w |= reg1.IsWide();
|
||||
if (info.src_w)
|
||||
w |= sib.IsWide();
|
||||
bool r = reg1.IsExtended();
|
||||
bool x = sib.Index.IsExtended();
|
||||
bool b = sib.Base.IsExtended();
|
||||
if (!NeedsSibMagic(sib))
|
||||
{
|
||||
b = x;
|
||||
x = false;
|
||||
}
|
||||
EmitRex(w, r, x, b, reg1.IsExtended8Bit());
|
||||
}
|
||||
|
||||
void EmitRex(SIMDInstructionInfo info, uint reg1, const xRegisterBase& reg2)
|
||||
{
|
||||
bool w = info.src_w ? reg2.IsWide() : false;
|
||||
bool r = false;
|
||||
bool x = false;
|
||||
bool b = reg2.IsExtended();
|
||||
EmitRex(w, r, x, b, reg2.IsExtended8Bit());
|
||||
}
|
||||
|
||||
// For use by instructions that are implicitly wide
|
||||
void EmitRexImplicitlyWide(const xRegisterBase& reg)
|
||||
{
|
||||
@@ -526,6 +568,89 @@ const xRegister32
|
||||
EmitRex(w, r, x, b);
|
||||
}
|
||||
|
||||
__emitinline static u8 GetVEXRXB(u32 ext, const xRegisterBase& src2)
|
||||
{
|
||||
return src2.IsExtended() << 5;
|
||||
}
|
||||
|
||||
__emitinline static u8 GetVEXRXB(const xRegisterBase& dst, const xIndirectVoid& src2)
|
||||
{
|
||||
bool r = dst.IsExtended();
|
||||
bool x = src2.Index.IsExtended();
|
||||
bool b = src2.Base.IsExtended();
|
||||
if (!NeedsSibMagic(src2))
|
||||
{
|
||||
b = x;
|
||||
x = false;
|
||||
}
|
||||
return (r << 7) | (x << 6) | (b << 5);
|
||||
}
|
||||
|
||||
__emitinline static u8 GetVEXRXB(const xRegisterBase& dst, const xRegisterBase& src2)
|
||||
{
|
||||
return (dst.IsExtended() << 7) | (src2.IsExtended() << 5);
|
||||
}
|
||||
|
||||
__emitinline static u8 GetL(const xRegisterBase& arg) { return arg.IsWideSIMD() ? 4 : 0; }
|
||||
__emitinline static u8 GetL(const xIndirectVoid& arg) { return 0; }
|
||||
__emitinline static u8 GetL(u32 ext) { return 0; }
|
||||
|
||||
__emitinline static u8 GetVEXW(const xRegisterBase& arg) { return arg.GetOperandSize() == 8 ? 0x80 : 0; }
|
||||
__emitinline static u8 GetVEXW(const xIndirectVoid& arg) { return arg.GetOperandSize() == 8 ? 0x80 : 0; }
|
||||
__emitinline static u8 GetVEXW(u32 ext) { return 0; }
|
||||
|
||||
template <typename D, typename S2>
|
||||
__emitinline void xOpWriteVEX(SIMDInstructionInfo info, D dst, u8 src1, const S2& src2, int extraRipOffset)
|
||||
{
|
||||
u8 m = static_cast<u8>(info.map);
|
||||
u8 p = static_cast<u8>(info.prefix);
|
||||
u8 w = 0;
|
||||
if (info.src_w || info.dst_w) {
|
||||
if (info.dst_w)
|
||||
w |= GetVEXW(dst);
|
||||
if (info.src_w)
|
||||
w |= GetVEXW(src2);
|
||||
} else {
|
||||
w = info.w_bit << 7;
|
||||
}
|
||||
u8 l = GetL(dst) | GetL(src2); // Needed for 256-bit movemask.
|
||||
u8 rxb = GetVEXRXB(dst, src2);
|
||||
u8 b2 = p | l | (src1 << 3);
|
||||
if (!w && info.map == SIMDInstructionInfo::Map::M0F && !(rxb & 0x7F))
|
||||
{
|
||||
// Can use a C5 VEX
|
||||
u8 b1 = rxb | b2;
|
||||
xWrite8(0xC5);
|
||||
xWrite8(b1 ^ 0xF8);
|
||||
xWrite8(info.opcode);
|
||||
}
|
||||
else
|
||||
{
|
||||
u8 b1 = rxb | m;
|
||||
b2 |= w;
|
||||
xWrite8(0xC4);
|
||||
xWrite8(b1 ^ 0xE0);
|
||||
xWrite8(b2 ^ 0x78);
|
||||
xWrite8(info.opcode);
|
||||
}
|
||||
EmitSibMagic(dst, src2, extraRipOffset);
|
||||
}
|
||||
|
||||
void EmitVEX(SIMDInstructionInfo info, const xRegisterBase& dst, u8 src1, const xRegisterBase& src2, int extraRipOffset)
|
||||
{
|
||||
xOpWriteVEX(info, dst, src1, src2, extraRipOffset);
|
||||
}
|
||||
|
||||
void EmitVEX(SIMDInstructionInfo info, const xRegisterBase& dst, u8 src1, const xIndirectVoid& src2, int extraRipOffset)
|
||||
{
|
||||
xOpWriteVEX(info, dst, src1, src2, extraRipOffset);
|
||||
}
|
||||
|
||||
void EmitVEX(SIMDInstructionInfo info, u32 ext, u8 dst, const xRegisterBase& src2, int extraRipOffset)
|
||||
{
|
||||
xOpWriteVEX(info, ext, dst, src2, extraRipOffset);
|
||||
}
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------------------
|
||||
// xSetPtr / xAlignPtr / xGetPtr / xAdvancePtr
|
||||
|
||||
@@ -29,6 +29,9 @@ namespace x86Emitter
|
||||
static constexpr int SHADOW_STACK_SIZE = 0;
|
||||
#endif
|
||||
|
||||
/// This will switch all SSE instructions to generate AVX instructions instead
|
||||
extern bool use_avx;
|
||||
|
||||
extern void xWrite8(u8 val);
|
||||
extern void xWrite16(u16 val);
|
||||
extern void xWrite32(u32 val);
|
||||
@@ -1075,4 +1078,4 @@ extern const xRegister32
|
||||
#include "implement/jmpcall.h"
|
||||
|
||||
#include "implement/bmi.h"
|
||||
#include "implement/avx.h"
|
||||
#include "implement/avx.h"
|
||||
|
||||
@@ -52,6 +52,7 @@
|
||||
#include "common/StringUtil.h"
|
||||
#include "common/Threading.h"
|
||||
#include "common/Timer.h"
|
||||
#include "common/emitter/x86emitter.h"
|
||||
|
||||
#include "IconsFontAwesome6.h"
|
||||
#include "IconsPromptFont.h"
|
||||
@@ -391,6 +392,10 @@ bool VMManager::Internal::CPUThreadInitialize()
|
||||
if (!cpuinfo_initialize())
|
||||
Console.Error("cpuinfo_initialize() failed.");
|
||||
|
||||
#ifdef _M_X86
|
||||
x86Emitter::use_avx = g_cpu.vectorISA >= ProcessorFeatures::VectorISA::AVX;
|
||||
#endif
|
||||
|
||||
LogCPUCapabilities();
|
||||
|
||||
if (!SysMemory::Allocate())
|
||||
|
||||
Reference in New Issue
Block a user