59 Commits

Author SHA1 Message Date
SternXD
d983b2b066 Copyright: Change year from 2002-2025 to 2002-2026 2026-01-15 00:22:32 +01:00
Ziemas
37f28e95b6 Core: Calculate EE/IOPmemSize based on structs 2025-09-11 12:45:12 +02:00
Ziemas
1870193615 Core: Fix EEmemSize
It's got desynced from the actual size of the EEVM_MemoryAllocMess
struct at some point.
2025-09-11 12:45:12 +02:00
TheTechnician27
23fd57f641 Copyright: Change year from 2002-2024 to 2002-2025 2025-01-20 05:07:26 +01:00
GovanifY
132431b7c8 headers: relicense to GPL-3.0+
also update to 2024 while i'm at it
2024-07-30 17:17:13 -04:00
Benjamin Moir
c6cd6b5eb3 Misc: Remove unused ps macros from Memory.h
The psHu64, psHu128 and psSu64 macros are also unused, but are kept for completeness.
2024-05-09 13:45:06 +10:00
Benjamin Moir
5f7e97c27c [SAVEVERSION+] EE: Expose advanced option for extra memory 2024-05-09 13:45:06 +10:00
Stenzek
fb15893521 VMManager: Remove and merge System.cpp 2023-12-27 13:55:35 +10:00
Stenzek
0bc9c7ffa1 Common: Replace x86_intrin.h with generic Intrin.h
For later Apple Silicon support.
2023-12-24 14:03:14 +10:00
Stenzek
d9abe10308 Misc: Remove explicit PCH include, switch to SPDX 2023-12-24 14:03:14 +10:00
refractionpcsx2
7bf18a4464 DEV9: Implement a slightly less hacky (incomplete) DVE reg set 2023-12-19 15:14:35 +00:00
Stenzek
606cbb3883 System: Simplify memory allocation 2023-10-10 18:01:30 +10:00
Stenzek
4cf041f6cb Common: Move VirtualMemory related functionality to core
Also rewrites page fault handling to not use EventSource junk.
2023-01-26 11:11:36 +00:00
Florin9doi
8fbb1e5565 BIOS: Map the entire ROM1 file to PS2 memory
EROM is part of ROM1, its exact location vary and can't be predicted
2022-10-18 10:04:52 +01:00
Connor McLaughlin
00bcb4cf02 System: Revamp memory allocation
Guest memory is now mapped into a shared memory/file mapping, for use
with fastmem.

64-bit and 128-bit arguments are passed by register/value instead of by
reference/address.

LDL/LDR/SDL/SDR now use 64-bit GPRs instead of SSE.
2022-10-14 22:24:42 +01:00
TellowKrinkle
e9518f78c7 vtlb: Switch read64 and read128 handlers to return in sse regs 2021-09-21 22:57:41 +01:00
kojin
8fdaaa2eab common: reorganize 2021-09-04 18:28:07 -04:00
kozarovv
6794bbbd6a Add rom2: support (Fix Chinese Bios) (#3439)
* Add rom2 support

* Add rom2 support on IOP

* Valid memory range for rom2

* Add rom2 support to IopMem.cpp
2020-08-08 20:59:46 +01:00
Gregory Hainaut
a6eb871b42 pcsx2: use a common general intrin include
Avoid issue with various compiler conversion
Fix build with GCC4.8
2016-01-11 09:13:52 +01:00
Gregory Hainaut
e4f407ae7c ee: use enum for mmap_GetRamPageInfo returned value 2015-11-12 10:35:10 +01:00
Ryan Houdek
3d37a6ce27 Removes the usage of __LINUX__ define
This is defined and set it a ton of different places.
It's checked in a whole lot more
Instead just use __linux__ like a real project should
2014-08-03 13:20:36 -05:00
refraction
dde94adec3 Cache Emulation: Updated cache emulation for new VTLB, Dead or Alive 2 (Japanese Version only) now playable. You can enable this under the Recompiler options by ticking the "Enable EE Cache" box, however it will only work with the EE in Interpreter mode. Also fixed some cache bugs from the old implementation.
Note: Once DoA2 is ingame (start of fight), you can switch to the EE Rec until the fight is over with good speed! Hopefully one day someone will be brave enough to implement it on the rec side so you dont have to mess about :P

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@4309 96395faa-99c1-11dd-bbfe-3dabce05a288
2011-02-17 21:27:24 +00:00
Jake.Stine
be1a590464 newHostVM: (WIP, may not run!) -- Applied host virtual memory mapping to the EE/IOP/VU main and on-chip memory banks. Added a new OO-based system allocator object for handling said virtual memory resources. Plus many code cleanups, and some added mess that needs to be cleaned up.
git-svn-id: http://pcsx2.googlecode.com/svn/branches/newHostVM@4020 96395faa-99c1-11dd-bbfe-3dabce05a288
2010-11-15 14:05:02 +00:00
Jake.Stine
01541f2c92 newHostVM branch: work-in-progress stuff...
git-svn-id: http://pcsx2.googlecode.com/svn/branches/newHostVM@3958 96395faa-99c1-11dd-bbfe-3dabce05a288
2010-10-22 16:23:52 +00:00
Jake.Stine
02b390b0e1 Changed SIF and IPU macros for hw register mappings into references. (-> into .)
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3727 96395faa-99c1-11dd-bbfe-3dabce05a288
2010-09-05 02:51:36 +00:00
Jake.Stine
0bb377511b Uninitialized variable fix in ScopedLock as found by Gregory, and a few more minor -> to . conversions.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3708 96395faa-99c1-11dd-bbfe-3dabce05a288
2010-08-31 16:40:25 +00:00
Jake.Stine
003da7d287 MAJOR: All new hwRead and hwWrite handlers (expect regressions). Details:
* Writes via 16 and 8 bit ops now use 32-bit read/modify/write operations by default; which should enable nearly complete support for all such operations (instead of the formerly spotty coverage before).
 * Eliminated almost all former 8/16-bit specific register operations.  All code shares the same 32 bit handlers now.
 * Completely revamped the developer trace logs for hardware registers!  *ALL* registers are logged now, complete with address, name, and value being read/written (and nicely formatted!).
 * Handlers are now fully page-based using templated functions (minor speedup)


git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3704 96395faa-99c1-11dd-bbfe-3dabce05a288
2010-08-31 05:22:26 +00:00
Jake.Stine
bda94b16cd General emulator memory work, regarding my new policy that most (or all) cpu and hardware registers should be standard globals, as it makes our lives a lot easier in general (and their memory footprint is small so it won't adversely affect the virtual memory availability of the host operating systems). Details:
* Removed the hacky g_pVU1 pointer, which required VU1 cpu registers to be part of VU0.  Replaced it with a standard VU1 variable (mimics all other CPU registers, which are standard static vars).  We were using translation functions/tables for all VU0 memory operations anyway, so this was a no-brainer.
 * Removed code from microVU that was only there to help deal with the fact that g_pVU1 was annoying.
 * Turned eeMem->HW into a static global array eeHw [64k].

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3692 96395faa-99c1-11dd-bbfe-3dabce05a288
2010-08-27 03:21:16 +00:00
Jake.Stine
70cd51a64b A 'nice' fix for GCC's fickle dislike of packed structs. 1) the VU registers struct no longer needs packed (the unions ensure proper packing); 2) introduction of 128-bit UQ/SQ members.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3689 96395faa-99c1-11dd-bbfe-3dabce05a288
2010-08-25 15:32:17 +00:00
Jake.Stine
a8e406523b Improved EE/VTLB memory management: Removes various psM/psR/psS/psH pointers and replaces them with a single unified eeMem pointer. Members of eeMem correspond to Main, Scratchpad, Hardware, etc. This simplifies the EE's memory allocation, improves compiler optimization, gets rid of some macro mess, and allows templated code to deduce the size of memory buffers automatically.
* Includes a minor tweak to DMAC.h - removed tDMA_TADR / tDMA_MADR / etc. and replaced them with a single tDMAC_ADDR class.

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3644 96395faa-99c1-11dd-bbfe-3dabce05a288
2010-08-16 15:57:01 +00:00
Jake.Stine
20adde44a6 PCSX2/EEcore:
* Now using SSE for all hardware register reads and writes (mainly MFIFO stuff) [don't expect a speedup, really -- its more of a code simplification in this case].
 * [refactoring] Changed the EE Memory (vtlb) to use the u128 type instead of u64 for the 128-bit loads/stores (see mem128_t typedef)

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3626 96395faa-99c1-11dd-bbfe-3dabce05a288
2010-08-09 15:42:13 +00:00
Jake.Stine
575e1ceb46 * Converted SPR.cpp and hwMFIFOWrite to use memcpy_qwc in the place of memcpy_fast.
* Fix a bug in my merge of the new MTGS code that caused crashes on some games (PATH1 queue bug).
* Added assertion checks to hwMFIFOWrite for qwc alignment and a SPR_LOG for null ringbuffer addresses (if a game specifies an invalid physical address).

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3533 96395faa-99c1-11dd-bbfe-3dabce05a288
2010-07-19 05:40:35 +00:00
ramapcsx2
9a9f3a6914 There was a slight threading affinity issue with r3000, so we have to revert it :p
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3003 96395faa-99c1-11dd-bbfe-3dabce05a288
2010-05-14 17:20:06 +00:00
pcsx2guide
cbb865632d * Added support for up to 24 threads. If you have a cluster server at home, enjoy PS2 emulation at 20x normal speed!
* Added DX11 support. DX11 enabled cards now give a +~40% speedup
* New SSE-X instructions we invented for PCSX2. Give a +200% speedup even on old CPUs.
* Full 64bit support. If you have 64 bit windows, be prepared for a 300% speed up.
* Implemented new DMAC, so far we have ~15 games that show improvements.
* Added support for USB-enabled vibrators. Feel the full pleasure of gaming, now also with PCSX2!
* SPU2-X now decodes Dolby Digital 7.1!
* Please test to find any bugs in the 24-thread code, it's a bit complex so some tiny bugs might have crept in.

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3000 96395faa-99c1-11dd-bbfe-3dabce05a288
2010-05-13 21:15:55 +00:00
Jake.Stine
70d47bf240 Copyright 2010 : PCSX2 and plugins! (notable exception: didn't update copyright info in any Gabest plugins)
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2937 96395faa-99c1-11dd-bbfe-3dabce05a288
2010-05-03 14:08:02 +00:00
sudonim1
4457fe40fc Removed all trailing whitespace in *.c *.cpp *.h because it irritates me.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2897 96395faa-99c1-11dd-bbfe-3dabce05a288
2010-04-25 00:31:27 +00:00
sudonim1
a21fb4b984 Map uninstalled main memory (>32MB). I can't see any suggestion in the manuals that accessing these addresses generates a bus error or tlb miss (and they are in the bios default tlb initialisation), so I'm assuming that it acts as write only memory for both DMA and normal accesses. The write-only implementation is a little sketchy for DMA, but it's very unlikely to matter in practice.
Changed dmaGetAddr to not lookup addresses in the TLB.

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2883 96395faa-99c1-11dd-bbfe-3dabce05a288
2010-04-22 00:11:53 +00:00
arcum42
f3a2c44112 Did some work on HwWrite. Updated my structures in GS.h. Fixed some podsafe object warnings I'd missed previously.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2335 96395faa-99c1-11dd-bbfe-3dabce05a288
2009-12-10 06:33:14 +00:00
arcum42
8a4d58ff76 More Tag stuff, mainly in Gif and HwWrite.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2305 96395faa-99c1-11dd-bbfe-3dabce05a288
2009-12-04 07:01:27 +00:00
arcum42
9380a492b0 Some header cleanup.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2193 96395faa-99c1-11dd-bbfe-3dabce05a288
2009-11-13 04:36:01 +00:00
Jake.Stine
efc35405f8 Reorganized the exception/signal handlers, setjmp/longjmp, and SysCoreThread stuff:
* Exception/Signal handling now uses an EventSource, so that multiple handlers can be registered.  This is in preparation for (eventual) more complete MIPS TLB support in the VTLB memory model.
 * Improved code isolation, so that recompiler-specific code is primarily in iR5900-32.cpp (cleans up Counters.cpp and SysCoreThread.cpp)

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2063 96395faa-99c1-11dd-bbfe-3dabce05a288
2009-10-23 20:24:59 +00:00
Jake.Stine
e8e61a5cf8 Settings work again!
* Switched the SysCoreThread to a static (fully persistent) thread.
 * Added some listeners for when the CoreThread status changes
 * fixed some slowness in savestates, and the emu will now stall until savestates complete, if you try to exit too quick (avoids savestate corruption)

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1993 96395faa-99c1-11dd-bbfe-3dabce05a288
2009-10-09 15:17:53 +00:00
Jake.Stine
aaa3b773c6 Improved MTGS (added better suspend/resume support), and work on savestates a bit (still not working tho)
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1908 96395faa-99c1-11dd-bbfe-3dabce05a288
2009-09-23 09:53:21 +00:00
Jake.Stine
d2fbb22076 Upgraded PCSX2 core and utilities to GPLv3.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1783 96395faa-99c1-11dd-bbfe-3dabce05a288
2009-09-08 12:08:10 +00:00
Jake.Stine
49144a5331 wxgui:
* Removed some erroneous language error messages during first-time startup on non-english systems.
 * Cleaned up BIOS code a bit and moved all the scatterings from Memory.cpp, Misc.cpp, etc. into a single BiosTools.cpp file.
 * Implemented BIOS selector in the config dialog.

git-svn-id: http://pcsx2.googlecode.com/svn/branches/wxgui@1634 96395faa-99c1-11dd-bbfe-3dabce05a288
2009-08-16 06:26:40 +00:00
Jake.Stine
f6ce237b8e Did some general cleanups to vtlb's memory protection and recompiled block integrity checking systems.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1208 96395faa-99c1-11dd-bbfe-3dabce05a288
2009-05-17 03:57:18 +00:00
Jake.Stine
2bf04882e3 Some code cleanups for the new vtlb optimization (no intentional functional changes -- just deleted unused code and converted all of vtlb to the new emitter syntax. Let's hope I didn't typo anything!)
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1138 96395faa-99c1-11dd-bbfe-3dabce05a288
2009-05-06 12:37:37 +00:00
arcum42
a661c80a4a Some work on Vif & Hw.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@979 96395faa-99c1-11dd-bbfe-3dabce05a288
2009-04-15 04:41:42 +00:00
arcum42
fa1a79b368 Cleaned a few things up, and moved a few things around.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@978 96395faa-99c1-11dd-bbfe-3dabce05a288
2009-04-15 01:25:11 +00:00
arcum42
7744205a58 Assorted cleanup. A few compilation errors went away, a few useless variables are gone, a few if statements are now case statements. Added comments on a few potential problem areas.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@904 96395faa-99c1-11dd-bbfe-3dabce05a288
2009-04-04 07:48:50 +00:00