mirror of
https://github.com/PCSX2/pcsx2-sourceforge.git
synced 2026-02-04 03:11:18 +01:00
more misc counter fixes for various video issues etc.
This commit is contained in:
refractionpcsx2
@@ -60,13 +60,13 @@ void rcntSet() {
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for (i = 0; i < 4; i++) {
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if (!(counters[i].mode & 0x80)) continue; // Stopped
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c = (0xffff - rcntCycle(i)) * counters[i].rate;
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c = (0x10000 - rcntCycle(i)) * counters[i].rate;
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if (c < nextCounter) {
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nextCounter = c;
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}
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// the + 10 is just in case of overflow
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if(!(counters[i].mode & 0x100)) continue;
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if(!(counters[i].mode & 0x100) && (counters[i].target & 0xffff) > 0) continue;
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c = (counters[i].target - rcntCycle(i)) * counters[i].rate;
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if (c < nextCounter) {
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nextCounter = c;
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@@ -457,8 +457,29 @@ void rcntUpdate()
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for (i=0; i<=3; i++) {
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if (!(counters[i].mode & 0x80)) continue; // Stopped
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if (counters[i].count >= 0xffff) {
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//eecntmask &= ~(1 << i);
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if ((s64)(counters[i].target - counters[i].count) <= 0 && (counters[i].target & 0xffff) > 0) { // Target interrupt
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if(counters[i].mode & 0x100 ) {
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#ifdef EECNT_LOG
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EECNT_LOG("EE counter %d target reached mode %x count %x target %x\n", i, counters[i].mode, counters[i].count, counters[i].target);
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#endif
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counters[i].mode|= 0x0400; // Target flag
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hwIntcIrq(counters[i].interrupt);
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if (counters[i].mode & 0x40) { //The PS2 only resets if the interrupt is enabled - Tested on PS2
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if((counters[i].target > 0xffff)) {
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//SysPrintf("EE Correcting target %x after reset on target\n", i);
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counters[i].target &= 0xffff;
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}
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counters[i].count = 0; // Reset on target
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}
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else counters[i].target += 0x10000;
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}
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}
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if (counters[i].count > 0xffff) {
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if (counters[i].mode & 0x0200) { // Overflow interrupt
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#ifdef EECNT_LOG
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@@ -466,41 +487,15 @@ void rcntUpdate()
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#endif
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counters[i].mode|= 0x0800; // Overflow flag
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hwIntcIrq(counters[i].interrupt);
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// SysPrintf("counter[%d] overflow interrupt (%x)\n", i, cpuRegs.cycle);
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//SysPrintf("counter[%d] overflow interrupt (%x)\n", i, cpuRegs.cycle);
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}
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counters[i].count = 0;
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if(counters[i].target > 0xffff) {
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//SysPrintf("EE %x Correcting target\n", i);
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counters[i].target -= 0x10000;
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//SysPrintf("EE %x Correcting target on overflow\n", i);
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counters[i].target &= 0xffff;
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}
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}
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if ((s64)(counters[i].target - counters[i].count) <= 0 && (counters[i].mode & 0x400) == 0) { // Target interrupt
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/*if (rcntCycle(i) != counters[i].target){
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SysPrintf("rcntcycle = %d, target = %d, cyclet = %d\n", rcntCycle(i), counters[i].target, counters[i].sCycleT);
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counters[i].sCycleT += (rcntCycle(i) - counters[i].target) * counters[i].rate;
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SysPrintf("rcntcycle = %d, target = %d, cyclet = %d\n", rcntCycle(i), counters[i].target, counters[i].sCycleT);
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}*/
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//if ((eecntmask & (1 << i)) == 0) {
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if(counters[i].mode & 0x100 ) {
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#ifdef EECNT_LOG
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EECNT_LOG("EE counter %d target mode %x count %x target %x\n", i, counters[i].mode, counters[i].count, counters[i].target);
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#endif
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counters[i].mode|= 0x0400; // Target flag
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hwIntcIrq(counters[i].interrupt);
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if (counters[i].mode & 0x40) //The PS2 only resets if the interrupt is enabled - Tested on PS2
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counters[i].count = 0; // Reset on target
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}
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//eecntmask |= (1 << i);
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//}
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}
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// rcntUpd(i);
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}
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if ((cpuRegs.cycle - counters[4].sCycleT) >= counters[4].CycleT && hblankend == 1){
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@@ -546,13 +541,14 @@ void rcntUpdate()
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}
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void rcntWcount(int index, u32 value) {
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//SysPrintf ("writeCcount[%d] = %x\n", index, value);
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#ifdef EECNT_LOG
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EECNT_LOG("EE count write %d count %x with %x target %x eecycle %x\n", index, counters[index].count, value, counters[index].target, cpuRegs.eCycle);
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#endif
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//if((u16)value < counters[index].target)
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//eecntmask &= ~(1 << index);
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counters[index].count = value & 0xffff;
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if(counters[index].target > 0xffff) {
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counters[index].target &= 0xffff;
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//SysPrintf("EE Counter %x count write, target > 0xffff\n", index);
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}
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rcntUpd(index);
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rcntSet();
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}
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@@ -562,17 +558,15 @@ void rcntWmode(int index, u32 value)
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if (value & 0xc00) { //Clear status flags, the ps2 only clears what is given in the value
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//eecntmask &= ~(1 << index);
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counters[index].mode &= ~(value & 0xc00);
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}
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if((value & 0x80) && !(counters[index].mode & 0x80)) rcntUpd(index); //Counter wasnt started, so set the start cycle
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// if((value & 0x3ff) != (counters[index].mode & 0x3ff))eecntmask &= ~(1 << index);
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counters[index].mode = (counters[index].mode & 0xc00) | (value & 0x3ff);
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#ifdef EECNT_LOG
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EECNT_LOG("EE counter set %d mode %x\n", index, counters[index].mode);
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EECNT_LOG("EE counter set %d mode %x count %x\n", index, counters[index].mode, rcntCycle(index));
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#endif
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switch (value & 0x3) { //Clock rate divisers *2, they use BUSCLK speed not PS2CLK
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@@ -592,10 +586,10 @@ void rcntWmode(int index, u32 value)
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rcntReset(index);
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}
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else gates &= ~(1<<index);
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//counters[index].count = 0;
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if(counters[index].target > 0xffff) {
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if((counters[index].target > 0xffff) && (counters[index].target & 0xffff) > rcntCycle(index)) {
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//SysPrintf("EE Correcting target %x after mode write\n", index);
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counters[index].target -= 0x10000;
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counters[index].target &= 0xffff;
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}
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rcntSet();
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@@ -662,15 +656,14 @@ void rcntEndGate(int mode){
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}
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void rcntWtarget(int index, u32 value) {
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//eecntmask &= ~(1 << index);
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counters[index].target = value & 0xffff;
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if(counters[index].target < rcntCycle(index)) {
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//SysPrintf("EE Saving target %d from early trigger\n", index);
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counters[index].target += 0x10000;
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}
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#ifdef EECNT_LOG
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EECNT_LOG("EE target write %d target %x value %x\n", index, counters[index].target, value);
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#endif
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counters[index].target = value & 0xffff;
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if(counters[index].target <= rcntCycle(index) && counters[index].target != 0) {
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//SysPrintf("EE Saving target %d from early trigger, target = %x, count = %x\n", index, counters[index].target, rcntCycle(index));
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counters[index].target += 0x10000;
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}
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rcntSet();
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}
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@@ -28,19 +28,11 @@ u8 psxvblankgate = 0;
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u8 psxcntmask = 0;
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static void psxRcntUpd16(u32 index) {
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//psxCounters[index].sCycle = psxRegs.cycle;
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psxCounters[index].sCycleT = psxRegs.cycle;
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//psxCounters[index].Cycle = (0xffff - psxCounters[index].count) * psxCounters[index].rate;
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//psxCounters[index].CycleT = (psxCounters[index].target - psxCounters[index].count) * psxCounters[index].rate;
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}
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static void psxRcntUpd32(u32 index) {
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//psxCounters[index].sCycle = psxRegs.cycle;
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psxCounters[index].sCycleT = psxRegs.cycle;
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//psxCounters[index].Cycle = (0xfffee000 - psxCounters[index].count) * psxCounters[index].rate;
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//psxCounters[index].CycleT = (psxCounters[index].target - psxCounters[index].count) * psxCounters[index].rate;
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}
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static void psxRcntReset16(u32 index) {
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@@ -65,10 +57,11 @@ static void psxRcntSet() {
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psxNextsCounter = psxRegs.cycle;
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for (i=0; i<3; i++) {
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c = (u32)(0xffff - psxRcntCycles(i)) * psxCounters[i].rate;
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c = (u32)(0x10000 - psxRcntCycles(i)) * psxCounters[i].rate;
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if (c < psxNextCounter) {
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psxNextCounter = c;
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}
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if((psxCounters[i].mode & 0x100) == 0 || (psxCounters[i].target & 0xffff) == 0) continue;
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c = (u32)(psxCounters[i].target - psxRcntCycles(i)) * psxCounters[i].rate;
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if (c < psxNextCounter && c > 0) {
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psxNextCounter = c;
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@@ -76,11 +69,12 @@ static void psxRcntSet() {
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}
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for (i=3; i<6; i++) {
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c = (u32)(0xffffffff - psxRcntCycles(i)) * psxCounters[i].rate;
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c = (u32)(0x100000000 - psxRcntCycles(i)) * psxCounters[i].rate;
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if (c < psxNextCounter) {
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psxNextCounter = c;
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}
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if((psxCounters[i].mode & 0x100) == 0 || (psxCounters[i].target & 0xffffffff) == 0) continue;
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c = (u32)(psxCounters[i].target - psxRcntCycles(i)) * psxCounters[i].rate;
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if (c < psxNextCounter && c > 0) {
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psxNextCounter = c;
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@@ -275,23 +269,22 @@ void _testRcnt16target(int i) {
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#endif
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psxCounters[i].mode|= 0x0800; // Target flag
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//newtarget[i] = 0;
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if(psxCounters[i].mode & 0x80)
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if (psxCounters[i].mode & 0x10)psxCounters[i].mode&= ~0x0400; // Interrupt flag
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if (psxCounters[i].mode & 0x10) // Target interrupt
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psxHu32(0x1070)|= psxCounters[i].interrupt;
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if (psxCounters[i].mode & 0x10) { // Target interrupt
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psxHu32(0x1070)|= psxCounters[i].interrupt;
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}
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if (psxCounters[i].mode & 0x08) { // Reset on target
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psxCounters[i].count = 0;
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if(psxCounters[i].target > 0xffff) {
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//SysPrintf("IOP 16 Correcting target\n");
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psxCounters[i].target -= 0x10000;
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psxCounters[i].target &= 0xffff;
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//SysPrintf("IOP 16 Correcting target target %x\n", psxCounters[i].target);
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}
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}
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} else psxCounters[i].target += 0x10000;
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/*if(!(psxCounters[i].mode & 0x40))psxcntmask |= (1<<i);
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else psxcntmask &= ~(1<<i);*/
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}
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void _testRcnt16overflow(int i) {
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@@ -305,14 +298,15 @@ void _testRcnt16overflow(int i) {
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psxHu32(0x1070)|= psxCounters[i].interrupt;
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if(psxCounters[i].mode & 0x80)
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psxCounters[i].mode&= ~0x0400; // Interrupt flag
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//SysPrintf("Overflow 16\n");
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}
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psxCounters[i].count = 0;
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psxRcntUpd16(i);
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if(psxCounters[i].target > 0xffff) {
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//SysPrintf("IOP 16 Correcting target\n");
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psxCounters[i].target -= 0x10000;
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psxCounters[i].target &= 0xffff;
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//SysPrintf("IOP 16 Correcting target ovf %x\n", psxCounters[i].target);
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}
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//psxcntmask &= ~(1<<i);
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//psxRcntUpd16(i);
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}
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void _testRcnt32target(int i) {
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@@ -323,23 +317,24 @@ void _testRcnt32target(int i) {
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psxCounters[i].mode|= 0x0800; // Target flag
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// newtarget[i] = 0;
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if(psxCounters[i].mode & 0x80)
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if (psxCounters[i].mode & 0x10)psxCounters[i].mode&= ~0x0400; // Interrupt flag
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if (psxCounters[i].mode & 0x10) // Target interrupt
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if (psxCounters[i].mode & 0x10) { // Target interrupt
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psxHu32(0x1070)|= psxCounters[i].interrupt;
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}
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if (psxCounters[i].mode & 0x08) { // Reset on target
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psxCounters[i].count = 0;
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if(psxCounters[i].target > 0xffffffff) {
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//SysPrintf("IOP 32 Correcting target\n");
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psxCounters[i].target -= 0x100000000;
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//SysPrintf("IOP 32 Correcting target on target reset\n");
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psxCounters[i].target &= 0xffffffff;
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}
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}
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} else psxCounters[i].target += 0x100000000;
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/*if(!(psxCounters[i].mode & 0x40))psxcntmask |= (1<<i);
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else psxcntmask &= ~(1<<i);*/
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}
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void _testRcnt32overflow(int i) {
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@@ -347,7 +342,7 @@ void _testRcnt32overflow(int i) {
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#ifdef PSXCNT_LOG
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PSXCNT_LOG("[%d] overflow 0x%x >= 0x%x (Cycle); Rcount=0x%x, count=0x%x\n", i, (psxRegs.cycle - psxCounters[i].sCycle), psxCounters[i].Cycle, psxRcntRcount32(i), psxCounters[i].count);
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#endif
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SysPrintf("Overflow \n");
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//SysPrintf("Overflow 32\n");
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psxCounters[i].mode|= 0x1000; // Overflow flag
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if (psxCounters[i].mode & 0x0020) { // Overflow interrupt
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psxHu32(0x1070)|= psxCounters[i].interrupt;
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@@ -356,42 +351,28 @@ void _testRcnt32overflow(int i) {
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}
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psxCounters[i].count = 0;
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if(psxCounters[i].target > 0xffffffff) {
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//SysPrintf("IOP 32 Correcting target\n");
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psxCounters[i].target -= 0x100000000;
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//SysPrintf("IOP 32 Correcting target on overflow\n");
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psxCounters[i].target &= 0xffffffff;
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}
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//psxcntmask &= ~(1<<i);
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//psxRcntUpd32(i);
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//psxRcntSet();
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}
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void _testRcnt16(int i) {
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/*if(!(psxHu32(0x1070) & psxCounters[i].interrupt)) {
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}*/
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if (psxCounters[i].count >= 0xffff)
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_testRcnt16overflow(i);
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if (/*!(psxcntmask & (1<<i))&&*/ (s64)(psxCounters[i].target - psxCounters[i].count) <= 0){
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if (psxCounters[i].target > 0 && (s64)(psxCounters[i].target - psxCounters[i].count) <= 0){
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_testRcnt16target(i);
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}
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if (psxCounters[i].count > 0xffff)
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_testRcnt16overflow(i);
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}
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void _testRcnt32(int i) {
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/*if(!(psxHu32(0x1070) & psxCounters[i].interrupt)) {
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psxCounters[i].mode &= ~0x1800;
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psxCounters[i].mode |= 0x400;
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}*/
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if (psxCounters[i].count >= 0xffffffff)
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_testRcnt32overflow(i);
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if (/*!(psxcntmask & (1<<i)) &&*/ (s64)(psxCounters[i].target - psxCounters[i].count) <= 0){
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if (psxCounters[i].target > 0 && (s64)(psxCounters[i].target - psxCounters[i].count) <= 0){
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_testRcnt32target(i);
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}
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if (psxCounters[i].count > 0xffffffff)
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_testRcnt32overflow(i);
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}
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@@ -414,14 +395,14 @@ void psxRcntUpdate() {
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if(SPU2async)
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{
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if ((psxRegs.cycle - psxCounters[6].sCycleT) >= psxCounters[6].CycleT) {
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SPU2async(psxRegs.cycle - psxCounters[6].sCycleT);//(u32)(psxRegs.cycle - psxNextsCounter));
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SPU2async(psxRegs.cycle - psxCounters[6].sCycleT);
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psxCounters[6].sCycleT = psxRegs.cycle;
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}
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}
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if(USBasync)
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{
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if ((psxRegs.cycle - psxCounters[7].sCycleT) >= psxCounters[7].CycleT) {
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USBasync(psxRegs.cycle - psxCounters[7].sCycleT);//(u32)(psxRegs.cycle - psxNextsCounter));
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USBasync(psxRegs.cycle - psxCounters[7].sCycleT);
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psxCounters[7].sCycleT = psxRegs.cycle;
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}
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}
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@@ -433,9 +414,13 @@ void psxRcntWcount16(int index, u32 value) {
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#ifdef PSXCNT_LOG
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PSXCNT_LOG("writeCcount[%d] = %x\n", index, value);
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#endif
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SysPrintf("Write to 16bit count reg counter %x\n",index);
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psxCounters[index].count = value & 0xffff;
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SysPrintf("Counter %x count write %x\n", index, value);
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if(psxCounters[index].target > 0xffff) {
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//SysPrintf("IOP 16 Correcting target on count write\n");
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psxCounters[index].target -= 0x10000;
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}
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psxRcntUpd16(index);
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psxRcntSet();
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}
|
||||
@@ -444,18 +429,21 @@ void psxRcntWcount32(int index, u32 value) {
|
||||
#ifdef PSXCNT_LOG
|
||||
PSXCNT_LOG("writeCcount[%d] = %x\n", index, value);
|
||||
#endif
|
||||
SysPrintf("Write to 32bit count reg counter %x\n", index);
|
||||
|
||||
psxCounters[index].count = value;
|
||||
SysPrintf("Counter %x count write %x\n", index, value);
|
||||
if(psxCounters[index].target > 0xffffffff) {
|
||||
//SysPrintf("IOP 32 Correcting target\n");
|
||||
psxCounters[index].target &= 0xffffffff;
|
||||
}
|
||||
psxRcntUpd32(index);
|
||||
psxRcntSet();
|
||||
}
|
||||
|
||||
void psxRcnt0Wmode(u32 value) {
|
||||
#ifdef PSXCNT_LOG
|
||||
//PSXCNT_LOG("IOP writeCmode[0] = %lx\n", value);
|
||||
PSXCNT_LOG("IOP writeCmode[0] = %lx\n", value);
|
||||
#endif
|
||||
SysPrintf("Counter Mode Write %x value %x\n", 0, value);
|
||||
|
||||
if (value & 0x1c00) {
|
||||
SysPrintf("Counter 0 Value write %x\n", value & 0x1c00);
|
||||
}
|
||||
@@ -463,7 +451,7 @@ void psxRcnt0Wmode(u32 value) {
|
||||
psxCounters[0].mode = value;
|
||||
psxCounters[0].mode|= 0x0400;
|
||||
psxCounters[0].rate = 1;
|
||||
//psxcntmask &= ~(1);
|
||||
|
||||
if(value & 0x100) psxCounters[0].rate = PSXPIXEL;
|
||||
|
||||
if(psxCounters[0].mode & 0x1){
|
||||
@@ -477,7 +465,7 @@ void psxRcnt0Wmode(u32 value) {
|
||||
psxRcntUpd16(0);
|
||||
if(psxCounters[0].target > 0xffff) {
|
||||
//SysPrintf("IOP 16 Correcting target 0 after mode write\n");
|
||||
psxCounters[0].target -= 0x10000;
|
||||
psxCounters[0].target &= 0xffff;
|
||||
}
|
||||
psxRcntSet();
|
||||
//}
|
||||
@@ -487,7 +475,7 @@ void psxRcnt1Wmode(u32 value) {
|
||||
#ifdef PSXCNT_LOG
|
||||
PSXCNT_LOG("IOP writeCmode[1] = %lx\n", value);
|
||||
#endif
|
||||
SysPrintf("Counter Mode Write %x value %x\n", 1, value);
|
||||
|
||||
if (value & 0x1c00) {
|
||||
SysPrintf("Counter 1 Value write %x\n", value & 0x1c00);
|
||||
}
|
||||
@@ -495,7 +483,7 @@ void psxRcnt1Wmode(u32 value) {
|
||||
psxCounters[1].mode = value;
|
||||
psxCounters[1].mode|= 0x0400;
|
||||
psxCounters[1].rate = 1;
|
||||
//psxcntmask &= ~(1<<1);
|
||||
|
||||
if(value & 0x100)psxCounters[1].rate = PSXHBLANK;
|
||||
|
||||
if(psxCounters[1].mode & 0x1){
|
||||
@@ -509,7 +497,7 @@ void psxRcnt1Wmode(u32 value) {
|
||||
psxRcntUpd16(1);
|
||||
if(psxCounters[1].target > 0xffff) {
|
||||
//SysPrintf("IOP 16 Correcting target 1 after mode write\n");
|
||||
psxCounters[1].target -= 0x10000;
|
||||
psxCounters[1].target &= 0xffff;
|
||||
}
|
||||
psxRcntSet();
|
||||
//}
|
||||
@@ -519,12 +507,11 @@ void psxRcnt2Wmode(u32 value) {
|
||||
#ifdef PSXCNT_LOG
|
||||
PSXCNT_LOG("IOP writeCmode[2] = %lx\n", value);
|
||||
#endif
|
||||
SysPrintf("Counter Mode Write %x value %x\n", 2, value);
|
||||
|
||||
if (value & 0x1c00) {
|
||||
SysPrintf("Counter 2 Value write %x\n", value & 0x1c00);
|
||||
}
|
||||
|
||||
//psxcntmask &= ~(1<<2);
|
||||
psxCounters[2].mode = value;
|
||||
psxCounters[2].mode|= 0x0400;
|
||||
|
||||
@@ -538,7 +525,7 @@ void psxRcnt2Wmode(u32 value) {
|
||||
}
|
||||
|
||||
if((psxCounters[2].mode & 0x7) == 0x7 || (psxCounters[2].mode & 0x7) == 0x1){
|
||||
SysPrintf("Gate set on IOP C2, disabling\n");
|
||||
//SysPrintf("Gate set on IOP C2, disabling\n");
|
||||
psxCounters[2].mode|= 0x1000000;
|
||||
}
|
||||
// Need to set a rate and target
|
||||
@@ -546,7 +533,7 @@ void psxRcnt2Wmode(u32 value) {
|
||||
psxRcntUpd16(2);
|
||||
if(psxCounters[2].target > 0xffff) {
|
||||
//SysPrintf("IOP 16 Correcting target 2 after mode write\n");
|
||||
psxCounters[2].target -= 0x10000;
|
||||
psxCounters[2].target &= 0xffff;
|
||||
}
|
||||
psxRcntSet();
|
||||
}
|
||||
@@ -555,12 +542,11 @@ void psxRcnt3Wmode(u32 value) {
|
||||
#ifdef PSXCNT_LOG
|
||||
PSXCNT_LOG("IOP writeCmode[3] = %lx\n", value);
|
||||
#endif
|
||||
SysPrintf("Counter Mode Write %x value %x\n", 3, value);
|
||||
|
||||
if (value & 0x1c00) {
|
||||
SysPrintf("Counter 3 Value write %x\n", value & 0x1c00);
|
||||
}
|
||||
|
||||
//psxcntmask &= ~(1<<3);
|
||||
psxCounters[3].mode = value;
|
||||
psxCounters[3].rate = 1;
|
||||
psxCounters[3].mode|= 0x0400;
|
||||
@@ -578,7 +564,7 @@ void psxRcnt3Wmode(u32 value) {
|
||||
psxRcntUpd32(3);
|
||||
if(psxCounters[3].target > 0xffffffff) {
|
||||
//SysPrintf("IOP 32 Correcting target 3 after mode write\n");
|
||||
psxCounters[3].target -= 0x100000000;
|
||||
psxCounters[3].target &= 0xffffffff;
|
||||
}
|
||||
psxRcntSet();
|
||||
//}
|
||||
@@ -588,12 +574,11 @@ void psxRcnt4Wmode(u32 value) {
|
||||
#ifdef PSXCNT_LOG
|
||||
PSXCNT_LOG("IOP writeCmode[4] = %lx\n", value);
|
||||
#endif
|
||||
SysPrintf("Counter Mode Write %x value %x\n", 4, value);
|
||||
|
||||
if (value & 0x1c00) {
|
||||
SysPrintf("Counter 4 Value write %x\n", value & 0x1c00);
|
||||
}
|
||||
|
||||
//psxcntmask &= ~(1<<4);
|
||||
psxCounters[4].mode = value;
|
||||
psxCounters[4].mode|= 0x0400;
|
||||
|
||||
@@ -620,7 +605,7 @@ void psxRcnt4Wmode(u32 value) {
|
||||
psxRcntUpd32(4);
|
||||
if(psxCounters[4].target > 0xffffffff) {
|
||||
//SysPrintf("IOP 32 Correcting target 4 after mode write\n");
|
||||
psxCounters[4].target -= 0x100000000;
|
||||
psxCounters[4].target &= 0xffffffff;
|
||||
}
|
||||
psxRcntSet();
|
||||
}
|
||||
@@ -629,11 +614,11 @@ void psxRcnt5Wmode(u32 value) {
|
||||
#ifdef PSXCNT_LOG
|
||||
PSXCNT_LOG("IOP writeCmode[5] = %lx\n", value);
|
||||
#endif
|
||||
SysPrintf("Counter Mode Write %x value %x\n", 5, value);
|
||||
|
||||
if (value & 0x1c00) {
|
||||
SysPrintf("Counter 5 Value write %x\n", value & 0x1c00);
|
||||
}
|
||||
//psxcntmask &= ~(1<<5);
|
||||
|
||||
psxCounters[5].mode = value;
|
||||
psxCounters[5].mode|= 0x0400;
|
||||
|
||||
@@ -660,50 +645,36 @@ void psxRcnt5Wmode(u32 value) {
|
||||
psxRcntUpd32(5);
|
||||
if(psxCounters[5].target > 0xffffffff) {
|
||||
//SysPrintf("IOP 32 Correcting target 5 after mode write\n");
|
||||
psxCounters[5].target -= 0x100000000;
|
||||
psxCounters[5].target &= 0xffffffff;
|
||||
}
|
||||
psxRcntSet();
|
||||
}
|
||||
|
||||
void psxRcntWtarget16(int index, u32 value) {
|
||||
//if(psxCounters[index].sCycleT > psxRegs.cycle) ReSyncTarget(index);
|
||||
#ifdef PSXCNT_LOG
|
||||
PSXCNT_LOG("writeCtarget16[%ld] = %lx\n", index, value);
|
||||
#endif
|
||||
psxCounters[index].target = value & 0xffff;
|
||||
if(psxCounters[index].target < psxCounters[index].count) {
|
||||
//SysPrintf("IOP 16 Saving target from early trigger\n");
|
||||
if(psxCounters[index].target <= psxRcntCycles(index) && psxCounters[index].target != 0) {
|
||||
//SysPrintf("IOP 16 Saving %x target from early trigger target = %x, count = %I64x\n", index, psxCounters[index].target, psxRcntCycles(index));
|
||||
psxCounters[index].target += 0x10000;
|
||||
}
|
||||
//newtarget[index] = 1;
|
||||
/*if (psxCounters[index].mode & 0x8) { // Reset on target
|
||||
psxCounters[index].count = 0;
|
||||
psxRcntUpd32(index);
|
||||
//return;
|
||||
} */
|
||||
|
||||
psxRcntSet();
|
||||
}
|
||||
|
||||
void psxRcntWtarget32(int index, u32 value) {
|
||||
//if(psxCounters[index].sCycleT > psxRegs.cycle) ReSyncTarget(index);
|
||||
psxCounters[index].target = value;
|
||||
if(psxCounters[index].target < psxCounters[index].count) {
|
||||
//SysPrintf("IOP 32 Saving target from early trigger\n");
|
||||
psxCounters[index].target += 0x100000000;
|
||||
}
|
||||
//newtarget[index] = 1;
|
||||
#ifdef PSXCNT_LOG
|
||||
PSXCNT_LOG("writeCtarget32[%ld] = %lx (count=%lx) ; sCycleT: %x CycleT: %x psxRegscycle %x\n",
|
||||
index, value, psxCounters[index].count, psxCounters[index].sCycleT, psxCounters[index].CycleT, psxRegs.cycle);
|
||||
|
||||
#endif
|
||||
|
||||
//if(index == 5) SysPrintf("Counter 5 tar set CT %x, Tar %x, mode %x, psx.cycle %x\n", psxCounters[index].CycleT + psxCounters[index].sCycleT, psxCounters[index].target, psxCounters[index].mode, psxRegs.cycle);
|
||||
/*if (psxCounters[index].mode & 0x8) { // Reset on target
|
||||
psxCounters[index].count = 0;
|
||||
psxRcntUpd32(index);
|
||||
//return;
|
||||
} */
|
||||
psxCounters[index].target = value;
|
||||
if(psxCounters[index].target <= psxRcntCycles(index) && psxCounters[index].target != 0) {
|
||||
//SysPrintf("IOP 32 Saving %x target from early trigger target = %x, count = %I64x\n", index, psxCounters[index].target, psxRcntCycles(index));
|
||||
psxCounters[index].target += 0x100000000;
|
||||
}
|
||||
|
||||
psxRcntSet();
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user