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Fix doc for t inline asm constraints for ARM/Thumb

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Summary: The constraint goes up to regs d15 and q7, not d16 and q8.

Subscribers: kristof.beyls, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D68090

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373228 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Pablo Barrio
2019-09-30 16:55:10 +00:00
parent b40beba15e
commit 1da64d7038
1 changed files with 12 additions and 12 deletions
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24
docs/LangRef.rst
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@@ -3862,12 +3862,12 @@ ARM and ARM's Thumb2 mode:
as ``r``.
- ``h``: In Thumb2 mode, a high 32-bit GPR register (``r8-r15``). In ARM mode,
invalid.
- ``w``: A 32, 64, or 128-bit floating-point/SIMD register: ``s0-s31``,
``d0-d31``, or ``q0-q15``.
- ``x``: A 32, 64, or 128-bit floating-point/SIMD register: ``s0-s15``,
``d0-d7``, or ``q0-q3``.
- ``t``: A low floating-point/SIMD register: ``s0-s31``, ``d0-d16``, or
``q0-q8``.
- ``w``: A 32, 64, or 128-bit floating-point/SIMD register in the ranges
``s0-s31``, ``d0-d31``, or ``q0-q15``, respectively.
- ``t``: A 32, 64, or 128-bit floating-point/SIMD register in the ranges
``s0-s31``, ``d0-d15``, or ``q0-q7``, respectively.
- ``x``: A 32, 64, or 128-bit floating-point/SIMD register in the ranges
``s0-s15``, ``d0-d7``, or ``q0-q3``, respectively.
ARM's Thumb1 mode:
@@ -3882,12 +3882,12 @@ ARM's Thumb1 mode:
- ``r``: A low 32-bit GPR register (``r0-r7``).
- ``l``: A low 32-bit GPR register (``r0-r7``).
- ``h``: A high GPR register (``r0-r7``).
- ``w``: A 32, 64, or 128-bit floating-point/SIMD register: ``s0-s31``,
``d0-d31``, or ``q0-q15``.
- ``x``: A 32, 64, or 128-bit floating-point/SIMD register: ``s0-s15``,
``d0-d7``, or ``q0-q3``.
- ``t``: A low floating-point/SIMD register: ``s0-s31``, ``d0-d16``, or
``q0-q8``.
- ``w``: A 32, 64, or 128-bit floating-point/SIMD register in the ranges
``s0-s31``, ``d0-d31``, or ``q0-q15``, respectively.
- ``t``: A 32, 64, or 128-bit floating-point/SIMD register in the ranges
``s0-s31``, ``d0-d15``, or ``q0-q7``, respectively.
- ``x``: A 32, 64, or 128-bit floating-point/SIMD register in the ranges
``s0-s15``, ``d0-d7``, or ``q0-q3``, respectively.
Hexagon: