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https://github.com/RPCS3/llvm.git
synced 2026-01-31 01:25:19 +01:00
LiveIntervals: Fix handleMoveUp with subreg def moving across a def
If a subregister def was moved across another subregister def and another use, the main range was not correctly updated. The end point of the moved interval ended too early and missed the use from theh other lanes in the subreg def. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375300 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault
@@ -1288,6 +1288,20 @@ private:
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const SlotIndex SplitPos = NewIdxDef;
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OldIdxVNI = OldIdxIn->valno;
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SlotIndex NewDefEndPoint = std::next(NewIdxIn)->end;
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LiveRange::iterator Prev = std::prev(OldIdxIn);
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if (OldIdxIn != LR.begin() &&
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SlotIndex::isEarlierInstr(NewIdx, Prev->end)) {
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// If the segment before OldIdx read a value defined earlier than
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// NewIdx, the moved instruction also reads and forwards that
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// value. Extend the lifetime of the new def point.
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// Extend to where the previous range started, unless there is
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// another redef first.
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NewDefEndPoint = std::min(OldIdxIn->start,
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std::next(NewIdxOut)->start);
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}
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// Merge the OldIdxIn and OldIdxOut segments into OldIdxOut.
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OldIdxOut->valno->def = OldIdxIn->start;
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*OldIdxOut = LiveRange::Segment(OldIdxIn->start, OldIdxOut->end,
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@@ -1305,7 +1319,8 @@ private:
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// There is no gap between NewSegment and its predecessor.
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*NewSegment = LiveRange::Segment(Next->start, SplitPos,
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Next->valno);
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*Next = LiveRange::Segment(SplitPos, Next->end, OldIdxVNI);
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*Next = LiveRange::Segment(SplitPos, NewDefEndPoint, OldIdxVNI);
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Next->valno->def = SplitPos;
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} else {
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// There is a gap between NewSegment and its predecessor
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@@ -0,0 +1,134 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -verify-misched -run-pass=machine-scheduler -o - %s | FileCheck %s
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---
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name: handleMoveUp_incorrect_interval
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tracksRegLiveness: true
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liveins:
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- { reg: '$sgpr4_sgpr5', virtual-reg: '%0' }
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo:
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isEntryFunction: true
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scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'
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scratchWaveOffsetReg: '$sgpr101'
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frameOffsetReg: '$sgpr101'
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stackPtrOffsetReg: '$sgpr101'
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argumentInfo:
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privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
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kernargSegmentPtr: { reg: '$sgpr4_sgpr5' }
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workGroupIDX: { reg: '$sgpr6' }
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privateSegmentWaveByteOffset: { reg: '$sgpr7' }
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workItemIDX: { reg: '$vgpr0' }
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body: |
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; CHECK-LABEL: name: handleMoveUp_incorrect_interval
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: liveins: $sgpr4_sgpr5
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; CHECK: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr4_sgpr5
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; CHECK: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN undef %2:vgpr_32, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr101, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 4, addrspace 5)
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; CHECK: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sgpr_64 = S_LOAD_DWORDX2_IMM [[COPY]](p4), 0, 0, 0 :: (dereferenceable invariant load 8, align 16, addrspace 4)
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; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 5329
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; CHECK: undef %5.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
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; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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; CHECK: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -4, implicit $exec
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; CHECK: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
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; CHECK: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK: bb.1:
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: INLINEASM &"", 1, 851978, def dead %11
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; CHECK: GLOBAL_STORE_DWORD undef %12:vreg_64, [[BUFFER_LOAD_DWORD_OFFEN]], 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
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; CHECK: [[DS_READ_B64_gfx9_:%[0-9]+]]:vreg_64 = DS_READ_B64_gfx9 undef %14:vgpr_32, 0, 0, implicit $exec :: (load 8, addrspace 3)
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; CHECK: INLINEASM &"def $0 $1", 1, 851978, def %15, 851978, def %16
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; CHECK: [[DS_READ_B32_gfx9_:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_]], 0, 0, implicit $exec
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; CHECK: [[DS_READ_B32_gfx9_1:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_1]], 0, 0, implicit $exec
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; CHECK: [[DS_READ_B32_gfx9_2:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 undef %20:vgpr_32, 0, 0, implicit $exec
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; CHECK: INLINEASM &"def $0 $1", 1, 851978, def %21, 851978, def %22
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; CHECK: [[DS_READ_B32_gfx9_3:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_1]], 0, 0, implicit $exec
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; CHECK: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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; CHECK: %5.sub1:vreg_64 = COPY [[V_MOV_B32_e32_]]
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; CHECK: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 1, [[DEF2]], implicit $exec
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; CHECK: [[V_CMP_GT_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_GT_U32_e64 64, [[V_ADD_U32_e32_]], implicit $exec
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; CHECK: [[DEF]].sub1:vreg_64 = COPY [[V_MOV_B32_e32_]]
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; CHECK: [[V_MOV_B32_e32_3:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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; CHECK: INLINEASM &"", 1, 851978, def dead [[V_MOV_B32_e32_2]], 851978, def dead [[V_MOV_B32_e32_3]], 851977, [[DS_READ_B64_gfx9_]].sub0, 2147483657, [[V_MOV_B32_e32_2]](tied-def 3), 2147549193, [[V_MOV_B32_e32_3]](tied-def 5), 851977, %15, 851977, %16, 851977, [[DS_READ_B32_gfx9_1]], 851977, [[DS_READ_B32_gfx9_]], 851977, [[DS_READ_B32_gfx9_3]], 851977, [[DS_READ_B32_gfx9_2]]
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; CHECK: DS_WRITE_B32_gfx9 undef %28:vgpr_32, %21, 0, 0, implicit $exec :: (store 4, addrspace 3)
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; CHECK: DS_WRITE_B32_gfx9 undef %29:vgpr_32, %22, 0, 0, implicit $exec :: (store 4, addrspace 3)
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; CHECK: DS_WRITE_B64_gfx9 undef %30:vgpr_32, %5, 0, 0, implicit $exec :: (store 8, addrspace 3)
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; CHECK: undef %31.sub1:vreg_64 = FLAT_LOAD_DWORD undef %32:vreg_64, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)
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; CHECK: [[V_MUL_LO_U32_:%[0-9]+]]:vgpr_32 = V_MUL_LO_U32 [[V_ADD_U32_e32_]], [[S_MOV_B32_]], implicit $exec
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; CHECK: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, [[V_ADD_U32_e32_]], [[V_CMP_GT_U32_e64_]], implicit $exec
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; CHECK: [[V_SUB_U32_e32_:%[0-9]+]]:vgpr_32 = V_SUB_U32_e32 [[V_MUL_LO_U32_]], [[DEF1]], implicit $exec
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; CHECK: [[V_MUL_LO_U32_1:%[0-9]+]]:vgpr_32 = V_MUL_LO_U32 [[V_CNDMASK_B32_e64_]], [[S_MOV_B32_]], implicit $exec
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; CHECK: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[V_SUB_U32_e32_]], [[DEF]].sub0, implicit $exec
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; CHECK: [[V_SUB_U32_e32_1:%[0-9]+]]:vgpr_32 = V_SUB_U32_e32 [[V_MUL_LO_U32_1]], [[V_MUL_LO_U32_]], implicit $exec
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; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[S_LOAD_DWORDX2_IMM]].sub1
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; CHECK: [[DEF]].sub0:vreg_64 = V_ADD_U32_e32 [[V_SUB_U32_e32_1]], [[V_ADD_U32_e32_1]], implicit $exec
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; CHECK: undef %38.sub0:vreg_64, %39:sreg_64_xexec = V_ADD_I32_e64 [[S_LOAD_DWORDX2_IMM]].sub0, [[DEF]].sub0, 0, implicit $exec
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; CHECK: undef %40.sub1:vreg_64, dead %41:sreg_64_xexec = V_ADDC_U32_e64 [[COPY1]], [[DEF]].sub1, %39, 0, implicit $exec
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; CHECK: undef %42.sub0:sgpr_64 = V_READFIRSTLANE_B32 %38.sub0, implicit $exec
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; CHECK: %42.sub1:sgpr_64 = V_READFIRSTLANE_B32 %40.sub1, implicit $exec
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; CHECK: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %42, 0, 0, 0 :: (load 4, addrspace 1)
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; CHECK: INLINEASM &"", 1
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; CHECK: [[DS_READ_B32_gfx9_4:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 undef %45:vgpr_32, 0, 0, implicit $exec :: (load 4, addrspace 3)
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; CHECK: GLOBAL_STORE_DWORD undef %46:vreg_64, [[DS_READ_B32_gfx9_4]], 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
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; CHECK: %31.sub0:vreg_64 = COPY [[S_LOAD_DWORD_IMM]], implicit $exec
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; CHECK: DS_WRITE_B64_gfx9 undef %47:vgpr_32, %31, 0, 0, implicit $exec :: (store 8, addrspace 3)
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; CHECK: S_BRANCH %bb.1
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bb.0:
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liveins: $sgpr4_sgpr5
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%0:sgpr_64(p4) = COPY $sgpr4_sgpr5
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%1:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN undef %2:vgpr_32, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr101, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 4, addrspace 5)
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%3:sgpr_64 = S_LOAD_DWORDX2_IMM %0(p4), 0, 0, 0 :: (dereferenceable invariant load 8, align 16, addrspace 4)
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%4:sreg_32_xm0 = S_MOV_B32 5329
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undef %5.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
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%6:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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%7:vgpr_32 = V_MOV_B32_e32 -4, implicit $exec
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%8:vreg_64 = IMPLICIT_DEF
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%9:vgpr_32 = IMPLICIT_DEF
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%10:vgpr_32 = IMPLICIT_DEF
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bb.1:
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INLINEASM &"", 1, 851978, def %11:vgpr_32
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GLOBAL_STORE_DWORD undef %12:vreg_64, %1, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
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%13:vreg_64 = DS_READ_B64_gfx9 undef %14:vgpr_32, 0, 0, implicit $exec :: (load 8, addrspace 3)
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INLINEASM &"def $0 $1", 1, 851978, def %15:vgpr_32, 851978, def %16:vgpr_32
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%17:vgpr_32 = DS_READ_B32_gfx9 %6, 0, 0, implicit $exec
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%18:vgpr_32 = DS_READ_B32_gfx9 %7, 0, 0, implicit $exec
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%19:vgpr_32 = DS_READ_B32_gfx9 undef %20:vgpr_32, 0, 0, implicit $exec
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INLINEASM &"def $0 $1", 1, 851978, def %21:vgpr_32, 851978, def %22:vgpr_32
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%23:vgpr_32 = DS_READ_B32_gfx9 %7, 0, 0, implicit $exec
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%24:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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%5.sub1:vreg_64 = COPY %6
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%25:vgpr_32 = V_ADD_U32_e32 1, %10, implicit $exec
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%26:sreg_64_xexec = V_CMP_GT_U32_e64 64, %25, implicit $exec
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%27:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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INLINEASM &"", 1, 851978, def dead %24, 851978, def dead %27, 851977, %13.sub0, 2147483657, %24(tied-def 3), 2147549193, %27(tied-def 5), 851977, %15, 851977, %16, 851977, %18, 851977, %17, 851977, %23, 851977, %19
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DS_WRITE_B32_gfx9 undef %28:vgpr_32, %21, 0, 0, implicit $exec :: (store 4, addrspace 3)
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DS_WRITE_B32_gfx9 undef %29:vgpr_32, %22, 0, 0, implicit $exec :: (store 4, addrspace 3)
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DS_WRITE_B64_gfx9 undef %30:vgpr_32, %5, 0, 0, implicit $exec :: (store 8, addrspace 3)
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undef %31.sub1:vreg_64 = FLAT_LOAD_DWORD undef %32:vreg_64, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)
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%33:vgpr_32 = V_MUL_LO_U32 %25, %4, implicit $exec
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%10:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, %25, %26, implicit $exec
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%34:vgpr_32 = V_SUB_U32_e32 %33, %9, implicit $exec
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%9:vgpr_32 = V_MUL_LO_U32 %10, %4, implicit $exec
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%35:vgpr_32 = V_ADD_U32_e32 %34, %8.sub0, implicit $exec
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%36:vgpr_32 = V_SUB_U32_e32 %9, %33, implicit $exec
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%37:vgpr_32 = COPY %3.sub1
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undef %8.sub0:vreg_64 = V_ADD_U32_e32 %36, %35, implicit $exec
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%8.sub1:vreg_64 = COPY %6
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undef %38.sub0:vreg_64, %39:sreg_64_xexec = V_ADD_I32_e64 %3.sub0, %8.sub0, 0, implicit $exec
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undef %40.sub1:vreg_64, dead %41:sreg_64_xexec = V_ADDC_U32_e64 %37, %8.sub1, %39, 0, implicit $exec
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undef %42.sub0:sgpr_64 = V_READFIRSTLANE_B32 %38.sub0, implicit $exec
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%42.sub1:sgpr_64 = V_READFIRSTLANE_B32 %40.sub1, implicit $exec
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%43:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %42, 0, 0, 0 :: (load 4, addrspace 1)
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INLINEASM &"", 1
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%44:vgpr_32 = DS_READ_B32_gfx9 undef %45:vgpr_32, 0, 0, implicit $exec :: (load 4, addrspace 3)
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GLOBAL_STORE_DWORD undef %46:vreg_64, %44, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
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%31.sub0:vreg_64 = COPY %43, implicit $exec
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DS_WRITE_B64_gfx9 undef %47:vgpr_32, %31, 0, 0, implicit $exec :: (store 8, addrspace 3)
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S_BRANCH %bb.1
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...
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@@ -421,6 +421,46 @@ TEST(LiveIntervalTest, DeadSubRegMoveUp) {
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});
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}
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TEST(LiveIntervalTest, TestMoveSubRegDefAcrossUseDef) {
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liveIntervalTest(R"MIR(
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%1:vreg_64 = IMPLICIT_DEF
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bb.1:
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%2:vgpr_32 = V_MOV_B32_e32 2, implicit $exec
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%3:vgpr_32 = V_ADD_U32_e32 %2, %1.sub0, implicit $exec
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undef %1.sub0:vreg_64 = V_ADD_U32_e32 %2, %2, implicit $exec
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%1.sub1:vreg_64 = COPY %2
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S_NOP 0, implicit %1.sub1
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S_BRANCH %bb.1
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)MIR", [](MachineFunction &MF, LiveIntervals &LIS) {
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MachineInstr &UndefSubregDef = getMI(MF, 2, 1);
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// The scheduler clears undef from subregister defs before moving
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UndefSubregDef.getOperand(0).setIsUndef(false);
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testHandleMove(MF, LIS, 3, 1, 1);
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});
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}
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TEST(LiveIntervalTest, TestMoveSubRegDefAcrossUseDefMulti) {
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liveIntervalTest(R"MIR(
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%1:vreg_96 = IMPLICIT_DEF
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bb.1:
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%2:vgpr_32 = V_MOV_B32_e32 2, implicit $exec
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%3:vgpr_32 = V_ADD_U32_e32 %2, %1.sub0, implicit $exec
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undef %1.sub0:vreg_96 = V_ADD_U32_e32 %2, %2, implicit $exec
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%1.sub1:vreg_96 = COPY %2
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%1.sub2:vreg_96 = COPY %2
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S_NOP 0, implicit %1.sub1, implicit %1.sub2
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S_BRANCH %bb.1
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)MIR", [](MachineFunction &MF, LiveIntervals &LIS) {
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MachineInstr &UndefSubregDef = getMI(MF, 2, 1);
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// The scheduler clears undef from subregister defs before moving
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UndefSubregDef.getOperand(0).setIsUndef(false);
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testHandleMove(MF, LIS, 4, 1, 1);
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});
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}
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int main(int argc, char **argv) {
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::testing::InitGoogleTest(&argc, argv);
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initLLVM();
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