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[X86] Rename matchBitOpReduction to matchScalarReduction. NFCI.

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This doesn't need to be just for bitops, but the ops do need to be fully associative.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375445 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Simon Pilgrim
2019-10-21 19:19:50 +00:00
parent f5e25f84fa
commit b1407138d4
1 changed files with 4 additions and 4 deletions
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8
lib/Target/X86/X86ISelLowering.cpp
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@@ -19891,8 +19891,8 @@ static SDValue getSETCC(X86::CondCode Cond, SDValue EFLAGS, const SDLoc &dl,
/// Helper for matching OR(EXTRACTELT(X,0),OR(EXTRACTELT(X,1),...))
/// style scalarized (associative) reduction patterns.
static bool matchBitOpReduction(SDValue Op, ISD::NodeType BinOp,
SmallVectorImpl<SDValue> &SrcOps) {
static bool matchScalarReduction(SDValue Op, ISD::NodeType BinOp,
SmallVectorImpl<SDValue> &SrcOps) {
SmallVector<SDValue, 8> Opnds;
DenseMap<SDValue, APInt> SrcOpMap;
EVT VT = MVT::Other;
@@ -19965,7 +19965,7 @@ static SDValue LowerVectorAllZeroTest(SDValue Op, ISD::CondCode CC,
return SDValue();
SmallVector<SDValue, 8> VecIns;
if (!matchBitOpReduction(Op, ISD::OR, VecIns))
if (!matchScalarReduction(Op, ISD::OR, VecIns))
return SDValue();
// Quit if not 128/256-bit vector.
@@ -39129,7 +39129,7 @@ static SDValue combineAnd(SDNode *N, SelectionDAG &DAG,
// TODO: Support multiple SrcOps.
if (VT == MVT::i1) {
SmallVector<SDValue, 2> SrcOps;
if (matchBitOpReduction(SDValue(N, 0), ISD::AND, SrcOps) &&
if (matchScalarReduction(SDValue(N, 0), ISD::AND, SrcOps) &&
SrcOps.size() == 1) {
SDLoc dl(N);
unsigned NumElts = SrcOps[0].getValueType().getVectorNumElements();