LLVM-Unit :: Support/./SupportTests/FileSystemTest.permissions currently
FAILs on Solaris:
FAIL: LLVM-Unit :: Support/./SupportTests/FileSystemTest.permissions (2940 of 51555)
******************** TEST 'LLVM-Unit :: Support/./SupportTests/FileSystemTest.permissions' FAILED ********************
Note: Google Test filter = FileSystemTest.permissions
[==========] Running 1 test from 1 test case.
[----------] Global test environment set-up.
[----------] 1 test from FileSystemTest
[ RUN ] FileSystemTest.permissions
/opt/llvm-buildbot/obj/llvm/llvm.src/unittests/Support/Path.cpp:1705: Failure
Value of: CheckPermissions(fs::sticky_bit)
Actual: false
Expected: true
/opt/llvm-buildbot/obj/llvm/llvm.src/unittests/Support/Path.cpp:1712: Failure
Value of: CheckPermissions(fs::set_uid_on_exe | fs::set_gid_on_exe | fs::sticky_bit)
Actual: false
Expected: true
/opt/llvm-buildbot/obj/llvm/llvm.src/unittests/Support/Path.cpp:1719: Failure
Value of: CheckPermissions(fs::all_read | fs::set_uid_on_exe | fs::set_gid_on_exe | fs::sticky_bit)
Actual: false
Expected: true
/opt/llvm-buildbot/obj/llvm/llvm.src/unittests/Support/Path.cpp:1722: Failure
Value of: CheckPermissions(fs::all_perms)
Actual: false
Expected: true
[ FAILED ] FileSystemTest.permissions (0 ms)
[----------] 1 test from FileSystemTest (0 ms total)
[----------] Global test environment tear-down
[==========] 1 test from 1 test case ran. (1 ms total)
[ PASSED ] 0 tests.
[ FAILED ] 1 test, listed below:
[ FAILED ] FileSystemTest.permissions
1 FAILED TEST
Checking with truss reveals that this is the same issue as on AIX and
documented in chmod(2):
If the process is not a privileged process and the file is not a direc-
tory, mode bit 01000 (S_ISVTX, the sticky bit) is cleared.
The following patch fixes this in the same way. Tested on amd64-pc-solaris2.11.
Differential Revision: https://reviews.llvm.org/D63598
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364671 91177308-0d34-0410-b5e6-96231b3b80d8
MVE adds the lsll, lsrl and asrl instructions, which perform a shift on a 64 bit value separated into two 32 bit registers.
The Expand64BitShift function is modified to accept ISD::SHL, ISD::SRL and ISD::SRA and convert it into the appropriate opcode in ARMISD. An SHL is converted into an lsll, an SRL is converted into an lsrl for the immediate form and a negation and lsll for the register form, and SRA is converted into an asrl.
test/CodeGen/ARM/shift_parts.ll is added to test the logic of emitting these instructions.
Differential Revision: https://reviews.llvm.org/D63430
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364654 91177308-0d34-0410-b5e6-96231b3b80d8
We were requiring that both shuffle operands were EXTRACT_SUBVECTORs, but we can relax this to only require one of them to be.
Also, we shouldn't bother attempting this if both operands are from the lowest subvector (or not EXTRACT_SUBVECTOR at all).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364644 91177308-0d34-0410-b5e6-96231b3b80d8
Delete unnecessary getters of AddressRange.
Simplify AddressRange::size(): Start <= End check should be checked in an upper layer.
Delete isContiguousWith() that doesn't make sense.
Simplify AddressRanges::insert. Delete commented code. Fix it when more than 1 ranges are to be deleted.
Delete trailing newline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364637 91177308-0d34-0410-b5e6-96231b3b80d8
MVE has instructions to widen as it loads, and narrow as it stores. This adds
the required patterns and legalisation to make them work including specifying
that they are legal, patterns to select them and test changes.
Patch by David Sherwood.
Differential Revision: https://reviews.llvm.org/D63839
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364636 91177308-0d34-0410-b5e6-96231b3b80d8
This fills in the gaps for basic MVE loads and stores, allowing unaligned
access and adding far too many tests. These will become important as
narrowing/expanding and pre/post inc are added. Big endian might still not be
handled very well, because we have not yet added bitcasts (and I'm not sure how
we want it to work yet). I've included the alignment code anyway which maps
with our current patterns. We plan to return to that later.
Code written by Simon Tatham, with additional tests from Me and Mikhail Maltsev.
Differential Revision: https://reviews.llvm.org/D63838
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364633 91177308-0d34-0410-b5e6-96231b3b80d8
This patch adds necessary shuffle vector and buildvector support for ARM MVE.
It essentially adds support for VDUP, VREVs and some VMOVs, which are often
required by other code (like upcoming patches).
This mostly uses the same code from Neon that already generated
NEONvdup/NEONvduplane/NEONvrev's. These have been renamed to ARMvdup/etc and
moved to ARMInstrInfo as they are common to both architectures. Most of the
selection code seems to be applicable to both, but NEON does have some more
instructions making some parts specific.
Most code originally by David Sherwood.
Differential Revision: https://reviews.llvm.org/D63567
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364626 91177308-0d34-0410-b5e6-96231b3b80d8
Without the fix gcc (7.4.0) complains with
../unittests/ADT/APIntTest.cpp: In member function 'virtual void {anonymous}::APIntTest_MultiplicativeInverseExaustive_Test::TestBody()':
../unittests/ADT/APIntTest.cpp:2510:36: error: comparison between signed and unsigned integer expressions [-Werror=sign-compare]
for (unsigned Value = 0; Value < (1 << BitWidth); ++Value) {
~~~~~~^~~~~~~~~~~~~~~~~
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364624 91177308-0d34-0410-b5e6-96231b3b80d8
Summary: This patch changes fs::setPermissions to optionally set permissions while respecting the umask. It also adds the function fs::getUmask() which returns the current umask.
Reviewers: jhenderson, rupprecht, aprantl, lhames
Reviewed By: jhenderson, rupprecht
Subscribers: sanaanajjar231288, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63583
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364621 91177308-0d34-0410-b5e6-96231b3b80d8
The new switch lowering code that tries to generate jump tables and range checks
were tested at -O0 on arm64, but on -O3 the generic switch lowering code goes to
town on trying to generate optimized lowerings, e.g. multiple jump tables, range
checks etc. This exposed bugs in the way PHI nodes are handled because the CFG
looks even stranger after all of this is done.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364613 91177308-0d34-0410-b5e6-96231b3b80d8
Summary:
Current InlineCost is not assignable because of const members Cost and Threshold.
I dont see practical benefits from having them const (access to these members is
private and internal interactions are rather simple). On other hand that makes
it hard to use as a member in some other data structure where assignability is necessary.
I'm going to use InlineCost in a downstream inliner that maintains a complex queue
of candidate call-sites and thus keeping and recalculating InlineCost is necessary.
This patch just removes 'const' from both members, making InlineCost assignable.
Reviewers: eraman, greened, chandlerc, yrouban, apilipenko
Reviewed By: apilipenko
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63823
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364612 91177308-0d34-0410-b5e6-96231b3b80d8
