Commit Graph

37248 Commits

Author SHA1 Message Date
Fangrui Song
4534bcb33a [DebugInfo] Fix setStartAddress after r364637
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364638 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 10:10:10 +00:00
Fangrui Song
9cd08b6cee [DebugInfo] Simplify GSYM::AddressRange and GSYM::AddressRanges
Delete unnecessary getters of AddressRange.
Simplify AddressRange::size(): Start <= End check should be checked in an upper layer.
Delete isContiguousWith() that doesn't make sense.
Simplify AddressRanges::insert. Delete commented code. Fix it when more than 1 ranges are to be deleted.
Delete trailing newline.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364637 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 10:06:11 +00:00
Fangrui Song
144fab93ff [DebugInfo] GSYM cleanups after D63104/r364427
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364634 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 08:58:05 +00:00
Sam Parker
6189e4972d [HardwareLoops] Loop counter guard intrinsic
Introduce llvm.test.set.loop.iterations which sets the loop counter
and also produces an i1 after testing that the count is not zero.

Differential Revision: https://reviews.llvm.org/D63809


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364628 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 07:38:16 +00:00
Alex Brachet
4a8cbaa1de [Support] Add fs::getUmask() function and change fs::setPermissions
Summary: This patch changes fs::setPermissions to optionally set permissions while respecting the umask. It also adds the function fs::getUmask() which returns the current umask.

Reviewers: jhenderson, rupprecht, aprantl, lhames

Reviewed By: jhenderson, rupprecht

Subscribers: sanaanajjar231288, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63583

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364621 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 03:21:00 +00:00
Matt Arsenault
cc1390c334 GlobalISel: Use Register
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364618 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 01:47:44 +00:00
Matt Arsenault
5564ced645 GlobalISel: Convert rest of MachineIRBuilder to using Register
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364615 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 01:16:41 +00:00
Amara Emerson
b9f4ed6752 [GlobalISel][IRTranslator] Fix some PHI bugs related to jump tables when optimizations are used.
The new switch lowering code that tries to generate jump tables and range checks
were tested at -O0 on arm64, but on -O3 the generic switch lowering code goes to
town on trying to generate optimized lowerings, e.g. multiple jump tables, range
checks etc. This exposed bugs in the way PHI nodes are handled because the CFG
looks even stranger after all of this is done.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364613 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-27 23:56:34 +00:00
Fedor Sergeev
a7789c6bb3 [InlineCost] make InlineCost assignable
Summary:
Current InlineCost is not assignable because of const members Cost and Threshold.
I dont see practical benefits from having them const (access to these members is
private and internal interactions are rather simple). On other hand that makes
it hard to use as a member in some other data structure where assignability is necessary.

I'm going to use InlineCost in a downstream inliner that maintains a complex queue
of candidate call-sites and thus keeping and recalculating InlineCost is necessary.

This patch just removes 'const' from both members, making InlineCost assignable.

Reviewers: eraman, greened, chandlerc, yrouban, apilipenko
Reviewed By: apilipenko
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63823

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364612 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-27 23:41:03 +00:00
Roman Lebedev
65afd3a0fd [CodeGen] [SelectionDAG] More efficient code for X % C == 0 (UREM case) (try 3)
Summary:
I'm submitting a new revision since i don't understand how to reclaim/reopen/take over the existing one, D50222.
There is no such action in "Add Action" menu...

This implements an optimization described in Hacker's Delight 10-17: when `C` is constant,
the result of `X % C == 0` can be computed more cheaply without actually calculating the remainder.
The motivation is discussed here: https://bugs.llvm.org/show_bug.cgi?id=35479.

This is a recommit, the original commit rL364563 was reverted in rL364568
because test-suite detected miscompile - the new comparison constant 'Q'
was being computed incorrectly (we divided by `D0` instead of `D`).

Original patch D50222 by @hermord (Dmytro Shynkevych)

Notes:
- In principle, it's possible to also handle the `X % C1 == C2` case, as discussed on bugzilla.
  This seems to require an extra branch on overflow, so I refrained from implementing this for now.
- An explicit check for when the `REM` can be reduced to just its LHS is included:
  the `X % C` == 0 optimization breaks `test1` in `test/CodeGen/X86/jump_sign.ll` otherwise.
  I hadn't managed to find a better way to not generate worse output in this case.
- The `test/CodeGen/X86/jump_sign.ll` regresses, and is being fixed by a followup patch D63390.

Reviewers: RKSimon, craig.topper, spatel, hermord, xbolva00

Reviewed By: RKSimon, xbolva00

Subscribers: dexonsmith, kristina, xbolva00, javed.absar, llvm-commits, hermord

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63391

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364600 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-27 21:52:10 +00:00
Alexandre Ganea
891342a33f Convert line endings to LF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364590 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-27 20:46:11 +00:00
Roman Lebedev
1df452bb5a Revert "[CodeGen] [SelectionDAG] More efficient code for X % C == 0 (UREM case) (try 2)"
*Appears* to break test-suite on
http://lab.llvm.org:8011/builders/clang-cmake-x86_64-sde-avx512-linux/builds/23790

FAIL: burg.execution_time
FAIL: spiff.execution_time
FAIL: employ.execution_time
FAIL: llu.execution_time
FAIL: gramschmidt.execution_time
FAIL: fdtd-apml.execution_time

This reverts commit r364563.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364568 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-27 17:22:31 +00:00
Roman Lebedev
84139109d4 [CodeGen] [SelectionDAG] More efficient code for X % C == 0 (UREM case) (try 2)
Summary:
I'm submitting a new revision since i don't understand how to reclaim/reopen/take over the existing one, D50222.
There is no such action in "Add Action" menu...
Original patch D50222 by @hermord (Dmytro Shynkevych)

This implements an optimization described in Hacker's Delight 10-17: when `C` is constant,
the result of `X % C == 0` can be computed more cheaply without actually calculating the remainder.
The motivation is discussed here: https://bugs.llvm.org/show_bug.cgi?id=35479.

Original patch author: @hermord (Dmytro Shynkevych)!

Notes:
- In principle, it's possible to also handle the `X % C1 == C2` case, as discussed on bugzilla.
  This seems to require an extra branch on overflow, so I refrained from implementing this for now.
- An explicit check for when the `REM` can be reduced to just its LHS is included:
  the `X % C` == 0 optimization breaks `test1` in `test/CodeGen/X86/jump_sign.ll` otherwise.
  I hadn't managed to find a better way to not generate worse output in this case.
- The `test/CodeGen/X86/jump_sign.ll` regresses, and is being fixed by a followup patch D63390.

Reviewers: RKSimon, craig.topper, spatel, hermord, xbolva00

Reviewed By: RKSimon, xbolva00

Subscribers: xbolva00, javed.absar, llvm-commits, hermord

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63391

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364563 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-27 16:45:42 +00:00
Johannes Doerfert
8a0fc5ba4f [Attr] Add "willreturn" function attribute
This patch introduces a new function attribute, willreturn, to indicate
that a call of this function will either exhibit undefined behavior or
comes back and continues execution at a point in the existing call stack
that includes the current invocation.

This attribute guarantees that the function does not have any endless
loops, endless recursion, or terminating functions like abort or exit.

Patch by Hideto Ueno (@uenoku)

Reviewers: jdoerfert

Subscribers: mehdi_amini, hiraditya, steven_wu, dexonsmith, lebedev.ri, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D62801

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364555 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-27 15:51:40 +00:00
Hans Wennborg
a1a5ec67ec Revert r363658 "[SVE][IR] Scalable Vector IR Type with pr42210 fix"
We saw a 70% ThinLTO link time increase in Chromium for Android, see
crbug.com/978817. Sounds like more of PR42210.

> Recommit of D32530 with a few small changes:
>   - Stopped recursively walking through aggregates in
>     the verifier, so that we don't impose too much
>     overhead on large modules under LTO (see PR42210).
>   - Changed tests to match; the errors are slightly
>     different since they only report the array or
>     struct that actually contains a scalable vector,
>     rather than all aggregates which contain one in
>     a nested member.
>   - Corrected an older comment
>
> Reviewers: thakis, rengolin, sdesmalen
>
> Reviewed By: sdesmalen
>
> Differential Revision: https://reviews.llvm.org/D63321

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364543 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-27 13:55:02 +00:00
Djordje Todorovic
192906bcfd [DWARF] Handle the DW_OP_entry_value operand
Add the IR and the AsmPrinter parts for handling of the DW_OP_entry_values
DWARF operation.

([11/13] Introduce the debug entry values.)

Co-authored-by: Ananth Sowda <asowda@cisco.com>
Co-authored-by: Nikola Prica <nikola.prica@rt-rk.com>
Co-authored-by: Ivan Baev <ibaev@cisco.com>

Differential Revision: https://reviews.llvm.org/D60866

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364542 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-27 13:52:34 +00:00
Djordje Todorovic
856ec6e1b0 [Backend] Keep call site info valid through the backend
Handle call instruction replacements and deletions in order to preserve
valid state of the call site info of the MachineFunction.

NOTE: If the call site info is enabled for a new target, the assertion from
the MachineFunction::DeleteMachineInstr() should help to locate places
where the updateCallSiteInfo() should be called in order to preserve valid
state of the call site info.

([10/13] Introduce the debug entry values.)

Co-authored-by: Ananth Sowda <asowda@cisco.com>
Co-authored-by: Nikola Prica <nikola.prica@rt-rk.com>
Co-authored-by: Ivan Baev <ibaev@cisco.com>

Differential Revision: https://reviews.llvm.org/D61062

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364536 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-27 13:10:29 +00:00
Stefan Stipanovic
ffa5500e3a [Attributor] Deducing existing nounwind attribute.
Adding nounwind deduction in new attributor framework.

Reviewers: jdoerfert, uenoku

Subscribers: hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D63379

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364521 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-27 11:27:54 +00:00
George Rimar
2cb558589f [yaml2obj] - Allow overriding e_shentsize, e_shoff, e_shnum and e_shstrndx fields in the YAML.
This allows setting different values for e_shentsize, e_shoff, e_shnum
and e_shstrndx fields and is useful for producing broken inputs for various
test cases.

Differential revision: https://reviews.llvm.org/D63771

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364517 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-27 11:08:42 +00:00
Djordje Todorovic
e02e5c6f21 [ISEL][X86] Tracking of registers that forward call arguments
While lowering calls, collect info about registers that forward arguments
into following function frame. We store such info into the MachineFunction
of the call. This is used very late when dumping DWARF info about
call site parameters.

([9/13] Introduce the debug entry values.)

Co-authored-by: Ananth Sowda <asowda@cisco.com>
Co-authored-by: Nikola Prica <nikola.prica@rt-rk.com>
Co-authored-by: Ivan Baev <ibaev@cisco.com>

Differential Revision: https://reviews.llvm.org/D60715

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364516 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-27 10:51:15 +00:00
Diana Picus
419fa631cd [GlobalISel] Remove [un]packRegs from IRTranslator
Remove the last use of packRegs from IRTranslator and delete
pack/unpackRegs. This introduces a fallback to DAGISel for intrinsics
with aggregate arguments, since we don't have a testcase for them so
it's hard to tell how we'd want to handle them.

Discussed in https://reviews.llvm.org/D63551

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364514 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-27 09:49:07 +00:00
Diana Picus
65c682330e [GlobalISel] Accept multiple vregs for lowerCall's args
Change the interface of CallLowering::lowerCall to accept several
virtual registers for each argument, instead of just one.  This is a
follow-up to D46018.

CallLowering::lowerReturn was similarly refactored in D49660 and
lowerFormalArguments in D63549.

With this change, we no longer pack the virtual registers generated for
aggregates into one big lump before delegating to the target. Therefore,
the target can decide itself whether it wants to handle them as separate
pieces or use one big register.

ARM and AArch64 have been updated to use the passed in virtual registers
directly, which means we no longer need to generate so many
merge/extract instructions.

NFCI for AMDGPU, Mips and X86.

Differential Revision: https://reviews.llvm.org/D63551

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364512 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-27 09:18:03 +00:00
Diana Picus
d3b26382a9 [GlobalISel] Accept multiple vregs for lowerCall's result
Change the interface of CallLowering::lowerCall to accept several
virtual registers for the call result, instead of just one.  This is a
follow-up to D46018.

CallLowering::lowerReturn was similarly refactored in D49660 and
lowerFormalArguments in D63549.

With this change, we no longer pack the virtual registers generated for
aggregates into one big lump before delegating to the target. Therefore,
the target can decide itself whether it wants to handle them as separate
pieces or use one big register.

ARM and AArch64 have been updated to use the passed in virtual registers
directly, which means we no longer need to generate so many
merge/extract instructions.

NFCI for AMDGPU, Mips and X86.

Differential Revision: https://reviews.llvm.org/D63550

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364511 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-27 09:15:53 +00:00
Diana Picus
4776c1ff97 [GlobalISel] Accept multiple vregs in lowerFormalArgs
Change the interface of CallLowering::lowerFormalArguments to accept
several virtual registers for each formal argument, instead of just one.
This is a follow-up to D46018.

CallLowering::lowerReturn was similarly refactored in D49660. lowerCall
will be refactored in the same way in follow-up patches.

With this change, we forward the virtual registers generated for
aggregates to CallLowering. Therefore, the target can decide itself
whether it wants to handle them as separate pieces or use one big
register. We also copy the pack/unpackRegs helpers to CallLowering to
facilitate this.

ARM and AArch64 have been updated to use the passed in virtual registers
directly, which means we no longer need to generate so many
merge/extract instructions.

AArch64 seems to have had a bug when lowering e.g. [1 x i8*], which was
put into a s64 instead of a p0. Added a test-case which illustrates the
problem more clearly (it crashes without this patch) and fixed the
existing test-case to expect p0.

AMDGPU has been updated to unpack into the virtual registers for
kernels. I think the other code paths fall back for aggregates, so this
should be NFC.

Mips doesn't support aggregates yet, so it's also NFC.

x86 seems to have code for dealing with aggregates, but I couldn't find
the tests for it, so I just added a fallback to DAGISel if we get more
than one virtual register for an argument.

Differential Revision: https://reviews.llvm.org/D63549

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364510 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-27 08:54:17 +00:00
Diana Picus
43a431faf5 [GlobalISel] Allow multiple VRegs in ArgInfo. NFC
Allow CallLowering::ArgInfo to contain more than one virtual register.
This is useful when passes split aggregates into several virtual
registers, but need to also provide information about the original type
to the call lowering. Used in follow-up patches.

Differential Revision: https://reviews.llvm.org/D63548

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364509 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-27 08:50:53 +00:00
Djordje Todorovic
3aa859711c [MachineFunction] Base support for call site info tracking
Add an attribute into the MachineFunction that tracks call site info.

([8/13] Introduce the debug entry values.)

Co-authored-by: Ananth Sowda <asowda@cisco.com>
Co-authored-by: Nikola Prica <nikola.prica@rt-rk.com>
Co-authored-by: Ivan Baev <ibaev@cisco.com>

Differential Revision: https://reviews.llvm.org/D61061

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364506 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-27 07:48:06 +00:00
Hans Wennborg
9e71fe14b1 Fix GCC 4 build after r364464
It was failing with:

In file included from /b/s/w/ir/cache/builder/src/third_party/llvm/llvm/lib/Bitcode/Reader/BitstreamReader.cpp:9:0:
/b/s/w/ir/cache/builder/src/third_party/llvm/llvm/include/llvm/Bitcode/BitstreamReader.h:
In member function 'llvm::Expected<long unsigned int> llvm::SimpleBitstreamCursor::ReadVBR64(unsigned int)':
/b/s/w/ir/cache/builder/src/third_party/llvm/llvm/include/llvm/Bitcode/BitstreamReader.h:262:14:
error: could not convert 'MaybeRead' from 'llvm::Expected<unsigned int>' to 'llvm::Expected<long unsigned int>'
       return MaybeRead;
              ^
/b/s/w/ir/cache/builder/src/third_party/llvm/llvm/include/llvm/Bitcode/BitstreamReader.h:279:16:
error: could not convert 'MaybeRead' from 'llvm::Expected<unsigned int>' to 'llvm::Expected<long unsigned int>'
         return MaybeRead;
                ^

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364504 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-27 07:32:10 +00:00
JF Bastien
22d9c5c34d BitStream reader: propagate errors
The bitstream reader handles errors poorly. This has two effects:

 * Bugs in file handling (especially modules) manifest as an "unexpected end of
   file" crash
 * Users of clang as a library end up aborting because the code unconditionally
   calls `report_fatal_error`

The bitstream reader should be more resilient and return Expected / Error as
soon as an error is encountered, not way late like it does now. This patch
starts doing so and adopting the error handling where I think it makes sense.
There's plenty more to do: this patch propagates errors to be minimally useful,
and follow-ups will propagate them further and improve diagnostics.

https://bugs.llvm.org/show_bug.cgi?id=42311
<rdar://problem/33159405>

Differential Revision: https://reviews.llvm.org/D63518

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364464 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-26 19:50:12 +00:00
David Blaikie
6a4aee34a9 Fix some undefined behavior (excessive shift of signed value) in r364253 detected by ubsan
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364461 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-26 19:18:50 +00:00
Simon Pilgrim
730742c930 Fix Wdocumentation warnings. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364459 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-26 18:53:24 +00:00
Nico Weber
4a77e2a0fc Make AddLastArg() variadic and use it more. No behavior change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364453 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-26 17:51:47 +00:00
Ulrich Weigand
3f58e45931 Allow matching extend-from-memory with strict FP nodes
This implements a small enhancement to https://reviews.llvm.org/D55506

Specifically, while we were able to match strict FP nodes for
floating-point extend operations with a register as source, this
did not work for operations with memory as source.

That is because from regular operations, this is represented as
a combined "extload" node (which is a variant of a load SD node);
but there is no equivalent using a strict FP operation.

However, it turns out that even in the absence of an extload
node, we can still just match the operations explicitly, e.g.
   (strict_fpextend (f32 (load node:$ptr))

This patch implements that method to match the LDEB/LXEB/LXDB
SystemZ instructions even when the extend uses a strict-FP node.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364450 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-26 17:19:12 +00:00
Greg Clayton
4871614dcf Add GSYM utility files along with unit tests.
The full GSYM patch started with: https://reviews.llvm.org/D53379

In that patch we wanted to split up getting GSYM into the LLVM code base so we are not committing too much code at once.

This is a first in a series of patches where I only add the foundation classes along with complete unit tests. They provide the foundation for encoding and decoding a GSYM file.

File entries are defined in llvm::gsym::FileEntry. This class splits the file up into a directory and filename represented by uniqued string table offsets. This allows all files that are referred to in a GSYM file to be encoded as 1 based indexes into a global file table in the GSYM file.

Function information in stored in llvm::gsym::FunctionInfo. This object represents a contiguous address range that has a name and range with an optional line table and inline call stack information.

Line table entries are defined in llvm::gsym::LineEntry. They store only address, file and line information to keep the line tables simple and allows the information to be efficiently encoded in a subsequent patch.

Inline information is defined in llvm::gsym::InlineInfo. These structs store the name of the inline function, along with one or more address ranges, and the file and line that called this function. They also contain any child inline information.

There are also utility classes for address ranges in llvm::gsym::AddressRange, and string table support in llvm::gsym::StringTable which are simple classes.

The unit tests test all the APIs on these simple classes so they will be ready for the next patches where we will create GSYM files and parse GSYM files.

Differential Revision: https://reviews.llvm.org/D63104




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364427 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-26 14:09:09 +00:00
Roman Lebedev
a698111256 [X86] X86DAGToDAGISel::matchBitExtract(): pattern b: truncation awareness
Summary:
(Not so) boringly identical to pattern a (D62786)
Not yet sure how do deal with the last pattern c.

Reviewers: RKSimon, craig.topper, spatel

Reviewed By: RKSimon

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D62793

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364418 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-26 12:19:39 +00:00
Clement Courbet
6f6d98e186 Revert "r364412 [ExpandMemCmp][MergeICmps] Move passes out of CodeGen into opt pipeline."
Breaks sanitizers:
    libFuzzer :: cxxstring.test
    libFuzzer :: memcmp.test
    libFuzzer :: recommended-dictionary.test
    libFuzzer :: strcmp.test
    libFuzzer :: value-profile-mem.test
    libFuzzer :: value-profile-strcmp.test

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364416 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-26 12:13:13 +00:00
Chen Zheng
3a6c5d72b9 [HardwareLoops] NFC - move loop with irreducible control flow checking logic to HarewareLoopInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364415 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-26 12:02:43 +00:00
Clement Courbet
e0fc543f4c [ExpandMemCmp][MergeICmps] Move passes out of CodeGen into opt pipeline.
This allows later passes (in particular InstCombine) to optimize more
cases.

One that's important to us is `memcmp(p, q, constant) < 0` and memcmp(p, q, constant) > 0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364412 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-26 11:50:18 +00:00
Djordje Todorovic
9eaa8818a5 [IR/DIVar] Add the flag for params that have unmodified value
Introduce the debug info flag that indicates that a parameter has unchanged
value throughout a function. This info will be used to emit the expressions
with DW_OP_entry_value.

([4/13] Introduce the debug entry values.)

Co-authored-by: Ananth Sowda <asowda@cisco.com>
Co-authored-by: Nikola Prica <nikola.prica@rt-rk.com>
Co-authored-by: Ivan Baev <ibaev@cisco.com>

Differential Revision: https://reviews.llvm.org/D58034

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364406 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-26 11:19:26 +00:00
Chen Zheng
5bd39d6f6e [HardwareLoops] NFC - move loop with irreducible control flow checking logic to isHardwareLoopProfitable()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364397 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-26 09:12:52 +00:00
Djordje Todorovic
2ba7e80886 [TargetOption] Add option to ebanble the debug entry values
The option enables debug info about parameter's entry values.

([2/13] Introduce the debug entry values.)

Co-authored-by: Ananth Sowda <asowda@cisco.com>
Co-authored-by: Nikola Prica <nikola.prica@rt-rk.com>
Co-authored-by: Ivan Baev <ibaev@cisco.com>

Differential Revision: https://reviews.llvm.org/D60961

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364395 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-26 08:35:43 +00:00
Djordje Todorovic
4ba5b90239 [Metadata] Add GNU extensions for call site DWARF symbols
As discussed on RFC
(http://lists.llvm.org/pipermail/llvm-dev/2019-February/130094.html), this
is set of patches that introduces debug information about call site and
call site parameters. Since the LLVM has portion of this support (dumping
DWARF 5 symbols for calls), we generate GNU extensions as well. All of that
will be restricted under an option.

([1/13] Introduce the debug entry values.)

Co-authored-by: Ananth Sowda <asowda@cisco.com>
Co-authored-by: Nikola Prica <nikola.prica@rt-rk.com>
Co-authored-by: Ivan Baev <ibaev@cisco.com>

Differential Revision: https://reviews.llvm.org/D60712

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364385 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-26 07:31:09 +00:00
Keno Fischer
6a559cdf84 [WebAssembly] Fix list of relocations with addends in lld
Summary:
The list of relocations with addend in lld was missing `R_WASM_MEMORY_ADDR_REL_SLEB`,
causing `wasm-ld` to generate corrupted output. This fixes that problem and while
we're at it pulls the list of such relocations into the Wasm.h header, to avoid
duplicating it in multiple places.

Reviewers: sbc100
Differential Revision: https://reviews.llvm.org/D63696

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364367 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-26 00:52:42 +00:00
Philip Reames
7e88372346 [Peephole] Allow folding loads into instructions w/multiple uses (such as test64rr)
Peephole opt has a one use limitation which appears to be accidental. The function being used was incorrectly documented as returning whether the def had one *user*, but instead returned true only when there was one *use*. Add a corresponding hasOneNonDbgUser helper, and adjust peephole-opt to use the appropriate one.

All of the actual folding code handles multiple uses within a single instruction. That codepath is well exercised through instruction selection.

Differential Revision: https://reviews.llvm.org/D63656



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364336 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-25 17:29:18 +00:00
Xing Xue
50650dce81 Improve zero-size allocation with safe_malloc, etc.
Summary:
The current implementations of the memory allocation functions mistake a nullptr returned from std::malloc, std::calloc, or std::realloc as a failure. The behaviour for each of std::malloc, std::calloc, and std::realloc when the size is 0 is implementation defined (ISO/IEC 9899:2018 7.22.3), and may return a nullptr.

This patch checks if space requested is zero when a nullptr is returned, retry requesting non-zero if it is.

Authored By: andusy

Reviewers: hubert.reinterpretcast, xingxue, jasonliu

Reviewed By: hubert.reinterpretcast, xingxue, abrachet

Subscribers: abrachet, jsji, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63668

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364322 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-25 15:08:28 +00:00
Whitney Tsang
93f99745ce Expand cloneLoopWithPreheader() to support cloning loop nest
Summary: cloneLoopWithPreheader() currently only support innermost loop,
and assert otherwise.
Reviewers: Meinersbur, fhahn, kbarton
Reviewed By: Meinersbur
Subscribers: hiraditya, jsji, llvm-commits
Tag: LLVM
Differential Revision: https://reviews.llvm.org/D63446

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364310 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-25 13:23:13 +00:00
Matt Arsenault
2d01698b04 AMDGPU: Make amdgcn.s.get.waveid.in.workgroup inaccessiblememonly
This should probably be readnone, even though the instruction looks
like a load.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364304 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-25 13:03:06 +00:00
Nicolai Haehnle
f1a1a392db AMDGPU/MC: Add .amdgpu_lds directive
Summary:
The directive defines a symbol as an group/local memory (LDS) symbol.
LDS symbols behave similar to common symbols for the purposes of ELF,
using the processor-specific SHN_AMDGPU_LDS as section index.

It is the linker and/or runtime loader's job to "instantiate" LDS symbols
and resolve relocations that reference them.

It is not possible to initialize LDS memory (not even zero-initialize
as for .bss).

We want to be able to link together objects -- starting with relocatable
objects, but possible expanding to shared objects in the future -- that
access LDS memory in a flexible way.

LDS memory is in an address space that is entirely separate from the
address space that contains the program image (code and normal data),
so having program segments for it doesn't really make sense.

Furthermore, we want to be able to compile multiple kernels in a
compilation unit which have disjoint use of LDS memory. In that case,
we may want to place LDS symbols differently for different kernels
to save memory (LDS memory is very limited and physically private to
each kernel invocation), so we can't simply place LDS symbols in a
.lds section.

Hence this solution where LDS symbols always stay undefined.

Change-Id: I08cbc37a7c0c32f53f7b6123aa0afc91dbc1748f

Reviewers: arsenm, rampitec, t-tye, b-sumner, jsjodin

Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, rupprecht, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D61493

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364296 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-25 11:51:35 +00:00
Clement Courbet
6ef46a770d [ExpandMemCmp] Move all options to TargetTransformInfo.
Split off from D60318.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364281 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-25 08:04:13 +00:00
David Blaikie
ea1783464b DataExtractor: use decodeSLEB128 to implement getSLEB128
Should've been NFC, but turns out DataExtractor had better test coverage
for decoding SLEB128 than the decodeSLEB128 did - revealing a couple of
bugs (one in the error handling, another in sign extension). So fixed
those to get the DataExtractor tests passing again.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364253 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-24 23:45:18 +00:00
Tim Shen
1342f43ec9 Revert "[NVPTX][NFC] Fix documentation for shfl instructions." The
original documentation is correct as it matches the C++ builtins.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364250 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-24 23:29:20 +00:00