Commit Graph

124259 Commits

Author SHA1 Message Date
Simon Pilgrim
08a4b34e50 [X86] CombineShuffleWithExtract - recurse through EXTRACT_SUBVECTOR chain
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364667 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 17:57:32 +00:00
Peter Collingbourne
9e1d739445 hwasan: Remove the old frame descriptor mechanism.
Differential Revision: https://reviews.llvm.org/D63470

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364665 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 17:53:26 +00:00
Wouter van Oortmerssen
a8ce5edb5c [WebAssembly] Added visibility and ident directives to WasmAsmParser.
Summary:
These are output by clang -S, so can now be roundtripped thru clang.

(partially) fixes: https://bugs.llvm.org/show_bug.cgi?id=34544

Reviewers: dschuff

Subscribers: sbc100, jgravelle-google, aheejin, sunfish, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63901

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364658 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 16:51:06 +00:00
Dmitry Preobrazhensky
539c69ef52 [AMDGPU][MC] Fix 2 for sanitizer failure in 364645
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364656 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 16:28:46 +00:00
Sam Tebbs
a71ac42554 [ARM] Add support for the MVE long shift instructions
MVE adds the lsll, lsrl and asrl instructions, which perform a shift on a 64 bit value separated into two 32 bit registers.

The Expand64BitShift function is modified to accept ISD::SHL, ISD::SRL and ISD::SRA and convert it into the appropriate opcode in ARMISD. An SHL is converted into an lsll, an SRL is converted into an lsrl for the immediate form and a negation and lsll for the register form, and SRA is converted into an asrl.

test/CodeGen/ARM/shift_parts.ll is added to test the logic of emitting these instructions.

Differential Revision: https://reviews.llvm.org/D63430

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364654 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 15:43:31 +00:00
Dmitry Preobrazhensky
c8753f157b [AMDGPU][MC] Fix for sanitizer failure in 364645
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364651 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 15:22:47 +00:00
Dmitry Preobrazhensky
3c357a49a3 [AMDGPU][MC] Enabled constant expressions as operands of sendmsg
See bug 40820: https://bugs.llvm.org/show_bug.cgi?id=40820

Reviewers: artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D62735

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364645 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 14:14:02 +00:00
Simon Pilgrim
ef0e051c6d [X86] CombineShuffleWithExtract - only require 1 source to be EXTRACT_SUBVECTOR
We were requiring that both shuffle operands were EXTRACT_SUBVECTORs, but we can relax this to only require one of them to be.

Also, we shouldn't bother attempting this if both operands are from the lowest subvector (or not EXTRACT_SUBVECTOR at all).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364644 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 12:24:49 +00:00
David Green
5f0953343c [ARM] Add MVE mul patterns
This simply adds integer and floating point VMUL patterns for MVE, same as we
have add and sub.

Differential Revision: https://reviews.llvm.org/D63866


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364643 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 11:44:03 +00:00
David Green
2dd6a9d6de [ARM] Mark math routines as non-legal for MVE
This adds handling and tests for a number of floating point math routines,
which have no MVE instructions.

Differential Revision: https://reviews.llvm.org/D63725


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364641 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 11:17:38 +00:00
David Green
4cbe79049c [ARM] MVE patterns for VABS and VNEG
This simply adds the required patterns for fp neg and abs.

Differential Revision: https://reviews.llvm.org/D63861


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364640 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 10:25:35 +00:00
Fangrui Song
9cd08b6cee [DebugInfo] Simplify GSYM::AddressRange and GSYM::AddressRanges
Delete unnecessary getters of AddressRange.
Simplify AddressRange::size(): Start <= End check should be checked in an upper layer.
Delete isContiguousWith() that doesn't make sense.
Simplify AddressRanges::insert. Delete commented code. Fix it when more than 1 ranges are to be deleted.
Delete trailing newline.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364637 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 10:06:11 +00:00
David Green
0272917d5a [ARM] Widening loads and narrowing stores
MVE has instructions to widen as it loads, and narrow as it stores. This adds
the required patterns and legalisation to make them work including specifying
that they are legal, patterns to select them and test changes.

Patch by David Sherwood.

Differential Revision: https://reviews.llvm.org/D63839


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364636 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 09:47:55 +00:00
Simon Tatham
4f77b3ddf3 [ARM] Fix integer UB in MVE load/store immediate handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364635 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 09:28:39 +00:00
Fangrui Song
144fab93ff [DebugInfo] GSYM cleanups after D63104/r364427
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364634 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 08:58:05 +00:00
David Green
c2c9f7413e [ARM] MVE loads and stores
This fills in the gaps for basic MVE loads and stores, allowing unaligned
access and adding far too many tests. These will become important as
narrowing/expanding and pre/post inc are added. Big endian might still not be
handled very well, because we have not yet added bitcasts (and I'm not sure how
we want it to work yet). I've included the alignment code anyway which maps
with our current patterns. We plan to return to that later.

Code written by Simon Tatham, with additional tests from Me and Mikhail Maltsev.

Differential Revision: https://reviews.llvm.org/D63838


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364633 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 08:41:40 +00:00
Dylan McKay
54003d0c08 [AVR] Don't look for the TargetFrameLowering in the FrameLowering implementation
c.f. r364349

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364632 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 08:35:21 +00:00
David Green
67091fc7e1 [ARM] Mark div and rem as expand for MVE
We don't have vector operations for these, so they need to be expanded for both
integer and float.

Differential Revision: https://reviews.llvm.org/D63595


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364631 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 08:18:55 +00:00
David Green
03b8387d14 [ARM] Select MVE fp add and sub
The same as integer arithmetic, we can add simple floating point MVE addition and
subtraction patterns.

Initial code by David Sherwood

Differential Revision: https://reviews.llvm.org/D63257


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364629 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 07:41:09 +00:00
Sam Parker
6189e4972d [HardwareLoops] Loop counter guard intrinsic
Introduce llvm.test.set.loop.iterations which sets the loop counter
and also produces an i1 after testing that the count is not zero.

Differential Revision: https://reviews.llvm.org/D63809


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364628 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 07:38:16 +00:00
David Green
93744b32bb [ARM] Select MVE add and sub
This adds the first few patterns for MVE code generation, adding simple integer
add and sub patterns.

Initial code by David Sherwood

Differential Revision: https://reviews.llvm.org/D63255


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364627 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 07:21:11 +00:00
David Green
3b9e91d904 [ARM] MVE vector shuffles
This patch adds necessary shuffle vector and buildvector support for ARM MVE.
It essentially adds support for VDUP, VREVs and some VMOVs, which are often
required by other code (like upcoming patches).

This mostly uses the same code from Neon that already generated
NEONvdup/NEONvduplane/NEONvrev's. These have been renamed to ARMvdup/etc and
moved to ARMInstrInfo as they are common to both architectures. Most of the
selection code seems to be applicable to both, but NEON does have some more
instructions making some parts specific.

Most code originally by David Sherwood.

Differential Revision: https://reviews.llvm.org/D63567


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364626 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 07:08:42 +00:00
Craig Topper
5dcd620f4b [X86] Connect the output chain properly when combining vzext_movl+load into vzext_load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364625 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 06:58:50 +00:00
Craig Topper
90bbc45f62 [X86] Remove some duplicate patterns that already exist as part of their instruction definition. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364623 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 05:03:47 +00:00
Alex Brachet
4a8cbaa1de [Support] Add fs::getUmask() function and change fs::setPermissions
Summary: This patch changes fs::setPermissions to optionally set permissions while respecting the umask. It also adds the function fs::getUmask() which returns the current umask.

Reviewers: jhenderson, rupprecht, aprantl, lhames

Reviewed By: jhenderson, rupprecht

Subscribers: sanaanajjar231288, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63583

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364621 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 03:21:00 +00:00
Zi Xuan Wu
8a35ae4e3b [NFC][PowerPC] Move XS*QP series instruction apart from XS*QPO series in position of td file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364620 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 02:51:03 +00:00
Stanislav Mekhanoshin
41e9ec03c7 [AMDGPU] Packed thread ids in function call ABI
Differential Revision: https://reviews.llvm.org/D63851

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364619 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 01:52:13 +00:00
Matt Arsenault
cc1390c334 GlobalISel: Use Register
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364618 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 01:47:44 +00:00
Kai Luo
6408bc58aa [PowerPC][NFC] Use |= to update Simplified flag
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364617 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 01:38:42 +00:00
Matt Arsenault
30321492f6 AMDGPU/GlobalISel: Convert to using Register
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364616 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 01:16:46 +00:00
Matt Arsenault
5564ced645 GlobalISel: Convert rest of MachineIRBuilder to using Register
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364615 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 01:16:41 +00:00
Amara Emerson
b9f4ed6752 [GlobalISel][IRTranslator] Fix some PHI bugs related to jump tables when optimizations are used.
The new switch lowering code that tries to generate jump tables and range checks
were tested at -O0 on arm64, but on -O3 the generic switch lowering code goes to
town on trying to generate optimized lowerings, e.g. multiple jump tables, range
checks etc. This exposed bugs in the way PHI nodes are handled because the CFG
looks even stranger after all of this is done.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364613 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-27 23:56:34 +00:00
Rumeet Dhindsa
cf66538c75 Fix ASAN error caused by commit r364512.
This patch intends to fix ASAN stack-use-after-scope error.
This is at least a short-term fix to unbreak LLVM's mainline.

Differential Revision: https://reviews.llvm.org/D63905

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364611 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-27 23:37:04 +00:00
Peter Collingbourne
405de2bdbd hwasan: Use llvm.read_register intrinsic to read the PC on aarch64 instead of taking the function's address.
This shaves an instruction (and a GOT entry in PIC code) off prologues of
functions with stack variables.

Differential Revision: https://reviews.llvm.org/D63472

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364608 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-27 23:24:07 +00:00
Roman Lebedev
65afd3a0fd [CodeGen] [SelectionDAG] More efficient code for X % C == 0 (UREM case) (try 3)
Summary:
I'm submitting a new revision since i don't understand how to reclaim/reopen/take over the existing one, D50222.
There is no such action in "Add Action" menu...

This implements an optimization described in Hacker's Delight 10-17: when `C` is constant,
the result of `X % C == 0` can be computed more cheaply without actually calculating the remainder.
The motivation is discussed here: https://bugs.llvm.org/show_bug.cgi?id=35479.

This is a recommit, the original commit rL364563 was reverted in rL364568
because test-suite detected miscompile - the new comparison constant 'Q'
was being computed incorrectly (we divided by `D0` instead of `D`).

Original patch D50222 by @hermord (Dmytro Shynkevych)

Notes:
- In principle, it's possible to also handle the `X % C1 == C2` case, as discussed on bugzilla.
  This seems to require an extra branch on overflow, so I refrained from implementing this for now.
- An explicit check for when the `REM` can be reduced to just its LHS is included:
  the `X % C` == 0 optimization breaks `test1` in `test/CodeGen/X86/jump_sign.ll` otherwise.
  I hadn't managed to find a better way to not generate worse output in this case.
- The `test/CodeGen/X86/jump_sign.ll` regresses, and is being fixed by a followup patch D63390.

Reviewers: RKSimon, craig.topper, spatel, hermord, xbolva00

Reviewed By: RKSimon, xbolva00

Subscribers: dexonsmith, kristina, xbolva00, javed.absar, llvm-commits, hermord

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63391

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364600 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-27 21:52:10 +00:00
Cameron McInally
fd11f0fdb7 [GVN] Add support for unary FNeg to GVN pass
Differential Revision: https://reviews.llvm.org/D63896

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364592 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-27 21:05:02 +00:00
Sanjay Patel
df3cc01106 [x86] prevent crashing from select narrowing with AVX512
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364585 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-27 20:16:58 +00:00
Jinsong Ji
cbdf90b993 [PowerPC][NFC] Remove unused (and unsupported) fusion feature bits.
FeatureFusion bits was first introduced in
https://reviews.llvm.org/rL253724. for add/load integer fusion for P8.
The only use of `hasFusion` was https://reviews.llvm.org/rL255319.

However, this was removed later in https://reviews.llvm.org/rL280440.

So, there is NO any reference to fusion in code now.

Leaving it there is misleading and confusing, so remove it for now.
We can alwasy add back if we ever support fusion in the future.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364581 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-27 19:35:11 +00:00
Johannes Doerfert
775fc9548c Use "willreturn" in isGuaranteedToTransferExecutionToSuccessor
The `willreturn` function attribute guarantees that a function call will
come back to the call site if the call is also known not to throw.
Therefore, this attribute can be used in
`isGuaranteedToTransferExecutionToSuccessor`.

Patch by Hideto Ueno (@uenoku)

Reviewers: jdoerfert, sstefan1

Reviewed By: jdoerfert

Subscribers: hiraditya, jfb, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63372

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364580 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-27 19:29:48 +00:00
Philip Reames
27daa20eac Update -analyze -scalar-evolution output for multiple exit loops w/computable exit values
The previous output was next to useless if *any* exit was not computable.  If we have more than one exit, show the exit count for each so that it's easier to see what's going from with SCEV analysis when debugging.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364579 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-27 19:22:43 +00:00
Michael Liao
b7055ab4b1 Correct the file path. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364577 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-27 19:05:46 +00:00
Wouter van Oortmerssen
b389cd0209 [WebAssembly] AsmParser: better atomic inst detection
Summary:
Previously missed atomic.notify.

Fixes https://bugs.llvm.org/show_bug.cgi?id=40728

Reviewers: aheejin

Subscribers: sbc100, jgravelle-google, sunfish, jfb, llvm-commits, dschuff

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63747

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364576 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-27 18:58:26 +00:00
Djordje Todorovic
6998f5cb03 Revert "[LiveDebugValues] Emit the debug entry values"
Appears that the 'test/DebugInfo/MIR/X86/dbginfo-entryvals.mir'
does not pass on Windows.

This reverts commit rL364553.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364571 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-27 18:12:04 +00:00
Wouter van Oortmerssen
c1056cbe8b [WebAssembly] Fix p2align in assembler.
Summary:
- Match the syntax output by InstPrinter.
- Fix it always emitting 0 for align. Had to work around fact that
  opcode is not available for GetDefaultP2Align while parsing.
- Updated tests that were erroneously happy with a p2align=0

Fixes https://bugs.llvm.org/show_bug.cgi?id=40752

Reviewers: aheejin, sbc100

Subscribers: jgravelle-google, sunfish, jfb, llvm-commits, dschuff

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63633

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364570 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-27 18:11:15 +00:00
Simon Pilgrim
9a5e06d961 [X86] combineX86ShufflesRecursively - merge shuffles with more than 2 inputs
We already had the infrastructure for this, but were waiting for the fix for a number of regressions which were handled by the recent shuffle(extract_subvector(),extract_subvector()) -> extract_subvector(shuffle()) shuffle combines

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364569 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-27 17:30:51 +00:00
Roman Lebedev
1df452bb5a Revert "[CodeGen] [SelectionDAG] More efficient code for X % C == 0 (UREM case) (try 2)"
*Appears* to break test-suite on
http://lab.llvm.org:8011/builders/clang-cmake-x86_64-sde-avx512-linux/builds/23790

FAIL: burg.execution_time
FAIL: spiff.execution_time
FAIL: employ.execution_time
FAIL: llu.execution_time
FAIL: gramschmidt.execution_time
FAIL: fdtd-apml.execution_time

This reverts commit r364563.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364568 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-27 17:22:31 +00:00
Nicolai Haehnle
c71a1c3902 AMDGPU: Make fixing i1 copies robust against re-ordering
Summary:
The new test case led to incorrect code.

Change-Id: Ief48b227e97aa662dd3535c9bafb27d4a184efca

Reviewers: arsenm, david-salinas

Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63871

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364566 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-27 16:56:44 +00:00
Simon Pilgrim
b2caa05202 Use getConstantOperandAPInt instead of getConstantOperandVal for comparisons.
getConstantOperandAPInt avoids any large integer issues - these are unlikely but the fuzzers do like to mess around.....

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364564 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-27 16:46:00 +00:00
Roman Lebedev
84139109d4 [CodeGen] [SelectionDAG] More efficient code for X % C == 0 (UREM case) (try 2)
Summary:
I'm submitting a new revision since i don't understand how to reclaim/reopen/take over the existing one, D50222.
There is no such action in "Add Action" menu...
Original patch D50222 by @hermord (Dmytro Shynkevych)

This implements an optimization described in Hacker's Delight 10-17: when `C` is constant,
the result of `X % C == 0` can be computed more cheaply without actually calculating the remainder.
The motivation is discussed here: https://bugs.llvm.org/show_bug.cgi?id=35479.

Original patch author: @hermord (Dmytro Shynkevych)!

Notes:
- In principle, it's possible to also handle the `X % C1 == C2` case, as discussed on bugzilla.
  This seems to require an extra branch on overflow, so I refrained from implementing this for now.
- An explicit check for when the `REM` can be reduced to just its LHS is included:
  the `X % C` == 0 optimization breaks `test1` in `test/CodeGen/X86/jump_sign.ll` otherwise.
  I hadn't managed to find a better way to not generate worse output in this case.
- The `test/CodeGen/X86/jump_sign.ll` regresses, and is being fixed by a followup patch D63390.

Reviewers: RKSimon, craig.topper, spatel, hermord, xbolva00

Reviewed By: RKSimon, xbolva00

Subscribers: xbolva00, javed.absar, llvm-commits, hermord

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63391

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364563 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-27 16:45:42 +00:00
Simon Pilgrim
08c5274803 [X86] getTargetVShiftByConstNode - reduce variable scope. NFCI.
Fixes cppcheck warning.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364561 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-27 16:33:44 +00:00