Commit Graph

2595 Commits

Author SHA1 Message Date
Simon Pilgrim
eb39630694 [DAGCombine] visitEXTRACT_SUBVECTOR - add TODO for extract_subvector(bitcast()) support
We support 'big to little' (e.g. extract_subvector(v16i8 bitcast(v2i64))) but not 'little to big' cases  (e.g. extract_subvector(v2i64 bitcast(v16i8)))


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364405 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-26 11:17:38 +00:00
QingShan Zhang
2d7ed2481d Teach the DAGCombine to fold this pattern(c1 and c2 is constant).
// fold (sext (select cond, c1, c2)) -> (select cond, sext c1, sext c2)
// fold (zext (select cond, c1, c2)) -> (select cond, zext c1, zext c2)
// fold (aext (select cond, c1, c2)) -> (select cond, sext c1, sext c2)
Sign extend the operands if it is any_extend, to keep the signess of the operands that, the other combine rule would apply. The any_extend is handled as zero extend for constants. i.e.

t1: i8 = select t0, Constant:i8<-1>, Constant:i8<0>
t2: i64 = any_extend t1
 -->
t3: i64 = select t0, Constant:i64<-1>, Constant:i64<0>
 -->
t4: i64 = sign_extend_inreg t3

Differential Revision: https://reviews.llvm.org/D63318



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364382 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-26 05:12:53 +00:00
Simon Pilgrim
d3047099fd [DAGCombine] combineRepeatedFPDivisors - recognize -1.0 / X as a reciprocal
Fixes issue identified by @nemanjai (Nemanja Ivanovic) in D62963 / rL363040 - infinite loop due to GetNegatedExpression fighting combineRepeatedFPDivisors resulting in fneg(fdiv(x,splat)) -> fneg(fmul(x,1.0/splat)) -> fmul(x,-1.0/splat) -> fmul(x,(-1.0 * 1.0)/splat) ......

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364326 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-25 16:00:16 +00:00
Simon Pilgrim
0d7db2b064 [DAGCombine] visitMUL - allow shift by zero in MulByConstant.
This can occur under certain circumstances when undefs are created later on in the constant multipliers (e.g. in this case due to SimplifyDemandedVectorElts). Its better to let the shift by zero to occur and perform any cleanup afterward.

Fixes OSS Fuzz #15429

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364179 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-24 12:47:17 +00:00
Craig Topper
368f8d3387 [SelectionDAG] Remove the code that attempts to calculate the alignment for the second half of a split masked load/store.
The code divides the alignment by 2 if the original alignment is
equal to the original VT size. But this wouldn't be correct
if the alignment was larger than the VT size.

The memory operand object already takes care of calling MinAlign
on the base alignment and the memory pointer offset. So we don't
need any special code at all.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364151 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-23 07:00:46 +00:00
Simon Pilgrim
edb8a845db [DAGCombine] narrowExtractedVectorBinOp - pull out repeated getOpcode(). NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364076 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-21 16:44:51 +00:00
Simon Pilgrim
d821478ac9 [DAGCombine] narrowInsertExtractVectorBinOp - reuse "extract from insert" detection code.
Move the "extract from insert detection code" into a lambda helper function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364059 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-21 14:46:21 +00:00
Simon Pilgrim
fea914288b [DAGCombiner] Use getAPIntValue() instead of getZExtValue() where possible.
Better handling of out-of-i64-range values due to large integer types or from fuzz tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363955 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-20 17:36:23 +00:00
Jordan Rupprecht
83e2cc3dcc [DAGCombiner][NFC] Remove unused var
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363954 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-20 17:30:01 +00:00
Simon Pilgrim
702c4f09d3 [DAGCombiner] Support (shl (zext (srl x, C)), C) -> (zext (shl (srl x, C), C)) non-uniform folds.
Use matchBinaryPredicate instead of isConstOrConstSplat to let us handle non-uniform shift cases. 

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363929 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-20 14:42:27 +00:00
Simon Pilgrim
f5e38eacd2 [DAGCombine] Add TODOs for some combines that should support non-uniform vectors
We tend to only test for scalar/scalar consts when really we could support non-uniform vectors using ISD::matchUnaryPredicate/matchBinaryPredicate etc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363924 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-20 12:48:49 +00:00
Simon Pilgrim
c6588e6c21 [DAGCombine] Reduce scope of ShAmtVal variable. NFCI.
Fixes cppcheck warning.

Use the more capable getAPIntVal() instead of getZExtValue() as well since I'm here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363921 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-20 10:56:37 +00:00
Simon Pilgrim
374c7da137 [DAGCombine] Use ConstantSDNode::getAPIntValue() instead of getZExtValue().
Use getAPIntValue() in a few more places. Most of the time getZExtValue() is fine, but occasionally there's fuzzed code or someone decides to create i65536 or something.....

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363887 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-19 22:14:24 +00:00
Simon Pilgrim
1e8341d544 [DAGCombiner] Support (shl (ext (shl x, c1)), c2) -> (shl (ext x), (add c1, c2)) non-uniform folds.
Use matchBinaryPredicate instead of isConstOrConstSplat to let us handle non-uniform shift cases. 

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363793 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-19 12:41:37 +00:00
Simon Pilgrim
c69190afaf [DAGCombiner] Support (shl (ext (shl x, c1)), c2) -> 0 non-uniform folds.
Use matchBinaryPredicate instead of isConstOrConstSplat to let us handle non-uniform shift cases. 

This requires us to tweak matchBinaryPredicate to allow it to (optionally) handle constants with different type widths.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363792 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-19 12:25:29 +00:00
Simon Pilgrim
b9650afebd [DAGCombiner] visitSHL - pull out repeated shift amount VT. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363789 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-19 11:31:26 +00:00
Simon Pilgrim
07e51b46a7 [DAGCombine] Fix (shl (ext (shl x, c1)), c2) -> (shl (ext x), (add c1, c2)) comment. NFCI.
We pre-extend, not post.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363787 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-19 11:17:48 +00:00
Luis Marques
e36a3e35dd [DAGCombiner] [CodeGenPrepare] More comprehensive GEP splitting
Some GEPs were not being split, presumably because that split would just be 
undone by the DAGCombiner. Not performing those splits can prevent important 
optimizations, such as preventing the element indices / member offsets from 
being (partially) folded into load/store instruction immediates. This patch:

- Makes the splits also occur in the cases where the base address and the GEP 
  are in the same BB.
- Ensures that the DAGCombiner doesn't reassociate them back again.

Differential Revision: https://reviews.llvm.org/D60294



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363544 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-17 10:54:12 +00:00
Michael Berg
d71bd8db7b adding more fmf propagation for selects plus updated tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363484 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-15 04:53:51 +00:00
Fangrui Song
118986bcda Revert "adding more fmf propagation for selects plus tests"
This reverts rL363474. -debug-only=isel was added to some tests that
don't specify `REQUIRES: asserts`. This causes failures on
-DLLVM_ENABLE_ASSERTIONS=off builds.

I chose to revert instead of fixing the tests because I'm not sure
whether we should add `REQUIRES: asserts` to more tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363482 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-15 03:51:08 +00:00
Michael Berg
aad9d5e5dd adding more fmf propagation for selects plus tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363474 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-14 23:30:52 +00:00
Simon Pilgrim
9b95d3f22f [TargetLowering] Add MachineMemOperand::Flags to allowsMemoryAccess tests (PR42123)
As discussed on D62910, we need to check whether particular types of memory access are allowed, not just their alignment/address-space.

This NFC patch adds a MachineMemOperand::Flags argument to allowsMemoryAccess and allowsMisalignedMemoryAccesses, and wires up calls to pass the relevant flags to them.

If people are happy with this approach I can then update X86TargetLowering::allowsMisalignedMemoryAccesses to handle misaligned NT load/stores.

Differential Revision: https://reviews.llvm.org/D63075

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363179 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-12 17:14:03 +00:00
Simon Pilgrim
2c71ea94d2 [TargetLowering] Add allowsMemoryAccess(MachineMemOperand) helper wrapper. NFCI.
As suggested by @arsenm on D63075 - this adds a TargetLowering::allowsMemoryAccess wrapper that takes a Load/Store node's MachineMemOperand to handle the AddressSpace/Alignment arguments and will also implicitly handle the MachineMemOperand::Flags change in D63075.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363048 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-11 11:00:23 +00:00
Simon Pilgrim
6317ed58b0 [DAGCombine] GetNegatedExpression - constant float vector support (PR42105)
Add support for negation of constant build vectors.

Differential Revision: https://reviews.llvm.org/D62963

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363040 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-11 09:44:33 +00:00
QingShan Zhang
39d8acb1d8 [DAGCombine] Match a pattern where a wide type scalar value is stored by several narrow stores
This opportunity is found from spec 2017 557.xz_r. And it is used by the sha encrypt/decrypt. See sha-2/sha512.c

static void store64(u64 x, unsigned char* y)
{
    for(int i = 0; i != 8; ++i)
        y[i] = (x >> ((7-i) * 8)) & 255;
}

static u64 load64(const unsigned char* y)
{
    u64 res = 0;
    for(int i = 0; i != 8; ++i)
        res |= (u64)(y[i]) << ((7-i) * 8);
    return res;
}
The load64 has been implemented by https://reviews.llvm.org/D26149
This patch is trying to implement the store pattern.

Match a pattern where a wide type scalar value is stored by several narrow
stores. Fold it into a single store or a BSWAP and a store if the targets
supports it.

Assuming little endian target:
i8 *p = ...
i32 val = ...
p[0] = (val >> 0) & 0xFF;
p[1] = (val >> 8) & 0xFF;
p[2] = (val >> 16) & 0xFF;
p[3] = (val >> 24) & 0xFF;

>
*((i32)p) = val;

i8 *p = ...
i32 val = ...
p[0] = (val >> 24) & 0xFF;
p[1] = (val >> 16) & 0xFF;
p[2] = (val >> 8) & 0xFF;
p[3] = (val >> 0) & 0xFF;

>
*((i32)p) = BSWAP(val);

Differential Revision: https://reviews.llvm.org/D62897



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362921 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-10 05:40:21 +00:00
Simon Pilgrim
36c109e47b Use for-range loop. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362897 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-09 09:07:30 +00:00
Simon Pilgrim
eecb240e9f [DAGCombine] visitAND - merge (zext_inreg ((s)extload x)) -> (zextload x) combines. NFCI.
Same codegen, only differ by the oneuse limit for the sextload case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362880 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-08 17:02:00 +00:00
Simon Pilgrim
9c4a9b9919 [DAGCombine] visitAND - fix local shadow variable warnings. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362825 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-07 18:36:43 +00:00
Simon Pilgrim
f409c45eff [DAGCombine] Use APInt::extractBits in "sub-splat" constant mask detection. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362820 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-07 18:07:06 +00:00
Simon Pilgrim
deea5e593e [DAGCombine] MergeConsecutiveStores - improve non-temporal load\store handling (PR42123)
This patch is the first step towards ensuring MergeConsecutiveStores correctly handles non-temporal loads\stores:

1 - When merging load\stores we must ensure that they all have the same non-temporal flag. This is unlikely to occur, but can in strange cases where we're storing at the end of one page and the beginning of another.

2 - The merged load\store node must retain the non-temporal flag.

Differential Revision: https://reviews.llvm.org/D62910

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362723 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-06 17:04:13 +00:00
Simon Pilgrim
2f136046e7 [DAGCombine] Cleanup isNegatibleForFree/GetNegatedExpression. NFCI.
Prep work for PR42105 - clang-format, use auto for cast and merge nested if()s

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362695 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-06 10:21:18 +00:00
Simon Pilgrim
56aef0ccc9 Fix shadow local variable warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362622 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-05 17:26:29 +00:00
Nemanja Ivanovic
a395745750 Revert r362472 as it is breaking PPC build bots
The patch https://reviews.llvm.org/rL362472 broke PPC LNT buildbots.
Reverting it to bring the bots back to green.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362539 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-04 18:48:43 +00:00
Craig Topper
74136095bc [DAGCombiner][X86] Fold (not (neg X)) -> (add X, -1)
This is a special case of a more general transform (not (sub Y, X)) -> (add X, ~Y). InstCombine knows the general form. I've restricted to the special case to fix the motivating case PR42118. I tried handling any case where Y was constant, but got some changes on some Mips tests that I couldn't quickly prove where beneficial.

Fixes PR42118

Differential Revision: https://reviews.llvm.org/D62828

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362533 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-04 17:44:18 +00:00
Sanjay Patel
47d861e4bf [SelectionDAG][x86] limit post-legalization store merging by type
The proposal in D62498 showed that x86 would benefit from vector
store splitting, but that may conflict with the generic DAG
combiner's store merging transforms.

Add memory type to the existing TLI hook that enables the merging
transforms, so we can limit those changes to scalars only for x86.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362507 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-04 15:15:59 +00:00
Roman Lebedev
4c668f9d5b [DAGCombine][X86][AArch64][MIPS][LANAI] (C - x) - y -> C - (x + y) fold (PR41952)
Summary:
This *might* be the last fold for `sink-addsub-of-const.ll`, but i'm not sure yet.

As far as i can tell, there are no regressions here (ignoring x86-32),
all changes are either good or neutral.

This, almost surprisingly to me, fixes the motivational tests (in `shift-amount-mod.ll`)
`@reg32_lshr_by_sub_from_negated` from [[ https://bugs.llvm.org/show_bug.cgi?id=41952 | PR41952 ]].

https://rise4fun.com/Alive/vMd3

Reviewers: RKSimon, t.p.northover, craig.topper, spatel, efriedma

Reviewed By: RKSimon

Subscribers: sdardis, javed.absar, arichardson, kristof.beyls, jrtc27, atanasyan, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D62774

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362488 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-04 11:06:21 +00:00
Roman Lebedev
e270352fc3 [DAGCombine][X86][AArch64][ARM] (C - x) + y -> (y - x) + C fold
Summary:
All changes except ARM look **great**.
https://rise4fun.com/Alive/R2M

The regression `test/CodeGen/ARM/addsubcarry-promotion.ll`
is recovered fully by D62392 + D62450.

Reviewers: RKSimon, craig.topper, spatel, rogfer01, efriedma

Reviewed By: efriedma

Subscribers: dmgreen, javed.absar, kristof.beyls, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D62266

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362487 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-04 11:06:08 +00:00
Simon Pilgrim
11c4864708 [SelectionDAG] Add fpto[us]i(undef) --> undef constant fold
Follow up to D62807.

Differential Revision: https://reviews.llvm.org/D62811

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362483 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-04 10:04:55 +00:00
QingShan Zhang
d59be50a0a [DAGCombine] Match a pattern where a wide type scalar value is stored by several narrow stores
This opportunity is found from spec 2017 557.xz_r. And it is used by the sha encrypt/decrypt. See sha-2/sha512.c

static void store64(u64 x, unsigned char* y)
{
    for(int i = 0; i != 8; ++i)
        y[i] = (x >> ((7-i) * 8)) & 255;
}

static u64 load64(const unsigned char* y)
{
    u64 res = 0;
    for(int i = 0; i != 8; ++i)
        res |= (u64)(y[i]) << ((7-i) * 8);
    return res;
}
The load64 has been implemented by https://reviews.llvm.org/D26149
This patch is trying to implement the store pattern.

Match a pattern where a wide type scalar value is stored by several narrow
stores. Fold it into a single store or a BSWAP and a store if the targets
supports it.

Assuming little endian target:
i8 *p = ...
i32 val = ...
p[0] = (val >> 0) & 0xFF;
p[1] = (val >> 8) & 0xFF;
p[2] = (val >> 16) & 0xFF;
p[3] = (val >> 24) & 0xFF;

>
*((i32)p) = val;

i8 *p = ...
i32 val = ...
p[0] = (val >> 24) & 0xFF;
p[1] = (val >> 16) & 0xFF;
p[2] = (val >> 8) & 0xFF;
p[3] = (val >> 0) & 0xFF;

>
*((i32)p) = BSWAP(val);

Differential Revision: https://reviews.llvm.org/D61843



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362472 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-04 08:53:53 +00:00
Michael Berg
66d9648f59 Propagate fmf for setcc/select folds
Summary: This change facilitates propagating fmf which was placed on setcc from fcmp through folds with selects so that back ends can model this path for arithmetic folds on selects in SDAG.

Reviewers: qcolombet, spatel

Reviewed By: qcolombet

Subscribers: nemanjai, jsji

Differential Revision: https://reviews.llvm.org/D62552

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362439 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-03 19:12:15 +00:00
Simon Pilgrim
2d2b2ea8ca [SelectionDAG] Add [us]itofp(undef) --> 0 constant fold (PR39205)
We were missing this fold in the DAG, which I've copied directly from llvm::ConstantFoldCastInstruction

Differential Revision: https://reviews.llvm.org/D62807

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362397 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-03 13:02:07 +00:00
Florian Hahn
cbd1abe8d8 Recommit r360171: [DAGCombiner] Avoid creating large tokenfactors in visitTokenFactor.
If we hit the limit, we do expand the outstanding tokenfactors.
Otherwise, we might drop nodes with users in the unexpanded
tokenfactors. This fixes the crashes reported by Jordan Rupprecht.

Reviewers: niravd, spatel, craig.topper, rupprecht

Reviewed By: niravd

Differential Revision: https://reviews.llvm.org/D62633

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362350 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-03 01:30:19 +00:00
Craig Topper
12cba04e86 [DAGCombiner][X86] Fold away masked store and scatter with all zeroes mask.
Similar to what was done for masked load and gather.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362342 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-02 22:52:38 +00:00
Craig Topper
010dd36cca [DAGCombiner] Replace masked loads with a zero mask with the passthru value
Similar to what was recently done for gathers in r362015.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362337 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-02 18:58:46 +00:00
Simon Pilgrim
68ea3a046b [DAGCombine] Fold insert_subvector(bitcast(x),bitcast(y),c1) -> bitcast(insert_subvector(x,y),c2)
Move this combine from x86 into generic DAGCombine, which currently only manages cases where the bitcast is between types of the same scalarsize.

Differential Revision: https://reviews.llvm.org/D59188

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362324 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-02 14:42:11 +00:00
Craig Topper
6f01df3d75 [DAGCombiner] Replace two unchecked dyn_casts with casts.
The results of the dyn_casts were immediately dereferenced on the next line
so they had better not be null.

I don't think there's any way for these dyn_casts to fail, so use a cast
of adding null check.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362315 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-02 03:31:01 +00:00
Roman Lebedev
deaea97947 [DAGCombine] Limit 'hoist add/sub binop w/ constant op' to non-opaque consts
I don't have a test case for these, but there is a test case for D62266
where, even after all the constant-folding patches, we still end up
with endless combine loop. Which makes sense, since we don't constant
fold for opaque constants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362156 91177308-0d34-0410-b5e6-96231b3b80d8
2019-05-30 21:10:37 +00:00
Roman Lebedev
f9fcbf5fb1 [DAGCombiner][X86][AArch64] (x - C) + y -> (x + y) - C fold. Try 2
Summary:
Only vector tests are being affected here,
since subtraction by scalar constant is rewritten
as addition by negated constant.

No surprising test changes.

https://rise4fun.com/Alive/pbT

This is a recommit, originally committed in rL361852, but reverted
to investigate test-suite compile-time hangs.

Reviewers: RKSimon, craig.topper, spatel

Reviewed By: RKSimon

Subscribers: javed.absar, kristof.beyls, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D62257

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362146 91177308-0d34-0410-b5e6-96231b3b80d8
2019-05-30 20:37:49 +00:00
Roman Lebedev
438582d348 [DAGCombine] (x - C) - y -> (x - y) - C fold. Try 3
Summary:
Again only vectors affected. Frustrating. Let me take a look into that..

https://rise4fun.com/Alive/AAq

This is a recommit, originally committed in rL361852, but reverted
to investigate test-suite compile-time hangs, and then reverted in
rL362109 to fix missing constant folds that were causing
endless combine loops.

Reviewers: RKSimon, craig.topper, spatel

Reviewed By: RKSimon

Subscribers: javed.absar, JDevlieghere, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D62294

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362145 91177308-0d34-0410-b5e6-96231b3b80d8
2019-05-30 20:37:39 +00:00
Roman Lebedev
97a393580c [DAGCombine][X86][AArch64][AMDGPU] (x - y) + -1 -> add (xor y, -1), x fold. Try 3
Summary:
This prevents regressions in next patch,
and somewhat recovers from the regression to AMDGPU test in D62223.

It is indeed not great that we leave vector decrement,
don't transform it into vector add all-ones..

https://rise4fun.com/Alive/ZRl

This is a recommit, originally committed in rL361852, but reverted
to investigate test-suite compile-time hangs, and then reverted in
rL362109 to fix missing constant folds that were causing
endless combine loops.

Reviewers: RKSimon, craig.topper, spatel, arsenm

Reviewed By: RKSimon, arsenm

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, javed.absar, dstuttard, tpr, t-tye, kristof.beyls, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D62263

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362144 91177308-0d34-0410-b5e6-96231b3b80d8
2019-05-30 20:37:29 +00:00