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3 Commits

Author SHA1 Message Date
Matt Arsenault
a2b05bc24d CodeGen: Introduce a class for registers 
Avoids using a plain unsigned for registers throughoug codegen.
Doesn't attempt to change every register use, just something a little
more than the set needed to build after changing the return type of
MachineOperand::getReg().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364191 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-06-24 15:50:29 +00:00
Pete Couperus
0aec7d5911 Uncomment LLVM_FALLTHROUGH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360798 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-05-15 19:46:17 +00:00
Pete Couperus
b82e24e53f [ARC] Add ARCOptAddrMode pass to generate postincrement loads/stores. 
Build on newly introduced ARC postincrement loads/stores from r356200.

Patch By Denis Antrushin! <denis@synopsys.com>

Differential Revision: https://reviews.llvm.org/D59409

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356606 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-03-20 20:06:21 +00:00