Commit Graph

12 Commits

Author SHA1 Message Date
Hsiangkai Wang
0b65399dd6 [RISCV] Add CFI directives for RISCV prologue/epilog.
In order to generate correct debug frame information, it needs to
generate CFI information in prologue and epilog.

Differential Revision: https://reviews.llvm.org/D61773

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363120 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-12 03:04:22 +00:00
Chandler Carruth
6b547686c5 Update the file headers across all of the LLVM projects in the monorepo
to reflect the new license.

We understand that people may be surprised that we're moving the header
entirely to discuss the new license. We checked this carefully with the
Foundation's lawyer and we believe this is the correct approach.

Essentially, all code in the project is now made available by the LLVM
project under our new license, so you will see that the license headers
include that license only. Some of our contributors have contributed
code under our old license, and accordingly, we have retained a copy of
our old license notice in the top-level files in each project and
repository.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351636 91177308-0d34-0410-b5e6-96231b3b80d8
2019-01-19 08:50:56 +00:00
Ana Pazos
2feea28672 [RISCV] Fix std::advance slowness
Summary:
It seems std::advance template is treating "-MFI.getCalleeSavedInfo().size()"
as a large unsigned value", causing slowness.

Thanks to Henrik Gustafsson for reporting the issue.

Reviewers: asb

Reviewed By: asb

Subscribers: llvm-commits, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, asb

Differential Revision: https://reviews.llvm.org/D51148

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340669 91177308-0d34-0410-b5e6-96231b3b80d8
2018-08-24 23:13:59 +00:00
Ana Pazos
23f8b78022 [RISCV] Add support for _interrupt attribute
- Save/restore only registers that are used.
This includes Callee saved registers and Caller saved registers
(arguments and temporaries) for integer and FP registers.
- If there is a call in the interrupt handler, save/restore all
Caller saved registers (arguments and temporaries) and all FP registers.
- Emit special return instructions depending on "interrupt"
attribute type.
Based on initial patch by Zhaoshi Zheng.

Reviewers: asb

Reviewed By: asb

Subscribers: rkruppe, the_o, MartinMosbeck, brucehoult, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, rogfer01, llvm-commits

Differential Revision: https://reviews.llvm.org/D48411

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338047 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-26 17:49:43 +00:00
Shiva Chen
6a9321130f [RISCV] Preserve stack space for outgoing arguments when the function contain variable size objects
E.g.

bar (int x)
{
  char p[x];

  push outgoing variables for foo.
  call foo
}

We need to generate stack adjustment instructions for outgoing arguments by
eliminateCallFramePseudoInstr when the function contains variable size
objects to avoid outgoing variables corrupt the variable size object.

Default hasReservedCallFrame will return !hasFP().
We don't want to generate extra sp adjustment instructions when hasFP()
return true, So We override hasReservedCallFrame as !hasVarSizedObjects().

Differential Revision: https://reviews.llvm.org/D43752

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327938 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-20 01:39:17 +00:00
Alex Bradbury
ff5fe57525 [RISCV] Implement frame pointer elimination
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322839 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-18 11:34:02 +00:00
Alex Bradbury
585e4d5040 [RISCV] Reserve an emergency spill slot for the register scavenger when necessary
Although the register scavenger can often find a spare register, an emergency 
spill slot is needed to guarantee success. Reserve this slot in cases where 
the function is known to have a large stack (meaning the scavenger may be 
needed when forming stack addresses).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322269 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-11 11:17:19 +00:00
Alex Bradbury
58c4e96dc9 [RISCV] Support stack frames and offsets up to 32-bits
Differential Revision: https://reviews.llvm.org/D40807


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322216 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-10 19:53:46 +00:00
Alex Bradbury
2e92718904 [RISCV] Support for varargs
Includes support for expanding va_copy. Also adds support for using 'aligned'
registers when necessary for vararg calls, and ensure the frame pointer always
points to the bottom of the vararg spill region. This is necessary to ensure
that the saved return address and stack pointer are always available at fixed
known offsets of the frame pointer.

Differential Revision: https://reviews.llvm.org/D40805



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322215 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-10 19:41:03 +00:00
Alex Bradbury
dcfcbe7bdc [RISCV] Implement prolog and epilog insertion
As frame pointer elimination isn't implemented until a later patch and we make 
extensive use of update_llc_test_checks.py, this changes touches a lot of the 
RISC-V tests.

Differential Revision: https://reviews.llvm.org/D39849


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320357 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-11 12:34:11 +00:00
Alex Bradbury
1e4e4646ad [RISCV] Support lowering FrameIndex
Introduces the AddrFI "addressing mode", which is necessary simply because 
it's not possible to write a pattern that directly matches a frameindex.

Ensure callee-saved registers are accessed relative to the stackpointer. This
is necessary as callee-saved register spills are performed before the frame
pointer is set.

Move HexagonDAGToDAGISel::isOrEquivalentToAdd to SelectionDAGISel, so we can 
make use of it in the RISC-V backend.

Differential Revision: https://reviews.llvm.org/D39848


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320353 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-11 11:53:54 +00:00
Alex Bradbury
5a3d179fab [RISCV] Initial codegen support for ALU operations
This adds the minimum necessary to support codegen for simple ALU operations
on RV32. Prolog and epilog insertion, support for memory operations etc etc 
follow in future patches.

Leave guessInstructionProperties=1 until https://reviews.llvm.org/D37065 is 
reviewed and lands.

Differential Revision: https://reviews.llvm.org/D29933


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316188 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-19 21:37:38 +00:00