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f9deb98480
Keep loads and stores together (target defines how many loads and stores to gang up), such that it will help in pairing and vectorization. Differential Revision https://reviews.llvm.org/D46477 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332482 91177308-0d34-0410-b5e6-96231b3b80d8
22 lines
780 B
LLVM
22 lines
780 B
LLVM
; RUN: llc -o - %s | FileCheck %s
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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target triple = "arm64-apple-ios10.0.0"
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; PR33475 - Expect 64-bit operations as 128-operations are not legal
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; However, we can generate a paired 64-bit loads and stores, without using
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; floating point registers.
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; CHECK-LABEL: pr33475
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; CHECK-DAG: ldp [[R0:x[0-9]+]], [[R0:x[0-9]+]], [x1, #16]
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; CHECK-DAG: ldp [[R0:x[0-9]+]], [[R0:x[0-9]+]], [x1]
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; CHECK-DAG: stp [[R0:x[0-9]+]], [[R0:x[0-9]+]], [x0, #16]
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; CHECK-DAG: stp [[R0:x[0-9]+]], [[R0:x[0-9]+]], [x0]
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define void @pr33475(i8* %p0, i8* %p1) noimplicitfloat {
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call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %p0, i8* align 4 %p1, i64 32, i1 false)
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ret void
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}
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declare void @llvm.memcpy.p0i8.p0i8.i64(i8*, i8*, i64, i1)
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