mirror of
https://github.com/RPCS3/llvm.git
synced 2026-01-31 01:25:19 +01:00
695940b0f1
Reapply r346374 with the fixes for modules build. Original summary: This change implements assembler parser, code emitter, ELF object writer and disassembler for the MSP430 ISA. Also, more instruction forms are added to the target description. Patch by Michael Skvortsov! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346948 91177308-0d34-0410-b5e6-96231b3b80d8
47 lines
854 B
LLVM
47 lines
854 B
LLVM
; RUN: llc -march=msp430 < %s | FileCheck %s
|
|
target datalayout = "e-p:16:8:8-i8:8:8-i8:8:8-i32:8:8"
|
|
target triple = "msp430-generic-generic"
|
|
|
|
define i8 @mov(i8 %a, i8 %b) nounwind {
|
|
; CHECK-LABEL: mov:
|
|
; CHECK: mov r13, r12
|
|
ret i8 %b
|
|
}
|
|
|
|
define i8 @add(i8 %a, i8 %b) nounwind {
|
|
; CHECK-LABEL: add:
|
|
; CHECK: add.b
|
|
%1 = add i8 %a, %b
|
|
ret i8 %1
|
|
}
|
|
|
|
define i8 @and(i8 %a, i8 %b) nounwind {
|
|
; CHECK-LABEL: and:
|
|
; CHECK: and r13, r12
|
|
%1 = and i8 %a, %b
|
|
ret i8 %1
|
|
}
|
|
|
|
define i8 @bis(i8 %a, i8 %b) nounwind {
|
|
; CHECK-LABEL: bis:
|
|
; CHECK: bis r13, r12
|
|
%1 = or i8 %a, %b
|
|
ret i8 %1
|
|
}
|
|
|
|
define i8 @bic(i8 %a, i8 %b) nounwind {
|
|
; CHECK-LABEL: bic:
|
|
; CHECK: bic.b r13, r12
|
|
%1 = xor i8 %b, -1
|
|
%2 = and i8 %a, %1
|
|
ret i8 %2
|
|
}
|
|
|
|
define i8 @xor(i8 %a, i8 %b) nounwind {
|
|
; CHECK-LABEL: xor:
|
|
; CHECK: xor r13, r12
|
|
%1 = xor i8 %a, %b
|
|
ret i8 %1
|
|
}
|
|
|