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https://github.com/RPCS3/llvm.git
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6d2316158f
DAG combiner combines two shifts into shift + and with bitmask. Avoid such combines for vectors since leaving two vector shifts as they are produces better end results. Differential Revision: https://reviews.llvm.org/D58225 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354461 91177308-0d34-0410-b5e6-96231b3b80d8
212 lines
8.4 KiB
LLVM
212 lines
8.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=mips64el-linux-gnu -mcpu=mips64r6 -mattr=+msa,+fp64 < %s | FileCheck %s --check-prefixes=MIPSEL64R6
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; RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64 < %s | FileCheck %s --check-prefixes=MIPSEL32R5
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declare <2 x i64> @llvm.mips.slli.d(<2 x i64>, i32)
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declare <2 x i64> @llvm.mips.srli.d(<2 x i64>, i32)
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declare <4 x i32> @llvm.mips.slli.w(<4 x i32>, i32)
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declare <4 x i32> @llvm.mips.srli.w(<4 x i32>, i32)
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; do not fold (shl (srl x, c1), c2) -> (and (srl x, (sub c1, c2), MASK) if C1 < C2
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; MASK_TYPE1 = C2-C1 0s | 1s | ends with C1 0s
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define void @avoid_to_combine_shifts_to_shift_plus_and_mask_type1_i64(<2 x i64>* %a, <2 x i64>* %b) {
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; MIPSEL64R6-LABEL: avoid_to_combine_shifts_to_shift_plus_and_mask_type1_i64:
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; MIPSEL64R6: # %bb.0: # %entry
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; MIPSEL64R6-NEXT: ld.d $w0, 0($4)
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; MIPSEL64R6-NEXT: srli.d $w0, $w0, 52
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; MIPSEL64R6-NEXT: slli.d $w0, $w0, 51
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; MIPSEL64R6-NEXT: jr $ra
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; MIPSEL64R6-NEXT: st.d $w0, 0($5)
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;
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; MIPSEL32R5-LABEL: avoid_to_combine_shifts_to_shift_plus_and_mask_type1_i64:
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; MIPSEL32R5: # %bb.0: # %entry
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; MIPSEL32R5-NEXT: ld.d $w0, 0($4)
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; MIPSEL32R5-NEXT: srli.d $w0, $w0, 52
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; MIPSEL32R5-NEXT: slli.d $w0, $w0, 51
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; MIPSEL32R5-NEXT: jr $ra
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; MIPSEL32R5-NEXT: st.d $w0, 0($5)
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entry:
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%0 = load <2 x i64>, <2 x i64>* %a
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%1 = tail call <2 x i64> @llvm.mips.srli.d(<2 x i64> %0, i32 52)
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%2 = tail call <2 x i64> @llvm.mips.slli.d(<2 x i64> %1, i32 51)
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store <2 x i64> %2, <2 x i64>* %b
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ret void
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}
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; do not fold (shl (srl x, c1), c2) -> (and (srl x, (sub c1, c2), MASK) if C1 < C2
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define void @avoid_to_combine_shifts_to_shift_plus_and_mask_type1_i64_long(<2 x i64>* %a, <2 x i64>* %b) {
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; MIPSEL64R6-LABEL: avoid_to_combine_shifts_to_shift_plus_and_mask_type1_i64_long:
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; MIPSEL64R6: # %bb.0: # %entry
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; MIPSEL64R6-NEXT: ld.d $w0, 0($4)
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; MIPSEL64R6-NEXT: srli.d $w0, $w0, 6
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; MIPSEL64R6-NEXT: slli.d $w0, $w0, 4
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; MIPSEL64R6-NEXT: jr $ra
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; MIPSEL64R6-NEXT: st.d $w0, 0($5)
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;
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; MIPSEL32R5-LABEL: avoid_to_combine_shifts_to_shift_plus_and_mask_type1_i64_long:
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; MIPSEL32R5: # %bb.0: # %entry
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; MIPSEL32R5-NEXT: ld.d $w0, 0($4)
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; MIPSEL32R5-NEXT: srli.d $w0, $w0, 6
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; MIPSEL32R5-NEXT: slli.d $w0, $w0, 4
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; MIPSEL32R5-NEXT: jr $ra
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; MIPSEL32R5-NEXT: st.d $w0, 0($5)
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entry:
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%0 = load <2 x i64>, <2 x i64>* %a
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%1 = tail call <2 x i64> @llvm.mips.srli.d(<2 x i64> %0, i32 6)
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%2 = tail call <2 x i64> @llvm.mips.slli.d(<2 x i64> %1, i32 4)
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store <2 x i64> %2, <2 x i64>* %b
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ret void
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}
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; do not fold (shl (srl x, c1), c2) -> (and (shl x, (sub c1, c2), MASK) if C1 >= C2
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; MASK_TYPE2 = 1s | C1 zeros
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define void @avoid_to_combine_shifts_to_shift_plus_and_mask_type2_i32(<2 x i64>* %a, <2 x i64>* %b) {
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; MIPSEL64R6-LABEL: avoid_to_combine_shifts_to_shift_plus_and_mask_type2_i32:
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; MIPSEL64R6: # %bb.0: # %entry
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; MIPSEL64R6-NEXT: ld.d $w0, 0($4)
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; MIPSEL64R6-NEXT: srli.d $w0, $w0, 4
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; MIPSEL64R6-NEXT: slli.d $w0, $w0, 6
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; MIPSEL64R6-NEXT: jr $ra
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; MIPSEL64R6-NEXT: st.d $w0, 0($5)
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;
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; MIPSEL32R5-LABEL: avoid_to_combine_shifts_to_shift_plus_and_mask_type2_i32:
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; MIPSEL32R5: # %bb.0: # %entry
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; MIPSEL32R5-NEXT: ld.d $w0, 0($4)
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; MIPSEL32R5-NEXT: srli.d $w0, $w0, 4
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; MIPSEL32R5-NEXT: slli.d $w0, $w0, 6
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; MIPSEL32R5-NEXT: jr $ra
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; MIPSEL32R5-NEXT: st.d $w0, 0($5)
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entry:
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%0 = load <2 x i64>, <2 x i64>* %a
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%1 = tail call <2 x i64> @llvm.mips.srli.d(<2 x i64> %0, i32 4)
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%2 = tail call <2 x i64> @llvm.mips.slli.d(<2 x i64> %1, i32 6)
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store <2 x i64> %2, <2 x i64>* %b
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ret void
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}
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; do not fold (shl (srl x, c1), c2) -> (and (srl x, (sub c1, c2), MASK) if C1 < C2
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define void @avoid_to_combine_shifts_to_shift_plus_and_mask_type1_i32_long(<4 x i32>* %a, <4 x i32>* %b) {
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; MIPSEL64R6-LABEL: avoid_to_combine_shifts_to_shift_plus_and_mask_type1_i32_long:
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; MIPSEL64R6: # %bb.0: # %entry
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; MIPSEL64R6-NEXT: ld.w $w0, 0($4)
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; MIPSEL64R6-NEXT: srli.w $w0, $w0, 7
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; MIPSEL64R6-NEXT: slli.w $w0, $w0, 3
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; MIPSEL64R6-NEXT: jr $ra
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; MIPSEL64R6-NEXT: st.w $w0, 0($5)
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;
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; MIPSEL32R5-LABEL: avoid_to_combine_shifts_to_shift_plus_and_mask_type1_i32_long:
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; MIPSEL32R5: # %bb.0: # %entry
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; MIPSEL32R5-NEXT: ld.w $w0, 0($4)
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; MIPSEL32R5-NEXT: srli.w $w0, $w0, 7
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; MIPSEL32R5-NEXT: slli.w $w0, $w0, 3
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; MIPSEL32R5-NEXT: jr $ra
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; MIPSEL32R5-NEXT: st.w $w0, 0($5)
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entry:
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%0 = load <4 x i32>, <4 x i32>* %a
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%1 = tail call <4 x i32> @llvm.mips.srli.w(<4 x i32> %0, i32 7)
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%2 = tail call <4 x i32> @llvm.mips.slli.w(<4 x i32> %1, i32 3)
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store <4 x i32> %2, <4 x i32>* %b
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ret void
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}
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; do not fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
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define void @avoid_to_combine_shifts_to_and_mask_type2_i64_long(<2 x i64>* %a, <2 x i64>* %b) {
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; MIPSEL64R6-LABEL: avoid_to_combine_shifts_to_and_mask_type2_i64_long:
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; MIPSEL64R6: # %bb.0: # %entry
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; MIPSEL64R6-NEXT: ld.d $w0, 0($4)
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; MIPSEL64R6-NEXT: srli.d $w0, $w0, 38
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; MIPSEL64R6-NEXT: slli.d $w0, $w0, 38
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; MIPSEL64R6-NEXT: jr $ra
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; MIPSEL64R6-NEXT: st.d $w0, 0($5)
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;
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; MIPSEL32R5-LABEL: avoid_to_combine_shifts_to_and_mask_type2_i64_long:
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; MIPSEL32R5: # %bb.0: # %entry
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; MIPSEL32R5-NEXT: ld.d $w0, 0($4)
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; MIPSEL32R5-NEXT: srli.d $w0, $w0, 38
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; MIPSEL32R5-NEXT: slli.d $w0, $w0, 38
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; MIPSEL32R5-NEXT: jr $ra
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; MIPSEL32R5-NEXT: st.d $w0, 0($5)
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entry:
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%0 = load <2 x i64>, <2 x i64>* %a
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%1 = tail call <2 x i64> @llvm.mips.srli.d(<2 x i64> %0, i32 38)
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%2 = tail call <2 x i64> @llvm.mips.slli.d(<2 x i64> %1, i32 38)
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store <2 x i64> %2, <2 x i64>* %b
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ret void
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}
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; do not fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
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define void @avoid_to_combine_shifts_to_and_mask_type2_i64(<2 x i64>* %a, <2 x i64>* %b) {
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; MIPSEL64R6-LABEL: avoid_to_combine_shifts_to_and_mask_type2_i64:
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; MIPSEL64R6: # %bb.0: # %entry
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; MIPSEL64R6-NEXT: ld.d $w0, 0($4)
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; MIPSEL64R6-NEXT: srli.d $w0, $w0, 3
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; MIPSEL64R6-NEXT: slli.d $w0, $w0, 3
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; MIPSEL64R6-NEXT: jr $ra
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; MIPSEL64R6-NEXT: st.d $w0, 0($5)
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;
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; MIPSEL32R5-LABEL: avoid_to_combine_shifts_to_and_mask_type2_i64:
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; MIPSEL32R5: # %bb.0: # %entry
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; MIPSEL32R5-NEXT: ld.d $w0, 0($4)
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; MIPSEL32R5-NEXT: srli.d $w0, $w0, 3
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; MIPSEL32R5-NEXT: slli.d $w0, $w0, 3
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; MIPSEL32R5-NEXT: jr $ra
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; MIPSEL32R5-NEXT: st.d $w0, 0($5)
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entry:
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%0 = load <2 x i64>, <2 x i64>* %a
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%1 = tail call <2 x i64> @llvm.mips.srli.d(<2 x i64> %0, i32 3)
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%2 = tail call <2 x i64> @llvm.mips.slli.d(<2 x i64> %1, i32 3)
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store <2 x i64> %2, <2 x i64>* %b
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ret void
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}
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; do not fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
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define void @avoid_to_combine_shifts_to_and_mask_type1_long_i32_a(<4 x i32>* %a, <4 x i32>* %b) {
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; MIPSEL64R6-LABEL: avoid_to_combine_shifts_to_and_mask_type1_long_i32_a:
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; MIPSEL64R6: # %bb.0: # %entry
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; MIPSEL64R6-NEXT: ld.w $w0, 0($4)
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; MIPSEL64R6-NEXT: srli.w $w0, $w0, 5
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; MIPSEL64R6-NEXT: slli.w $w0, $w0, 5
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; MIPSEL64R6-NEXT: jr $ra
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; MIPSEL64R6-NEXT: st.w $w0, 0($5)
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;
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; MIPSEL32R5-LABEL: avoid_to_combine_shifts_to_and_mask_type1_long_i32_a:
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; MIPSEL32R5: # %bb.0: # %entry
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; MIPSEL32R5-NEXT: ld.w $w0, 0($4)
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; MIPSEL32R5-NEXT: srli.w $w0, $w0, 5
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; MIPSEL32R5-NEXT: slli.w $w0, $w0, 5
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; MIPSEL32R5-NEXT: jr $ra
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; MIPSEL32R5-NEXT: st.w $w0, 0($5)
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entry:
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%0 = load <4 x i32>, <4 x i32>* %a
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%1 = tail call <4 x i32> @llvm.mips.srli.w(<4 x i32> %0, i32 5)
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%2 = tail call <4 x i32> @llvm.mips.slli.w(<4 x i32> %1, i32 5)
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store <4 x i32> %2, <4 x i32>* %b
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ret void
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}
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; do not fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
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define void @avoid_to_combine_shifts_to_and_mask_type1_long_i32_b(<4 x i32>* %a, <4 x i32>* %b) {
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; MIPSEL64R6-LABEL: avoid_to_combine_shifts_to_and_mask_type1_long_i32_b:
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; MIPSEL64R6: # %bb.0: # %entry
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; MIPSEL64R6-NEXT: ld.w $w0, 0($4)
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; MIPSEL64R6-NEXT: srli.w $w0, $w0, 30
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; MIPSEL64R6-NEXT: slli.w $w0, $w0, 30
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; MIPSEL64R6-NEXT: jr $ra
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; MIPSEL64R6-NEXT: st.w $w0, 0($5)
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;
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; MIPSEL32R5-LABEL: avoid_to_combine_shifts_to_and_mask_type1_long_i32_b:
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; MIPSEL32R5: # %bb.0: # %entry
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; MIPSEL32R5-NEXT: ld.w $w0, 0($4)
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; MIPSEL32R5-NEXT: srli.w $w0, $w0, 30
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; MIPSEL32R5-NEXT: slli.w $w0, $w0, 30
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; MIPSEL32R5-NEXT: jr $ra
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; MIPSEL32R5-NEXT: st.w $w0, 0($5)
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entry:
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%0 = load <4 x i32>, <4 x i32>* %a
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%1 = tail call <4 x i32> @llvm.mips.srli.w(<4 x i32> %0, i32 30)
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%2 = tail call <4 x i32> @llvm.mips.slli.w(<4 x i32> %1, i32 30)
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store <4 x i32> %2, <4 x i32>* %b
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ret void
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}
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