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The recently announced IBM z15 processor implements the architecture already supported as "arch13" in LLVM. This patch adds support for "z15" as an alternate architecture name for arch13. The patch also uses z15 in a number of places where we used arch13 as long as the official name was not yet announced. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372435 91177308-0d34-0410-b5e6-96231b3b80d8
127 lines
2.5 KiB
LLVM
127 lines
2.5 KiB
LLVM
; Combined logical operations involving complement on z15
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;
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; RUN: llc -mcpu=z15 < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; And-with-complement 32-bit.
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define i32 @f1(i32 %dummy, i32 %a, i32 %b) {
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; CHECK-LABEL: f1:
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; CHECK: ncrk %r2, %r3, %r4
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; CHECK: br %r14
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%neg = xor i32 %b, -1
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%ret = and i32 %neg, %a
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ret i32 %ret
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}
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; And-with-complement 64-bit.
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define i64 @f2(i64 %dummy, i64 %a, i64 %b) {
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; CHECK-LABEL: f2:
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; CHECK: ncgrk %r2, %r3, %r4
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; CHECK: br %r14
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%neg = xor i64 %b, -1
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%ret = and i64 %neg, %a
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ret i64 %ret
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}
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; Or-with-complement 32-bit.
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define i32 @f3(i32 %dummy, i32 %a, i32 %b) {
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; CHECK-LABEL: f3:
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; CHECK: ocrk %r2, %r3, %r4
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; CHECK: br %r14
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%neg = xor i32 %b, -1
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%ret = or i32 %neg, %a
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ret i32 %ret
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}
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; Or-with-complement 64-bit.
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define i64 @f4(i64 %dummy, i64 %a, i64 %b) {
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; CHECK-LABEL: f4:
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; CHECK: ocgrk %r2, %r3, %r4
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; CHECK: br %r14
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%neg = xor i64 %b, -1
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%ret = or i64 %neg, %a
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ret i64 %ret
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}
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; NAND 32-bit.
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define i32 @f5(i32 %dummy, i32 %a, i32 %b) {
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; CHECK-LABEL: f5:
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; CHECK: nnrk %r2, %r3, %r4
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; CHECK: br %r14
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%tmp = and i32 %a, %b
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%ret = xor i32 %tmp, -1
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ret i32 %ret
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}
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; NAND 64-bit.
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define i64 @f6(i64 %dummy, i64 %a, i64 %b) {
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; CHECK-LABEL: f6:
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; CHECK: nngrk %r2, %r3, %r4
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; CHECK: br %r14
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%tmp = and i64 %a, %b
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%ret = xor i64 %tmp, -1
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ret i64 %ret
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}
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; NOR 32-bit.
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define i32 @f7(i32 %dummy, i32 %a, i32 %b) {
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; CHECK-LABEL: f7:
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; CHECK: nork %r2, %r3, %r4
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; CHECK: br %r14
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%tmp = or i32 %a, %b
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%ret = xor i32 %tmp, -1
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ret i32 %ret
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}
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; NOR 64-bit.
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define i64 @f8(i64 %dummy, i64 %a, i64 %b) {
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; CHECK-LABEL: f8:
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; CHECK: nogrk %r2, %r3, %r4
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; CHECK: br %r14
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%tmp = or i64 %a, %b
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%ret = xor i64 %tmp, -1
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ret i64 %ret
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}
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; NXOR 32-bit.
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define i32 @f9(i32 %dummy, i32 %a, i32 %b) {
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; CHECK-LABEL: f9:
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; CHECK: nxrk %r2, %r3, %r4
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; CHECK: br %r14
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%tmp = xor i32 %a, %b
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%ret = xor i32 %tmp, -1
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ret i32 %ret
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}
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; NXOR 64-bit.
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define i64 @f10(i64 %dummy, i64 %a, i64 %b) {
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; CHECK-LABEL: f10:
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; CHECK: nxgrk %r2, %r3, %r4
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; CHECK: br %r14
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%tmp = xor i64 %a, %b
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%ret = xor i64 %tmp, -1
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ret i64 %ret
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}
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; Or-with-complement 32-bit of a constant.
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define i32 @f11(i32 %a) {
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; CHECK-LABEL: f11:
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; CHECK: lhi [[REG:%r[0-5]]], -256
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; CHECK: ocrk %r2, [[REG]], %r2
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; CHECK: br %r14
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%neg = xor i32 %a, -1
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%ret = or i32 %neg, -256
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ret i32 %ret
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}
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; Or-with-complement 64-bit of a constant.
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define i64 @f12(i64 %a) {
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; CHECK-LABEL: f12:
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; CHECK: lghi [[REG:%r[0-5]]], -256
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; CHECK: ocgrk %r2, [[REG]], %r2
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; CHECK: br %r14
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%neg = xor i64 %a, -1
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%ret = or i64 %neg, -256
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ret i64 %ret
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}
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