Florian Hahn 6cf02b953e [AArch64][SVE] Asm: Add SVE (Z) Register definitions and parsing support ...

Patch [3/5] in a series to add assembler/disassembler support for AArch64 SVE unpredicated ADD/SUB instructions.

To summarise, this patch adds:

 * SVE register definitions
 * Methods to parse SVE register operands
 * Methods to print SVE register operands
 * RegKind SVEDataVector to distinguish it from other data types like scalar register or Neon vector.
 * k_SVEDataRegister and SVEDataRegOp to describe SVE registers (which will be extended by further patches with e.g. ElementWidth and the shift-extend type).


Patch by Sander De Smalen.

Reviewed by: rengolin

Differential Revision: https://reviews.llvm.org/D39089


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317590 91177308-0d34-0410-b5e6-96231b3b80d8

2017-11-07 16:45:48 +00:00

..

AArch64Disassembler.cpp

[AArch64][SVE] Asm: Add SVE (Z) Register definitions and parsing support

2017-11-07 16:45:48 +00:00

AArch64Disassembler.h

[AArch64, Lanai] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).

2017-01-06 00:30:53 +00:00

AArch64ExternalSymbolizer.cpp

Untabify.

2016-06-20 00:37:41 +00:00

AArch64ExternalSymbolizer.h

Reflect the MC/MCDisassembler split on the include/ level.

2016-01-26 16:44:37 +00:00

CMakeLists.txt

Remove outdated CMake MSVC workaround

2014-06-08 07:37:17 +00:00

LLVMBuild.txt

[AArch64] Add v8.1a atomic instructions

2015-06-02 10:58:41 +00:00