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5a3d179fab
This adds the minimum necessary to support codegen for simple ALU operations on RV32. Prolog and epilog insertion, support for memory operations etc etc follow in future patches. Leave guessInstructionProperties=1 until https://reviews.llvm.org/D37065 is reviewed and lands. Differential Revision: https://reviews.llvm.org/D29933 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316188 91177308-0d34-0410-b5e6-96231b3b80d8
30 lines
1.1 KiB
C++
30 lines
1.1 KiB
C++
//===-- RISCVFrameLowering.cpp - RISCV Frame Information ------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the RISCV implementation of TargetFrameLowering class.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCVFrameLowering.h"
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#include "RISCVSubtarget.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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using namespace llvm;
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bool RISCVFrameLowering::hasFP(const MachineFunction &MF) const { return true; }
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void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {}
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void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {}
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