Alex Bradbury da781c7295 [RISCV] Initial support for function calls ...

Note that this is just enough for simple function call examples to generate 
working code. Support for varargs etc follows in future patches.

Differential Revision: https://reviews.llvm.org/D29936


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317691 91177308-0d34-0410-b5e6-96231b3b80d8

2017-11-08 13:41:21 +00:00

..

AsmParser

[RISCV] RISCVAsmParser: early exit if RISCVOperand isn't immediate as expected

2017-10-19 16:22:51 +00:00

Disassembler

[RISCV] Prepare for the use of variable-sized register classes

2017-10-19 14:29:03 +00:00

InstPrinter

[RISCV] Add support for all RV32I instructions

2017-09-17 14:27:35 +00:00

MCTargetDesc

[RISCV] Prepare for the use of variable-sized register classes

2017-10-19 14:29:03 +00:00

TargetInfo

[RISCV] Add bare-bones RISC-V MCTargetDesc

2016-11-01 23:47:30 +00:00

CMakeLists.txt

[RISCV] Initial codegen support for ALU operations

2017-10-19 21:37:38 +00:00

LLVMBuild.txt

[RISCV] Initial codegen support for ALU operations

2017-10-19 21:37:38 +00:00

RISCV.h

[RISCV] Codegen support for memory operations on global addresses

2017-11-08 13:24:21 +00:00

RISCV.td

[NFCI] Ensure TargetOpcode::* are compatible with guessInstructionProperties=0

2017-11-08 09:26:06 +00:00

RISCVAsmPrinter.cpp

[RISCV] Codegen support for memory operations on global addresses

2017-11-08 13:24:21 +00:00

RISCVCallingConv.td

[RISCV] Codegen for conditional branches

2017-11-08 13:31:40 +00:00

RISCVFrameLowering.cpp

[RISCV] Initial codegen support for ALU operations

2017-10-19 21:37:38 +00:00

RISCVFrameLowering.h

[RISCV] Initial support for function calls

2017-11-08 13:41:21 +00:00

RISCVInstrFormats.td

[RISCV] Prepare for the use of variable-sized register classes

2017-10-19 14:29:03 +00:00

RISCVInstrInfo.cpp

[RISCV] Initial support for function calls

2017-11-08 13:41:21 +00:00

RISCVInstrInfo.h

[RISCV] Codegen for conditional branches

2017-11-08 13:31:40 +00:00

RISCVInstrInfo.td

[RISCV] Initial support for function calls

2017-11-08 13:41:21 +00:00

RISCVISelDAGToDAG.cpp

[RISCV] Initial codegen support for ALU operations

2017-10-19 21:37:38 +00:00

RISCVISelLowering.cpp

[RISCV] Initial support for function calls

2017-11-08 13:41:21 +00:00

RISCVISelLowering.h

[RISCV] Initial support for function calls

2017-11-08 13:41:21 +00:00

RISCVMCInstLower.cpp

[RISCV] Initial support for function calls

2017-11-08 13:41:21 +00:00

RISCVRegisterInfo.cpp

[RISCV] Initial support for function calls

2017-11-08 13:41:21 +00:00

RISCVRegisterInfo.h

[RISCV] Initial support for function calls

2017-11-08 13:41:21 +00:00

RISCVRegisterInfo.td

[RISCV] Initial codegen support for ALU operations

2017-10-19 21:37:38 +00:00

RISCVSubtarget.cpp

[RISCV] Initial codegen support for ALU operations

2017-10-19 21:37:38 +00:00

RISCVSubtarget.h

[RISCV] Initial codegen support for ALU operations

2017-10-19 21:37:38 +00:00

RISCVTargetMachine.cpp

[RISCV] Initial codegen support for ALU operations

2017-10-19 21:37:38 +00:00

RISCVTargetMachine.h

[RISCV] Initial codegen support for ALU operations

2017-10-19 21:37:38 +00:00