Files
archived-llvm/utils/TableGen
Florian Hahn 8aa5d0fb6a [AArch64][SVE] Asm: Extend EnforceVectorSubVectorTypeIs to distinguish Scalable Vectors
Patch [1/5] in a series to add assembler/disassembler support for AArch64 SVE
unpredicated ADD/SUB instructions.

Patch by Sander De Smalen.

Reviewed by: rengolin

Differential Revision: https://reviews.llvm.org/D39087


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317564 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-07 10:43:56 +00:00
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2017-10-06 15:33:55 +00:00