mirror of
https://github.com/RPCS3/llvm.git
synced 2026-01-31 01:25:19 +01:00
93f5fcdff3
Since register classes and banks are already printed with the register definition, don't print it at the end of every instruction anymore. This follows MIR in this regard and is another step to the unification of the two formats. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322086 91177308-0d34-0410-b5e6-96231b3b80d8
25 lines
1.1 KiB
LLVM
25 lines
1.1 KiB
LLVM
; RUN: llc -debug-only=machine-scheduler -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs %s -o - 2>&1| FileCheck -check-prefix=SI-NOHSA -check-prefix=FUNC -check-prefix=DEBUG %s
|
|
target datalayout = "A5"
|
|
; REQUIRES: asserts
|
|
|
|
; Verify that the extload generated from %eval has the default
|
|
; alignment size (2) corresponding to the underlying memory size (i16)
|
|
; size and not 4 corresponding to the sign-extended size (i32).
|
|
|
|
; DEBUG: {{^}}# Machine code for function extload_align:
|
|
; DEBUG: mem:LD2[<unknown>(addrspace=5)]
|
|
; DEBUG: {{^}}# End machine code for function extload_align.
|
|
|
|
define amdgpu_kernel void @extload_align(i32 addrspace(5)* %out, i32 %index) #0 {
|
|
%v0 = alloca [4 x i16], addrspace(5)
|
|
%a1 = getelementptr inbounds [4 x i16], [4 x i16] addrspace(5)* %v0, i32 0, i32 0
|
|
%a2 = getelementptr inbounds [4 x i16], [4 x i16] addrspace(5)* %v0, i32 0, i32 1
|
|
store i16 0, i16 addrspace(5)* %a1
|
|
store i16 1, i16 addrspace(5)* %a2
|
|
%a = getelementptr inbounds [4 x i16], [4 x i16] addrspace(5)* %v0, i32 0, i32 %index
|
|
%val = load i16, i16 addrspace(5)* %a
|
|
%eval = sext i16 %val to i32
|
|
store i32 %eval, i32 addrspace(5)* %out
|
|
ret void
|
|
}
|