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96ed12f5f3
r322086 removed the trailing information describing reg classes for each register. This patch adds printing reg classes next to every register when individual operands/instructions/basic blocks are printed. In the case of dumping MIR or printing a full function, by default don't print it. Differential Revision: https://reviews.llvm.org/D42239 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322867 91177308-0d34-0410-b5e6-96231b3b80d8
129 lines
4.3 KiB
YAML
129 lines
4.3 KiB
YAML
# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=swift -run-pass machine-scheduler -enable-misched -verify-misched \
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# RUN: -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_SWIFT
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# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-a9 -run-pass machine-scheduler -enable-misched -verify-misched \
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# RUN: -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_A9
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# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52 -run-pass machine-scheduler -enable-misched -verify-misched \
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# RUN: -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_R52
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# REQUIRES: asserts
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--- |
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; ModuleID = 'foo.ll'
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source_filename = "foo.ll"
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "arm---eabi"
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define i64 @foo(i16 signext %a, i16 signext %b) {
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entry:
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%d = mul nsw i16 %a, %a
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%e = mul nsw i16 %b, %b
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%f = add nuw nsw i16 %e, %d
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%c = zext i16 %f to i32
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%mul8 = mul nsw i32 %c, %c
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%mul9 = mul nsw i32 %mul8, %mul8
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%add10 = add nuw nsw i32 %mul9, %mul8
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%conv1130 = zext i32 %add10 to i64
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%mul12 = mul nuw nsw i64 %conv1130, %conv1130
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%mul13 = mul nsw i64 %mul12, %mul12
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%add14 = add nuw nsw i64 %mul13, %mul12
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ret i64 %add14
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}
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# CHECK: ********** MI Scheduling **********
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# CHECK: SU(2): %2:gpr = SMULBB %1:gpr, %1:gpr, 14, %noreg
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# CHECK_A9: Latency : 2
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# CHECK_SWIFT: Latency : 4
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# CHECK_R52: Latency : 4
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#
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# CHECK: SU(3): %3:gprnopc = SMLABB %0:gprnopc, %0:gprnopc, %2:gpr, 14, %noreg
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# CHECK_A9: Latency : 2
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# CHECK_SWIFT: Latency : 4
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# CHECK_R52: Latency : 4
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#
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# CHECK: SU(4): %4:gprnopc = UXTH %3:gprnopc, 0, 14, %noreg
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# CHECK_A9: Latency : 1
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# CHECK_SWIFT: Latency : 1
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# CHECK_R52: Latency : 3
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#
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# CHECK: SU(5): %5:gprnopc = MUL %4:gprnopc, %4:gprnopc, 14, %noreg, %noreg
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# CHECK_A9: Latency : 2
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# CHECK_SWIFT: Latency : 4
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# CHECK_R52: Latency : 4
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#
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# CHECK: SU(6): %6:gprnopc = MLA %5:gprnopc, %5:gprnopc, %5:gprnopc, 14, %noreg, %noreg
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# CHECK_A9: Latency : 2
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# CHECK_SWIFT: Latency : 4
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# CHECK_R52: Latency : 4
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#
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# CHECK: SU(7): %7:gprnopc, %8:gprnopc = UMULL %6:gprnopc, %6:gprnopc, 14, %noreg, %noreg
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# CHECK_A9: Latency : 3
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# CHECK_SWIFT: Latency : 5
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# CHECK_R52: Latency : 4
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#
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# CHECK: SU(11): %13:gpr, %14:gprnopc = UMLAL %6:gprnopc, %6:gprnopc, %13:gpr, %14:gprnopc, 14, %noreg, %noreg
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# CHECK_SWIFT: Latency : 7
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# CHECK_A9: Latency : 3
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# CHECK_R52: Latency : 4
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# CHECK: ** ScheduleDAGMILive::schedule picking next node
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...
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---
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name: foo
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alignment: 2
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprnopc }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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- { id: 3, class: gprnopc }
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- { id: 4, class: gprnopc }
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- { id: 5, class: gprnopc }
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- { id: 6, class: gprnopc }
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- { id: 7, class: gprnopc }
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- { id: 8, class: gprnopc }
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- { id: 9, class: gpr }
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- { id: 10, class: gprnopc }
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- { id: 11, class: gprnopc }
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- { id: 12, class: gprnopc }
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- { id: 13, class: gpr }
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- { id: 14, class: gprnopc }
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liveins:
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- { reg: '%r0', virtual-reg: '%0' }
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- { reg: '%r1', virtual-reg: '%1' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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body: |
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bb.0.entry:
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liveins: %r0, %r1
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%1 = COPY %r1
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%0 = COPY %r0
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%2 = SMULBB %1, %1, 14, %noreg
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%3 = SMLABB %0, %0, %2, 14, %noreg
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%4 = UXTH %3, 0, 14, %noreg
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%5 = MUL %4, %4, 14, %noreg, %noreg
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%6 = MLA %5, %5, %5, 14, %noreg, %noreg
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%7, %8 = UMULL %6, %6, 14, %noreg, %noreg
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%13, %10 = UMULL %7, %7, 14, %noreg, %noreg
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%11 = MLA %7, %8, %10, 14, %noreg, %noreg
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%14 = MLA %7, %8, %11, 14, %noreg, %noreg
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%13, %14 = UMLAL %6, %6, %13, %14, 14, %noreg, %noreg
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%r0 = COPY %13
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%r1 = COPY %14
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BX_RET 14, %noreg, implicit %r0, implicit %r1
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...
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