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f31ac9d1e8
Summary: Predicate<> now has a field to indicate how often it must be recomputed. Currently, there are two frequencies, per-module (RecomputePerFunction==0) and per-function (RecomputePerFunction==1). Per-function predicates are currently recomputed more frequently than necessary since the only predicate in this category is cheap to test. Per-module predicates are now computed in getSubtargetImpl() while per-function predicates are computed in selectImpl(). Tablegen now manages the PredicateBitset internally. It should only be necessary to add the required includes. Also fixed a problem revealed by the test case where constrainSelectedInstRegOperands() would attempt to tie operands that BuildMI had already tied. Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D32491 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301750 91177308-0d34-0410-b5e6-96231b3b80d8
86 lines
2.9 KiB
C++
86 lines
2.9 KiB
C++
//===- llvm/CodeGen/GlobalISel/InstructionSelector.cpp -----------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the InstructionSelector class.
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
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#include "llvm/CodeGen/GlobalISel/Utils.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#define DEBUG_TYPE "instructionselector"
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using namespace llvm;
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InstructionSelector::InstructionSelector() {}
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bool InstructionSelector::constrainSelectedInstRegOperands(
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MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI,
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const RegisterBankInfo &RBI) const {
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MachineBasicBlock &MBB = *I.getParent();
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MachineFunction &MF = *MBB.getParent();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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for (unsigned OpI = 0, OpE = I.getNumExplicitOperands(); OpI != OpE; ++OpI) {
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MachineOperand &MO = I.getOperand(OpI);
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// There's nothing to be done on non-register operands.
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if (!MO.isReg())
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continue;
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DEBUG(dbgs() << "Converting operand: " << MO << '\n');
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assert(MO.isReg() && "Unsupported non-reg operand");
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unsigned Reg = MO.getReg();
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// Physical registers don't need to be constrained.
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if (TRI.isPhysicalRegister(Reg))
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continue;
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// Register operands with a value of 0 (e.g. predicate operands) don't need
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// to be constrained.
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if (Reg == 0)
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continue;
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// If the operand is a vreg, we should constrain its regclass, and only
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// insert COPYs if that's impossible.
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// constrainOperandRegClass does that for us.
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MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(),
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Reg, OpI));
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// Tie uses to defs as indicated in MCInstrDesc if this hasn't already been
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// done.
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if (MO.isUse()) {
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int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO);
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if (DefIdx != -1 && !I.isRegTiedToUseOperand(DefIdx))
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I.tieOperands(DefIdx, OpI);
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}
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}
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return true;
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}
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bool InstructionSelector::isOperandImmEqual(
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const MachineOperand &MO, int64_t Value,
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const MachineRegisterInfo &MRI) const {
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if (MO.getReg())
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if (auto VRegVal = getConstantVRegVal(MO.getReg(), MRI))
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return *VRegVal == Value;
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return false;
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}
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bool InstructionSelector::isObviouslySafeToFold(MachineInstr &MI) const {
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return !MI.mayLoadOrStore() && !MI.hasUnmodeledSideEffects() &&
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MI.implicit_operands().begin() == MI.implicit_operands().end();
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}
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