archived-llvm

AsmParser

Reverted r319315 because of unused functions (due to PPR not yet being

2017-11-29 15:14:39 +00:00

Disassembler

Reverted r319315 because of unused functions (due to PPR not yet being

2017-11-29 15:14:39 +00:00

InstPrinter

[AArch64][SVE] Asm: Add SVE (Z) Register definitions and parsing support

2017-11-07 16:45:48 +00:00

MCTargetDesc

[AArch64] Allow using emulated tls on platforms other than ELF

2017-12-04 09:09:04 +00:00

TargetInfo

Add backend name to Target to enable runtime info to be fed back into TableGen

2017-11-15 23:55:44 +00:00

Utils

[AArch64] Add support for dllimport of values and functions

2017-10-25 07:25:18 +00:00

AArch64.h

[AArch64] Avoid SIMD interleaved store instruction for Exynos.

2017-12-08 00:58:49 +00:00

AArch64.td

AArch64: Enable AES instruction fusion on Cyclone.

2017-10-17 21:46:15 +00:00

AArch64A53Fix835769.cpp

Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering

2017-11-08 01:01:31 +00:00

AArch64A57FPLoadBalancing.cpp

[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.

2017-12-07 10:40:31 +00:00

AArch64AdvSIMDScalarPass.cpp

Use StringRef in Pass/PassManager APIs (NFC)

2016-10-01 02:56:57 +00:00

AArch64AsmPrinter.cpp

Fix a bunch more layering of CodeGen headers that are in Target

2017-11-17 01:07:10 +00:00

AArch64CallingConvention.h

Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering

2017-11-08 01:01:31 +00:00

AArch64CallingConvention.td

AArch64: support SwiftCC properly on AAPCS64

2017-09-22 04:31:44 +00:00

AArch64CallLowering.cpp

[GlobalISel][IRTranslator] Fix crash during translation of zero sized loads/stores/args/returns.

2017-11-30 20:06:02 +00:00

AArch64CallLowering.h

GlobalISel (AArch64): fix ABI at border between GPRs and SP.

2017-08-21 21:56:11 +00:00

AArch64CleanupLocalDynamicTLSPass.cpp

fix trivial typos in comments; NFC

2017-07-03 06:32:59 +00:00

AArch64CollectLOH.cpp

Fix a bunch more layering of CodeGen headers that are in Target

2017-11-17 01:07:10 +00:00

AArch64CondBrTuning.cpp

Fix a bunch more layering of CodeGen headers that are in Target

2017-11-17 01:07:10 +00:00

AArch64ConditionalCompares.cpp

[CodeGen] Unify MBB reference format in both MIR and debug output

2017-12-04 17:18:51 +00:00

AArch64ConditionOptimizer.cpp

[CodeGen] Unify MBB reference format in both MIR and debug output

2017-12-04 17:18:51 +00:00

AArch64DeadRegisterDefinitionsPass.cpp

Fix a bunch more layering of CodeGen headers that are in Target

2017-11-17 01:07:10 +00:00

AArch64ExpandPseudoInsts.cpp

Fix a bunch more layering of CodeGen headers that are in Target

2017-11-17 01:07:10 +00:00

AArch64FalkorHWPFFix.cpp

[CodeGen] Rename functions PrintReg* to printReg*

2017-11-28 12:42:37 +00:00

AArch64FastISel.cpp

[AArch64] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).

2017-07-25 23:51:02 +00:00

AArch64FrameLowering.cpp

[CodeGen] Always use printReg to print registers in both MIR and debug

2017-11-30 16:12:24 +00:00

AArch64FrameLowering.h

Move TargetFrameLowering.h to CodeGen where it's implemented

2017-11-03 22:32:11 +00:00

AArch64GenRegisterBankInfo.def

[AArch64][RegisterBankInfo] Teach instruction mapping about gpr32 -> fpr16 cross copies

2017-11-18 04:28:56 +00:00

AArch64InstrAtomics.td

[globalisel][tablegen] Add support for relative AtomicOrderings

2017-11-30 21:05:59 +00:00

AArch64InstrFormats.td

[globalisel][tablegen] Import stores and allow GISel to automatically substitute zero regs like WZR/XZR/$zero.

2017-10-23 18:19:24 +00:00

AArch64InstrInfo.cpp

[MachineOutliner] Fix offset overflow check

2017-12-07 21:51:43 +00:00

AArch64InstrInfo.h

Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering

2017-11-08 01:01:31 +00:00

AArch64InstrInfo.td

[AArch64] Mark mrs of TPIDR_EL0 (thread pointer) as *having* side effects.

2017-11-21 18:08:34 +00:00

AArch64InstructionSelector.cpp

Revert r319691: [globalisel][tablegen] Split atomic load/store into separate opcode and enable for AArch64.

2017-12-05 05:52:07 +00:00

AArch64ISelDAGToDAG.cpp

[AArch64] Avoid selecting XZR inline ASM memory operand

2017-07-14 21:46:16 +00:00

AArch64ISelLowering.cpp

[AArch64] Do not abort if overflow check does not use EQ or NE.

2017-12-05 21:33:12 +00:00

AArch64ISelLowering.h

[ARM][AArch64][DAG] Reenable post-legalize store merge

2017-12-06 15:30:13 +00:00

AArch64LegalizerInfo.cpp

Revert r319691: [globalisel][tablegen] Split atomic load/store into separate opcode and enable for AArch64.

2017-12-05 05:52:07 +00:00

AArch64LegalizerInfo.h

[aarch64][globalisel] Define G_ATOMIC_CMPXCHG and G_ATOMICRMW_* and make them legal

2017-11-28 20:21:15 +00:00

AArch64LoadStoreOptimizer.cpp

[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.

2017-12-07 10:40:31 +00:00

AArch64MachineFunctionInfo.h

[AArch64] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).

2017-07-25 23:51:02 +00:00

AArch64MacroFusion.cpp

Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering

2017-11-08 01:01:31 +00:00

AArch64MacroFusion.h

Recommit rL305677: [CodeGen] Add generic MacroFusion pass

2017-06-19 12:53:31 +00:00

AArch64MCInstLower.cpp

Fix a bunch more layering of CodeGen headers that are in Target

2017-11-17 01:07:10 +00:00

AArch64MCInstLower.h

[COFF, ARM64] Add support for Windows ARM64 COFF format

2017-06-27 23:58:19 +00:00

AArch64PBQPRegAlloc.cpp

[CodeGen] Rename functions PrintReg* to printReg*

2017-11-28 12:42:37 +00:00

AArch64PBQPRegAlloc.h

[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).

2017-06-01 23:25:02 +00:00

AArch64PerfectShuffle.h

Canonicalize header guards into a common format.

2014-08-13 16:26:38 +00:00

AArch64PromoteConstant.cpp

[AArch64] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).

2017-07-25 23:51:02 +00:00

AArch64RedundantCopyElimination.cpp

[CodeGen] Unify MBB reference format in both MIR and debug output

2017-12-04 17:18:51 +00:00

AArch64RegisterBankInfo.cpp

[AArch64] Map G_LOAD on FPR when the definition goes to a copy to FPR

2017-11-18 04:28:59 +00:00

AArch64RegisterBankInfo.h

[AArch64][RegisterBankInfo] Add mapping for G_FPEXT.

2017-11-02 23:38:19 +00:00

AArch64RegisterBanks.td

[aarch64][globalisel] Register banks and classes should have distinct names.

2017-10-18 00:12:43 +00:00

AArch64RegisterInfo.cpp

Move TargetFrameLowering.h to CodeGen where it's implemented

2017-11-03 22:32:11 +00:00

AArch64RegisterInfo.h

AArch64: Enable post-ra liveness updates

2016-12-16 23:55:43 +00:00

AArch64RegisterInfo.td

Reverted r319315 because of unused functions (due to PPR not yet being

2017-11-29 15:14:39 +00:00

AArch64SchedA53.td

[AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models.

2017-11-07 15:03:11 +00:00

AArch64SchedA57.td

[AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models.

2017-11-07 15:03:11 +00:00

AArch64SchedA57WriteRes.td

[AArch64] Cortex-A57 FDIV/FSQRT scheduling fix (W-unit)

2016-12-23 12:51:41 +00:00

AArch64SchedCyclone.td

[AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models.

2017-11-07 15:03:11 +00:00

AArch64SchedFalkor.td

[AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models.

2017-11-07 15:03:11 +00:00

AArch64SchedFalkorDetails.td

[AArch64][Falkor] Remove some non-existent opcodes from sched detail regexes. NFC.

2017-06-23 21:59:09 +00:00

AArch64SchedKryo.td

[AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models.

2017-11-07 15:03:11 +00:00

AArch64SchedKryoDetails.td

[AArch64][Kryo] Add missing write latency for LDAXP, LDXP second destination.

2017-06-19 21:57:42 +00:00

AArch64SchedM1.td

[AArch64] Adjust the cost model for Exynos M1 and M2

2017-11-22 22:48:50 +00:00

AArch64SchedThunderX2T99.td

[AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models.

2017-11-07 15:03:11 +00:00

AArch64SchedThunderX.td

[AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models.

2017-11-07 15:03:11 +00:00

AArch64Schedule.td

CodeGen: Use MachineInstr& in TargetInstrInfo, NFC

2016-06-30 00:01:54 +00:00

AArch64SelectionDAGInfo.cpp

[AArch64] Drive-by cleanup, make this code shorter. NFCI.

2017-03-22 23:37:58 +00:00

AArch64SelectionDAGInfo.h

Pass DebugLoc and SDLoc by const ref.

2016-06-12 15:39:02 +00:00

AArch64StorePairSuppress.cpp

Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering

2017-11-08 01:01:31 +00:00

AArch64Subtarget.cpp

[aarch64][globalisel] Define G_ATOMIC_CMPXCHG and G_ATOMICRMW_* and make them legal

2017-11-28 20:21:15 +00:00

AArch64Subtarget.h

Fix a bunch more layering of CodeGen headers that are in Target

2017-11-17 01:07:10 +00:00

AArch64SVEInstrInfo.td

[AArch64][SVE] Asm: Add support for (ADD|SUB)_ZZZ

2017-11-07 16:58:13 +00:00

AArch64SystemOperands.td

[AArch64] IDSAR6 register assembler support

2017-08-31 08:36:45 +00:00

AArch64TargetMachine.cpp

[AArch64] Avoid SIMD interleaved store instruction for Exynos.

2017-12-08 00:58:49 +00:00

AArch64TargetMachine.h

Revert "TargetMachine: Merge TargetMachine and LLVMTargetMachine"

2017-10-12 22:57:28 +00:00

AArch64TargetObjectFile.cpp

Move Object format code to lib/BinaryFormat.

2017-06-07 03:48:56 +00:00

AArch64TargetObjectFile.h

Fix a bunch more layering of CodeGen headers that are in Target

2017-11-17 01:07:10 +00:00

AArch64TargetTransformInfo.cpp

Fix a bunch more layering of CodeGen headers that are in Target

2017-11-17 01:07:10 +00:00

AArch64TargetTransformInfo.h

[AArch64] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).

2017-07-25 23:51:02 +00:00

AArch64VectorByElementOpt.cpp

[AArch64] Avoid SIMD interleaved store instruction for Exynos.

2017-12-08 00:58:49 +00:00

CMakeLists.txt

[GlobalISel] Make GlobalISel a non-optional library.

2017-08-03 21:52:25 +00:00

LLVMBuild.txt

[AArch64] Plug the beginning of the GlobalISel pipeline.

2016-02-11 19:35:06 +00:00

SVEInstrFormats.td

Test commit

2017-11-13 09:57:20 +00:00