Alex Bradbury e65af32d44 [RISCV] MC layer support for the standard RV32F instruction set extension ...

The most interesting part of this patch is probably the handling of 
rounding mode arguments. Sadly, the RISC-V assembler handles floating point 
rounding modes as a special "argument" when it would be more consistent to 
handle them like the atomics, opcode suffixes. This patch supports parsing 
this optional parameter, using InstAlias to allow parsing these floating point 
instructions when no rounding mode is specified.

Differential Revision: https://reviews.llvm.org/D39893


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320020 91177308-0d34-0410-b5e6-96231b3b80d8

2017-12-07 10:26:05 +00:00

..

CMakeLists.txt

…

LLVMBuild.txt

…

RISCVInstPrinter.cpp

[RISCV] MC layer support for the standard RV32F instruction set extension

2017-12-07 10:26:05 +00:00

RISCVInstPrinter.h

[RISCV] MC layer support for the standard RV32F instruction set extension

2017-12-07 10:26:05 +00:00