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e65af32d44
The most interesting part of this patch is probably the handling of rounding mode arguments. Sadly, the RISC-V assembler handles floating point rounding modes as a special "argument" when it would be more consistent to handle them like the atomics, opcode suffixes. This patch supports parsing this optional parameter, using InstAlias to allow parsing these floating point instructions when no rounding mode is specified. Differential Revision: https://reviews.llvm.org/D39893 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320020 91177308-0d34-0410-b5e6-96231b3b80d8
80 lines
2.4 KiB
C++
80 lines
2.4 KiB
C++
//===-- RISCVInstPrinter.cpp - Convert RISCV MCInst to asm syntax ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This class prints an RISCV MCInst to a .s file.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCVInstPrinter.h"
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#include "MCTargetDesc/RISCVBaseInfo.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/FormattedStream.h"
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using namespace llvm;
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#define DEBUG_TYPE "asm-printer"
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// Include the auto-generated portion of the assembly writer.
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#define PRINT_ALIAS_INSTR
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#include "RISCVGenAsmWriter.inc"
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void RISCVInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
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StringRef Annot, const MCSubtargetInfo &STI) {
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if (!printAliasInstr(MI, O))
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printInstruction(MI, O);
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printAnnotation(O, Annot);
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}
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void RISCVInstPrinter::printRegName(raw_ostream &O, unsigned RegNo) const {
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O << getRegisterName(RegNo);
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}
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void RISCVInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O, const char *Modifier) {
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assert((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported");
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const MCOperand &MO = MI->getOperand(OpNo);
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if (MO.isReg()) {
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printRegName(O, MO.getReg());
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return;
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}
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if (MO.isImm()) {
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O << MO.getImm();
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return;
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}
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assert(MO.isExpr() && "Unknown operand kind in printOperand");
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MO.getExpr()->print(O, &MAI);
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}
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void RISCVInstPrinter::printFenceArg(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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unsigned FenceArg = MI->getOperand(OpNo).getImm();
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if ((FenceArg & RISCVFenceField::I) != 0)
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O << 'i';
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if ((FenceArg & RISCVFenceField::O) != 0)
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O << 'o';
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if ((FenceArg & RISCVFenceField::R) != 0)
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O << 'r';
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if ((FenceArg & RISCVFenceField::W) != 0)
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O << 'w';
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}
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void RISCVInstPrinter::printFRMArg(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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auto FRMArg =
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static_cast<RISCVFPRndMode::RoundingMode>(MI->getOperand(OpNo).getImm());
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O << RISCVFPRndMode::roundingModeToString(FRMArg);
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}
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