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archived-llvm/test/CodeGen/WebAssembly
Heejin Ahn 4b49e7df3d [WebAssembly] Support for atomic fences
Summary:
This adds support for translation of LLVM IR fence instruction. We
convert a singlethread fence to a pseudo compiler barrier which becomes
0 instructions in final binary, and a thread fence to an idempotent
atomicrmw instruction to a memory address.

Reviewers: dschuff, jfb, sunfish, tlively

Subscribers: sbc100, jgravelle-google, llvm-commits

Differential Revision: https://reviews.llvm.org/D50277

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361884 91177308-0d34-0410-b5e6-96231b3b80d8
2019-05-28 22:09:12 +00:00
..
2019-04-30 19:17:59 +00:00