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vp: ignore swizzles on ARL opcode (#4)
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@@ -189,9 +189,9 @@ namespace rsx
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return (instruction.data.d2.iaddrh << 3) | instruction.data.d3.iaddrl;
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}
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integer_expr<1> address_register()
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integer_expr<4> address_register()
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{
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return{ context.address_register(instruction.data.d0.addr_reg_sel_1), context.address_mask(instruction.data.d0.addr_swz), true, 4 };
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return context.address_register(instruction.data.d0.addr_reg_sel_1);
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}
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float_point_expr<4> swizzle_as_dst(float_point_expr<4> arg) const
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@@ -667,7 +667,7 @@ namespace rsx
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case (u32)vec_opcode_t::max: return set_dst(base::max(src_swizzled_as_dst(0), src_swizzled_as_dst(1)));
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case (u32)vec_opcode_t::slt: return set_dst(compare(base::compare_function::less, src_swizzled_as_dst(0), src_swizzled_as_dst(1)));
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case (u32)vec_opcode_t::sge: return set_dst(compare(base::compare_function::greater_equal, src_swizzled_as_dst(0), src_swizzled_as_dst(1)));
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case (u32)vec_opcode_t::arl: return typename base::writer_t{} += address_register() = base::clamp(integer_t<1>::ctor(src(0).x()), -512, 511);
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case (u32)vec_opcode_t::arl: return typename base::writer_t{} += address_register() = base::clamp(integer_t<4>::ctor(src(0)), -512, 511);
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case (u32)vec_opcode_t::frc: return set_dst(base::fract(src_swizzled_as_dst(0)));
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case (u32)vec_opcode_t::flr: return set_dst(base::floor(src_swizzled_as_dst(0)));;
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case (u32)vec_opcode_t::seq: return set_dst(compare(base::compare_function::equal, src_swizzled_as_dst(0), src_swizzled_as_dst(1)));
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