2012-07-07 04:00:00 +00:00
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//===-- llvm/MC/MCSchedule.h - Scheduling -----------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the classes used to describe a subtarget's machine model
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// for scheduling and other instruction cost heuristics.
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//
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//===----------------------------------------------------------------------===//
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2013-01-10 00:45:19 +00:00
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#ifndef LLVM_MC_MCSCHEDULE_H
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#define LLVM_MC_MCSCHEDULE_H
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2012-07-07 04:00:00 +00:00
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#include "llvm/Support/DataTypes.h"
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#include <cassert>
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2012-07-07 04:00:00 +00:00
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namespace llvm {
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struct InstrItinerary;
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/// Define a kind of processor resource that will be modeled by the scheduler.
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struct MCProcResourceDesc {
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#ifndef NDEBUG
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const char *Name;
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#endif
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unsigned NumUnits; // Number of resource of this kind
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unsigned SuperIdx; // Index of the resources kind that contains this kind.
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// Buffered resources may be consumed at some indeterminate cycle after
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// dispatch (e.g. for instructions that may issue out-of-order). Unbuffered
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// resources always consume their resource some fixed number of cycles after
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// dispatch (e.g. for instruction interlocking that may stall the pipeline).
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bool IsBuffered;
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bool operator==(const MCProcResourceDesc &Other) const {
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return NumUnits == Other.NumUnits && SuperIdx == Other.SuperIdx
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&& IsBuffered == Other.IsBuffered;
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}
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};
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/// Identify one of the processor resource kinds consumed by a particular
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/// scheduling class for the specified number of cycles.
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struct MCWriteProcResEntry {
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unsigned ProcResourceIdx;
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unsigned Cycles;
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bool operator==(const MCWriteProcResEntry &Other) const {
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return ProcResourceIdx == Other.ProcResourceIdx && Cycles == Other.Cycles;
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}
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};
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/// Specify the latency in cpu cycles for a particular scheduling class and def
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/// index. -1 indicates an invalid latency. Heuristics would typically consider
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/// an instruction with invalid latency to have infinite latency. Also identify
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/// the WriteResources of this def. When the operand expands to a sequence of
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/// writes, this ID is the last write in the sequence.
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struct MCWriteLatencyEntry {
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int Cycles;
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unsigned WriteResourceID;
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bool operator==(const MCWriteLatencyEntry &Other) const {
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return Cycles == Other.Cycles && WriteResourceID == Other.WriteResourceID;
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}
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};
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/// Specify the number of cycles allowed after instruction issue before a
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/// particular use operand reads its registers. This effectively reduces the
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/// write's latency. Here we allow negative cycles for corner cases where
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/// latency increases. This rule only applies when the entry's WriteResource
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/// matches the write's WriteResource.
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///
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/// MCReadAdvanceEntries are sorted first by operand index (UseIdx), then by
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/// WriteResourceIdx.
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struct MCReadAdvanceEntry {
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unsigned UseIdx;
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unsigned WriteResourceID;
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int Cycles;
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bool operator==(const MCReadAdvanceEntry &Other) const {
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return UseIdx == Other.UseIdx && WriteResourceID == Other.WriteResourceID
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&& Cycles == Other.Cycles;
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}
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};
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/// Summarize the scheduling resources required for an instruction of a
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/// particular scheduling class.
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///
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/// Defined as an aggregate struct for creating tables with initializer lists.
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struct MCSchedClassDesc {
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static const unsigned short InvalidNumMicroOps = UINT16_MAX;
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static const unsigned short VariantNumMicroOps = UINT16_MAX - 1;
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#ifndef NDEBUG
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const char* Name;
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#endif
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unsigned short NumMicroOps;
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bool BeginGroup;
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bool EndGroup;
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unsigned WriteProcResIdx; // First index into WriteProcResTable.
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unsigned NumWriteProcResEntries;
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unsigned WriteLatencyIdx; // First index into WriteLatencyTable.
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unsigned NumWriteLatencyEntries;
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unsigned ReadAdvanceIdx; // First index into ReadAdvanceTable.
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unsigned NumReadAdvanceEntries;
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bool isValid() const {
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return NumMicroOps != InvalidNumMicroOps;
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}
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bool isVariant() const {
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return NumMicroOps == VariantNumMicroOps;
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}
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};
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/// Machine model for scheduling, bundling, and heuristics.
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///
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/// The machine model directly provides basic information about the
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/// microarchitecture to the scheduler in the form of properties. It also
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/// optionally refers to scheduler resource tables and itinerary
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/// tables. Scheduler resource tables model the latency and cost for each
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/// instruction type. Itinerary tables are an independant mechanism that
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/// provides a detailed reservation table describing each cycle of instruction
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/// execution. Subtargets may define any or all of the above categories of data
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/// depending on the type of CPU and selected scheduler.
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class MCSchedModel {
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public:
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static MCSchedModel DefaultSchedModel; // For unknown processors.
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// IssueWidth is the maximum number of instructions that may be scheduled in
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// the same per-cycle group.
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unsigned IssueWidth;
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static const unsigned DefaultIssueWidth = 1;
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// MinLatency is the minimum latency between a register write
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// followed by a data dependent read. This determines which
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// instructions may be scheduled in the same per-cycle group. This
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// is distinct from *expected* latency, which determines the likely
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// critical path but does not guarantee a pipeline
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// hazard. MinLatency can always be overridden by the number of
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// InstrStage cycles.
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//
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// (-1) Standard in-order processor.
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// Use InstrItinerary OperandCycles as MinLatency.
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// If no OperandCycles exist, then use the cycle of the last InstrStage.
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//
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// (0) Out-of-order processor, or in-order with bundled dependencies.
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// RAW dependencies may be dispatched in the same cycle.
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// Optional InstrItinerary OperandCycles provides expected latency.
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//
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// (>0) In-order processor with variable latencies.
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// Use the greater of this value or the cycle of the last InstrStage.
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// Optional InstrItinerary OperandCycles provides expected latency.
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// TODO: can't yet specify both min and expected latency per operand.
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int MinLatency;
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static const int DefaultMinLatency = -1;
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// LoadLatency is the expected latency of load instructions.
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//
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// If MinLatency >= 0, this may be overriden for individual load opcodes by
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// InstrItinerary OperandCycles.
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unsigned LoadLatency;
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static const unsigned DefaultLoadLatency = 4;
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// HighLatency is the expected latency of "very high latency" operations.
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// See TargetInstrInfo::isHighLatencyDef().
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// By default, this is set to an arbitrarily high number of cycles
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// likely to have some impact on scheduling heuristics.
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// If MinLatency >= 0, this may be overriden by InstrItinData OperandCycles.
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unsigned HighLatency;
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static const unsigned DefaultHighLatency = 10;
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// ILPWindow is the number of cycles that the scheduler effectively ignores
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// before attempting to hide latency. This should be zero for in-order cpus to
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// always hide expected latency. For out-of-order cpus, it may be tweaked as
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// desired to roughly approximate instruction buffers. The actual threshold is
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// not very important for an OOO processor, as long as it isn't too high. A
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// nonzero value helps avoid rescheduling to hide latency when its is fairly
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// obviously useless and makes register pressure heuristics more effective.
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unsigned ILPWindow;
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static const unsigned DefaultILPWindow = 0;
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// MispredictPenalty is the typical number of extra cycles the processor
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// takes to recover from a branch misprediction.
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unsigned MispredictPenalty;
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static const unsigned DefaultMispredictPenalty = 10;
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private:
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unsigned ProcID;
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const MCProcResourceDesc *ProcResourceTable;
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const MCSchedClassDesc *SchedClassTable;
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unsigned NumProcResourceKinds;
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unsigned NumSchedClasses;
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// Instruction itinerary tables used by InstrItineraryData.
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friend class InstrItineraryData;
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const InstrItinerary *InstrItineraries;
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public:
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// Default's must be specified as static const literals so that tablegenerated
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// target code can use it in static initializers. The defaults need to be
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// initialized in this default ctor because some clients directly instantiate
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// MCSchedModel instead of using a generated itinerary.
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MCSchedModel(): IssueWidth(DefaultIssueWidth),
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MinLatency(DefaultMinLatency),
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LoadLatency(DefaultLoadLatency),
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HighLatency(DefaultHighLatency),
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ILPWindow(DefaultILPWindow),
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MispredictPenalty(DefaultMispredictPenalty),
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ProcID(0), ProcResourceTable(0), SchedClassTable(0),
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NumProcResourceKinds(0), NumSchedClasses(0),
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InstrItineraries(0) {
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(void)NumProcResourceKinds;
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(void)NumSchedClasses;
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}
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// Table-gen driven ctor.
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MCSchedModel(unsigned iw, int ml, unsigned ll, unsigned hl, unsigned ilp,
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unsigned mp, unsigned pi, const MCProcResourceDesc *pr,
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const MCSchedClassDesc *sc, unsigned npr, unsigned nsc,
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const InstrItinerary *ii):
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IssueWidth(iw), MinLatency(ml), LoadLatency(ll), HighLatency(hl),
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ILPWindow(ilp), MispredictPenalty(mp), ProcID(pi), ProcResourceTable(pr),
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SchedClassTable(sc), NumProcResourceKinds(npr), NumSchedClasses(nsc),
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InstrItineraries(ii) {}
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unsigned getProcessorID() const { return ProcID; }
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/// Does this machine model include instruction-level scheduling.
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bool hasInstrSchedModel() const { return SchedClassTable; }
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2012-11-06 07:10:38 +00:00
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unsigned getNumProcResourceKinds() const {
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return NumProcResourceKinds;
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}
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const MCProcResourceDesc *getProcResource(unsigned ProcResourceIdx) const {
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assert(hasInstrSchedModel() && "No scheduling machine model");
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assert(ProcResourceIdx < NumProcResourceKinds && "bad proc resource idx");
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return &ProcResourceTable[ProcResourceIdx];
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}
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const MCSchedClassDesc *getSchedClassDesc(unsigned SchedClassIdx) const {
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assert(hasInstrSchedModel() && "No scheduling machine model");
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assert(SchedClassIdx < NumSchedClasses && "bad scheduling class idx");
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return &SchedClassTable[SchedClassIdx];
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}
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};
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} // End llvm namespace
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#endif
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