llvm-mirror/lib/Target/Alpha/AlphaInstrInfo.h

//===- AlphaInstrInfo.h - Alpha Instruction Information ---------*- C++ -*-===//
//
//                     The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains the Alpha implementation of the TargetInstrInfo class.
//
//===----------------------------------------------------------------------===//

#ifndef ALPHAINSTRUCTIONINFO_H
#define ALPHAINSTRUCTIONINFO_H

#include "llvm/Target/TargetInstrInfo.h"
#include "AlphaRegisterInfo.h"

namespace llvm {

class AlphaInstrInfo : public TargetInstrInfoImpl {
  const AlphaRegisterInfo RI;
public:
  AlphaInstrInfo();

  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
  /// such, whenever a client has an instance of instruction info, it should
  /// always be able to get register info as well (through this method).
  ///
  virtual const AlphaRegisterInfo &getRegisterInfo() const { return RI; }

  /// Return true if the instruction is a register to register move and
  /// leave the source and dest operands in the passed parameters.
  ///
  virtual bool isMoveInstr(const MachineInstr &MI,
                           unsigned &SrcReg, unsigned &DstReg) const;
  
  virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
  virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
  
  virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
                            MachineBasicBlock *FBB,
                            const SmallVectorImpl<MachineOperand> &Cond) const;
  virtual bool copyRegToReg(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MI,
                            unsigned DestReg, unsigned SrcReg,
                            const TargetRegisterClass *DestRC,
                            const TargetRegisterClass *SrcRC) const;
  virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
                                   MachineBasicBlock::iterator MBBI,
                                   unsigned SrcReg, bool isKill, int FrameIndex,
                                   const TargetRegisterClass *RC) const;

  virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
                              SmallVectorImpl<MachineOperand> &Addr,
                              const TargetRegisterClass *RC,
                              SmallVectorImpl<MachineInstr*> &NewMIs) const;

  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
                                    MachineBasicBlock::iterator MBBI,
                                    unsigned DestReg, int FrameIndex,
                                    const TargetRegisterClass *RC) const;

  virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
                               SmallVectorImpl<MachineOperand> &Addr,
                               const TargetRegisterClass *RC,
                               SmallVectorImpl<MachineInstr*> &NewMIs) const;
  
  virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
                                          MachineInstr* MI,
                                          const SmallVectorImpl<unsigned> &Ops,
                                          int FrameIndex) const;

  virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
                                          MachineInstr* MI,
                                          const SmallVectorImpl<unsigned> &Ops,
                                          MachineInstr* LoadMI) const {
    return 0;
  }
  
  bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
                     MachineBasicBlock *&FBB,
                     SmallVectorImpl<MachineOperand> &Cond) const;
  unsigned RemoveBranch(MachineBasicBlock &MBB) const;
  void insertNoop(MachineBasicBlock &MBB, 
                  MachineBasicBlock::iterator MI) const;
  bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
  bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
};

}

#endif
Make file header comment consistent: extend the whole 80 cols to fill the line llvm-svn: 20039 2005-02-04 20:25:52 +00:00			`//===- AlphaInstrInfo.h - Alpha Instruction Information ---------- C++ --===//`
Remove trailing whitespace llvm-svn: 21424 2005-04-21 23:13:11 +00:00			`//`
Let me introduce you to the early stages of the llvm backend for the alpha processor llvm-svn: 19764 2005-01-22 23:41:55 +00:00			`// The LLVM Compiler Infrastructure`
			`//`
Remove attribution from file headers, per discussion on llvmdev. llvm-svn: 45418 2007-12-29 20:36:04 +00:00			`// This file is distributed under the University of Illinois Open Source`
			`// License. See LICENSE.TXT for details.`
Remove trailing whitespace llvm-svn: 21424 2005-04-21 23:13:11 +00:00			`//`
Let me introduce you to the early stages of the llvm backend for the alpha processor llvm-svn: 19764 2005-01-22 23:41:55 +00:00			`//===----------------------------------------------------------------------===//`
			`//`
			`// This file contains the Alpha implementation of the TargetInstrInfo class.`
			`//`
			`//===----------------------------------------------------------------------===//`

			`#ifndef ALPHAINSTRUCTIONINFO_H`
			`#define ALPHAINSTRUCTIONINFO_H`

			`#include "llvm/Target/TargetInstrInfo.h"`
			`#include "AlphaRegisterInfo.h"`

			`namespace llvm {`

Fix a problem where lib/Target/TargetInstrInfo.h would include and use a header file from libcodegen. This violates a layering order: codegen depends on target, not the other way around. The fix to this is to split TII into two classes, TII and TargetInstrInfoImpl, which defines stuff that depends on libcodegen. It is defined in libcodegen, where the base is not. llvm-svn: 45475 2008-01-01 01:03:04 +00:00			`class AlphaInstrInfo : public TargetInstrInfoImpl {`
Let me introduce you to the early stages of the llvm backend for the alpha processor llvm-svn: 19764 2005-01-22 23:41:55 +00:00			`const AlphaRegisterInfo RI;`
			`public:`
			`AlphaInstrInfo();`

			`/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As`
			`/// such, whenever a client has an instance of instruction info, it should`
			`/// always be able to get register info as well (through this method).`
			`///`
Change target-specific classes to use more precise static types. This eliminates the need for several awkward casts, including the last dynamic_cast under lib/Target. llvm-svn: 51091 2008-05-14 01:58:56 +00:00			`virtual const AlphaRegisterInfo &getRegisterInfo() const { return RI; }`
Let me introduce you to the early stages of the llvm backend for the alpha processor llvm-svn: 19764 2005-01-22 23:41:55 +00:00
			`/// Return true if the instruction is a register to register move and`
			`/// leave the source and dest operands in the passed parameters.`
			`///`
			`virtual bool isMoveInstr(const MachineInstr &MI,`
			`unsigned &SrcReg, unsigned &DstReg) const;`
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :) llvm-svn: 25913 2006-02-02 20:12:32 +00:00
			`virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;`
isStoreToStackSlot llvm-svn: 25925 2006-02-03 03:07:37 +00:00			`virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;`
implement uncond branch insertion so alpha works work branchfolding. llvm-svn: 31158 2006-10-24 16:41:36 +00:00
RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted. llvm-svn: 37192 2007-05-18 00:05:48 +00:00			`virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,`
implement uncond branch insertion so alpha works work branchfolding. llvm-svn: 31158 2006-10-24 16:41:36 +00:00			`MachineBasicBlock *FBB,`
Convert uses of std::vector in TargetInstrInfo to SmallVector. This change had to be propoagated down into all the targets and up into all clients of this API. llvm-svn: 54802 2008-08-14 22:49:33 +00:00			`const SmallVectorImpl<MachineOperand> &Cond) const;`
Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested was inserted or not. This allows bitcast in fast isel to properly handle the case where an appropriate reg-to-reg copy is not available. llvm-svn: 55375 2008-08-26 18:03:31 +00:00			`virtual bool copyRegToReg(MachineBasicBlock &MBB,`
Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the Machine-level API cleanup instigated by Chris. llvm-svn: 45470 2007-12-31 06:32:00 +00:00			`MachineBasicBlock::iterator MI,`
			`unsigned DestReg, unsigned SrcReg,`
			`const TargetRegisterClass *DestRC,`
			`const TargetRegisterClass *SrcRC) const;`
Move some more instruction creation methods from RegisterInfo into InstrInfo. llvm-svn: 45484 2008-01-01 21:11:32 +00:00			`virtual void storeRegToStackSlot(MachineBasicBlock &MBB,`
			`MachineBasicBlock::iterator MBBI,`
			`unsigned SrcReg, bool isKill, int FrameIndex,`
			`const TargetRegisterClass *RC) const;`

			`virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,`
			`SmallVectorImpl<MachineOperand> &Addr,`
			`const TargetRegisterClass *RC,`
			`SmallVectorImpl<MachineInstr*> &NewMIs) const;`

			`virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,`
			`MachineBasicBlock::iterator MBBI,`
			`unsigned DestReg, int FrameIndex,`
			`const TargetRegisterClass *RC) const;`

			`virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,`
			`SmallVectorImpl<MachineOperand> &Addr,`
			`const TargetRegisterClass *RC,`
			`SmallVectorImpl<MachineInstr*> &NewMIs) const;`
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672 2008-01-07 01:35:02 +00:00
It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned. llvm-svn: 46893 2008-02-08 21:20:40 +00:00			`virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,`
			`MachineInstr* MI,`
Const-ify several TargetInstrInfo methods. llvm-svn: 57622 2008-10-16 01:49:15 +00:00			`const SmallVectorImpl<unsigned> &Ops,`
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672 2008-01-07 01:35:02 +00:00			`int FrameIndex) const;`

It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned. llvm-svn: 46893 2008-02-08 21:20:40 +00:00			`virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,`
			`MachineInstr* MI,`
Const-ify several TargetInstrInfo methods. llvm-svn: 57622 2008-10-16 01:49:15 +00:00			`const SmallVectorImpl<unsigned> &Ops,`
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672 2008-01-07 01:35:02 +00:00			`MachineInstr* LoadMI) const {`
			`return 0;`
			`}`

Add all that branch mangling niftiness llvm-svn: 31313 2006-10-31 16:49:55 +00:00			`bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,`
			`MachineBasicBlock *&FBB,`
Convert uses of std::vector in TargetInstrInfo to SmallVector. This change had to be propoagated down into all the targets and up into all clients of this API. llvm-svn: 54802 2008-08-14 22:49:33 +00:00			`SmallVectorImpl<MachineOperand> &Cond) const;`
RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted. llvm-svn: 37192 2007-05-18 00:05:48 +00:00			`unsigned RemoveBranch(MachineBasicBlock &MBB) const;`
Add all that branch mangling niftiness llvm-svn: 31313 2006-10-31 16:49:55 +00:00			`void insertNoop(MachineBasicBlock &MBB,`
			`MachineBasicBlock::iterator MI) const;`
Const-ify several TargetInstrInfo methods. llvm-svn: 57622 2008-10-16 01:49:15 +00:00			`bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;`
Convert uses of std::vector in TargetInstrInfo to SmallVector. This change had to be propoagated down into all the targets and up into all clients of this API. llvm-svn: 54802 2008-08-14 22:49:33 +00:00			`bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;`
Let me introduce you to the early stages of the llvm backend for the alpha processor llvm-svn: 19764 2005-01-22 23:41:55 +00:00			`};`

			`}`

			`#endif`