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[TargetLowering] SimplifyDemandedBits - Cleanup ANY_EXTEND handling

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Match SIGN_EXTEND + ZERO_EXTEND handling - will be adding ANY_EXTEND_VECTOR_INREG support in a future patch.

llvm-svn: 363716
This commit is contained in:
Simon Pilgrim 2019-06-18 18:22:30 +00:00
parent 6baf5c5576
commit 0017bec24e
1 changed files with 8 additions and 2 deletions
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10
lib/CodeGen/SelectionDAG/TargetLowering.cpp
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@ -1440,12 +1440,18 @@ bool TargetLowering::SimplifyDemandedBits(
break;
}
case ISD::ANY_EXTEND: {
// TODO: Add ISD::ANY_EXTEND_VECTOR_INREG support.
SDValue Src = Op.getOperand(0);
unsigned InBits = Src.getScalarValueSizeInBits();
EVT SrcVT = Src.getValueType();
unsigned InBits = SrcVT.getScalarSizeInBits();
unsigned InElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1;
APInt InDemandedBits = DemandedBits.trunc(InBits);
if (SimplifyDemandedBits(Src, InDemandedBits, Known, TLO, Depth + 1))
APInt InDemandedElts = DemandedElts.zextOrSelf(InElts);
if (SimplifyDemandedBits(Src, InDemandedBits, InDemandedElts, Known, TLO,
Depth + 1))
return true;
assert(!Known.hasConflict() && "Bits known to be one AND zero?");
assert(Known.getBitWidth() == InBits && "Src width has changed?");
Known = Known.zext(BitWidth, false /* => any extend */);
break;
}