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[mips] Add capability to search in the forward direction for instructions that
can fill the delay slot. Currently, this is off by default. llvm-svn: 176320
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@ -47,11 +47,21 @@ static cl::opt<bool> SkipDelaySlotFiller(
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cl::desc("Skip MIPS' delay slot filling pass."),
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cl::Hidden);
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static cl::opt<bool> DisableForwardSearch(
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"disable-mips-df-forward-search",
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cl::init(true),
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cl::desc("Disallow MIPS delay filler to search forward."),
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cl::Hidden);
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namespace {
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class RegDefsUses {
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public:
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RegDefsUses(TargetMachine &TM);
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void init(const MachineInstr &MI);
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/// This function sets all caller-saved registers in Defs.
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void setCallerSaved(const MachineInstr &MI);
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bool update(const MachineInstr &MI, unsigned Begin, unsigned End);
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private:
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@ -65,13 +75,27 @@ namespace {
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BitVector Defs, Uses;
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};
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/// This class maintains memory dependence information.
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class MemDefsUses {
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/// Base class for inspecting loads and stores.
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class InspectMemInstr {
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public:
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virtual bool hasHazard(const MachineInstr &MI) = 0;
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virtual ~InspectMemInstr() {}
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};
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/// This subclass rejects any memory instructions.
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class NoMemInstr : public InspectMemInstr {
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public:
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virtual bool hasHazard(const MachineInstr &MI);
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};
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/// This subclass uses memory dependence information to determine whether a
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/// memory instruction can be moved to a delay slot.
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class MemDefsUses : public InspectMemInstr {
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public:
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MemDefsUses(const MachineFrameInfo *MFI);
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/// Return true if MI cannot be moved to delay slot.
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bool hasHazard(const MachineInstr &MI);
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virtual bool hasHazard(const MachineInstr &MI);
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private:
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/// Update Defs and Uses. Return true if there exist dependences that
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@ -127,15 +151,21 @@ namespace {
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/// and returns true if it isn't. It also updates memory and register
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/// dependence information.
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bool delayHasHazard(const MachineInstr &Candidate, RegDefsUses &RegDU,
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MemDefsUses &MemDU) const;
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InspectMemInstr &IM) const;
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/// This function searches range [Begin, End) for an instruction that can be
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/// moved to the delay slot. Returns true on success.
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template<typename IterTy>
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bool searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End,
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RegDefsUses &RegDU, MemDefsUses &MemDU, IterTy &Filler) const;
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RegDefsUses &RegDU, InspectMemInstr &IM, IterTy &Filler) const;
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bool searchBackward(MachineBasicBlock &MBB, Iter Slot, Iter &Filler) const;
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/// This function searches in the backward direction for an instruction that
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/// can be moved to the delay slot. Returns true on success.
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bool searchBackward(MachineBasicBlock &MBB, Iter Slot) const;
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/// This function searches MBB in the forward direction for an instruction
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/// that can be moved to the delay slot. Returns true on success.
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bool searchForward(MachineBasicBlock &MBB, Iter Slot) const;
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bool terminateSearch(const MachineInstr &Candidate) const;
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@ -168,6 +198,22 @@ void RegDefsUses::init(const MachineInstr &MI) {
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}
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}
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void RegDefsUses::setCallerSaved(const MachineInstr &MI) {
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assert(MI.isCall());
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// If MI is a call, add all caller-saved registers to Defs.
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BitVector CallerSavedRegs(TRI.getNumRegs(), true);
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CallerSavedRegs.reset(Mips::ZERO);
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CallerSavedRegs.reset(Mips::ZERO_64);
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for (const MCPhysReg *R = TRI.getCalleeSavedRegs(); *R; ++R)
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for (MCRegAliasIterator AI(*R, &TRI, true); AI.isValid(); ++AI)
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CallerSavedRegs.reset(*AI);
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Defs |= CallerSavedRegs;
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}
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bool RegDefsUses::update(const MachineInstr &MI, unsigned Begin, unsigned End) {
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BitVector NewDefs(TRI.getNumRegs()), NewUses(TRI.getNumRegs());
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bool HasHazard = false;
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@ -206,6 +252,11 @@ bool RegDefsUses::isRegInSet(const BitVector &RegSet, unsigned Reg) const {
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return false;
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}
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bool NoMemInstr::hasHazard(const MachineInstr &MI) {
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// Return true if MI accesses memory.
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return (MI.mayStore() || MI.mayLoad());
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}
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MemDefsUses::MemDefsUses(const MachineFrameInfo *MFI_)
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: MFI(MFI_), SeenLoad(false), SeenStore(false), SeenNoObjLoad(false),
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SeenNoObjStore(false), ForbidMemInstr(false) {}
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@ -295,17 +346,14 @@ bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
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++FilledSlots;
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Changed = true;
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Iter D;
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// Delay slot filling is disabled at -O0.
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if (!DisableDelaySlotFiller && (TM.getOptLevel() != CodeGenOpt::None) &&
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searchBackward(MBB, I, D)) {
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MBB.splice(llvm::next(I), &MBB, D);
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++UsefulSlots;
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} else
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BuildMI(MBB, llvm::next(I), I->getDebugLoc(), TII->get(Mips::NOP));
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(searchBackward(MBB, I) || searchForward(MBB, I)))
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continue;
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// Bundle the delay slot filler to the instruction with the delay slot.
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// Bundle the NOP to the instruction with the delay slot.
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BuildMI(MBB, llvm::next(I), I->getDebugLoc(), TII->get(Mips::NOP));
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MIBundleBuilder(MBB, I, llvm::next(llvm::next(I)));
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}
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@ -320,7 +368,7 @@ FunctionPass *llvm::createMipsDelaySlotFillerPass(MipsTargetMachine &tm) {
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template<typename IterTy>
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bool Filler::searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End,
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RegDefsUses &RegDU, MemDefsUses &MemDU,
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RegDefsUses &RegDU, InspectMemInstr& IM,
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IterTy &Filler) const {
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for (IterTy I = Begin; I != End; ++I) {
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// skip debug value
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@ -333,7 +381,7 @@ bool Filler::searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End,
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assert((!I->isCall() && !I->isReturn() && !I->isBranch()) &&
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"Cannot put calls, returns or branches in delay slot.");
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if (delayHasHazard(*I, RegDU, MemDU))
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if (delayHasHazard(*I, RegDU, IM))
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continue;
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Filler = I;
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@ -343,17 +391,38 @@ bool Filler::searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End,
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return false;
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}
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bool Filler::searchBackward(MachineBasicBlock &MBB, Iter Slot,
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Iter &Filler) const {
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bool Filler::searchBackward(MachineBasicBlock &MBB, Iter Slot) const {
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RegDefsUses RegDU(TM);
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MemDefsUses MemDU(MBB.getParent()->getFrameInfo());
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ReverseIter FillerReverse;
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ReverseIter Filler;
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RegDU.init(*Slot);
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if (searchRange(MBB, ReverseIter(Slot), MBB.rend(), RegDU, MemDU,
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FillerReverse)) {
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Filler = llvm::next(FillerReverse).base();
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if (searchRange(MBB, ReverseIter(Slot), MBB.rend(), RegDU, MemDU, Filler)) {
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MBB.splice(llvm::next(Slot), &MBB, llvm::next(Filler).base());
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MIBundleBuilder(MBB, Slot, llvm::next(llvm::next(Slot)));
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++UsefulSlots;
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return true;
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}
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return false;
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}
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bool Filler::searchForward(MachineBasicBlock &MBB, Iter Slot) const {
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// Can handle only calls.
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if (!Slot->isCall())
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return false;
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RegDefsUses RegDU(TM);
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NoMemInstr NM;
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Iter Filler;
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RegDU.setCallerSaved(*Slot);
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if (searchRange(MBB, llvm::next(Slot), MBB.end(), RegDU, NM, Filler)) {
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MBB.splice(llvm::next(Slot), &MBB, Filler);
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MIBundleBuilder(MBB, Slot, llvm::next(llvm::next(Slot)));
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++UsefulSlots;
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return true;
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}
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@ -361,10 +430,10 @@ bool Filler::searchBackward(MachineBasicBlock &MBB, Iter Slot,
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}
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bool Filler::delayHasHazard(const MachineInstr &Candidate, RegDefsUses &RegDU,
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MemDefsUses &MemDU) const {
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InspectMemInstr &IM) const {
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bool HasHazard = (Candidate.isImplicitDef() || Candidate.isKill());
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HasHazard |= MemDU.hasHazard(Candidate);
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HasHazard |= IM.hasHazard(Candidate);
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HasHazard |= RegDU.update(Candidate, 0, Candidate.getNumOperands());
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return HasHazard;
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@ -2,6 +2,8 @@
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; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=Default
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; RUN: llc -march=mipsel -O1 -relocation-model=static < %s | \
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; RUN: FileCheck %s -check-prefix=STATICO1
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; RUN: llc -march=mipsel -disable-mips-df-forward-search=false \
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; RUN: -relocation-model=static < %s | FileCheck %s -check-prefix=FORWARD
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define void @foo1() nounwind {
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entry:
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@ -99,3 +101,23 @@ entry:
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%add = add nsw i32 %1, %a
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ret i32 %add
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}
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; Test searchForward. Check that the second jal's slot is filled with another
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; instruction in the same block.
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;
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; FORWARD: foo10:
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; FORWARD: jal foo11
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; FORWARD: jal foo11
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; FORWARD-NOT: nop
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define void @foo10() nounwind {
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entry:
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tail call void @foo11() nounwind
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tail call void @foo11() nounwind
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store i32 0, i32* @g1, align 4
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tail call void @foo11() nounwind
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store i32 0, i32* @g1, align 4
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ret void
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}
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declare void @foo11()
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