mirror of
https://github.com/RPCS3/llvm-mirror.git
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[Target] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
llvm-svn: 305757
This commit is contained in:
Eugene Zelenko
parent
3d994828fb
commit
027b1deacd
@ -1,4 +1,4 @@
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//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
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//===- llvm/Target/TargetInstrInfo.h - Instruction Info ---------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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@ -14,36 +14,46 @@
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#ifndef LLVM_TARGET_TARGETINSTRINFO_H
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#define LLVM_TARGET_TARGETINSTRINFO_H
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/DenseMapInfo.h"
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#include "llvm/ADT/None.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineCombinerPattern.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/Support/BranchProbability.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include <cassert>
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#include <cstddef>
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#include <cstdint>
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#include <utility>
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#include <vector>
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namespace llvm {
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class DFAPacketizer;
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class InstrItineraryData;
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class LiveVariables;
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class MCAsmInfo;
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class MachineMemOperand;
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class MachineRegisterInfo;
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class MDNode;
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class MCAsmInfo;
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class MCInst;
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struct MCSchedModel;
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class MCSymbolRefExpr;
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class SDNode;
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class ScheduleHazardRecognizer;
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class SelectionDAG;
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class Module;
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class ScheduleDAG;
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class ScheduleHazardRecognizer;
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class SDNode;
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class SelectionDAG;
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class RegScavenger;
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class TargetRegisterClass;
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class TargetRegisterInfo;
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class TargetSubtargetInfo;
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class TargetSchedModel;
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class DFAPacketizer;
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class TargetSubtargetInfo;
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template<class T> class SmallVectorImpl;
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@ -52,8 +62,6 @@ template<class T> class SmallVectorImpl;
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/// TargetInstrInfo - Interface to description of machine instruction set
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///
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class TargetInstrInfo : public MCInstrInfo {
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TargetInstrInfo(const TargetInstrInfo &) = delete;
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void operator=(const TargetInstrInfo &) = delete;
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public:
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TargetInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u,
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unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u)
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@ -61,7 +69,8 @@ public:
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CallFrameDestroyOpcode(CFDestroyOpcode),
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CatchRetOpcode(CatchRetOpcode),
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ReturnOpcode(ReturnOpcode) {}
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TargetInstrInfo(const TargetInstrInfo &) = delete;
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TargetInstrInfo &operator=(const TargetInstrInfo &) = delete;
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virtual ~TargetInstrInfo();
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static bool isGenericOpcode(unsigned Opc) {
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@ -396,14 +405,17 @@ public:
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struct RegSubRegPair {
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unsigned Reg;
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unsigned SubReg;
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RegSubRegPair(unsigned Reg = 0, unsigned SubReg = 0)
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: Reg(Reg), SubReg(SubReg) {}
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};
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/// A pair composed of a pair of a register and a sub-register index,
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/// and another sub-register index.
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/// Used to give some type checking when modeling Reg:SubReg1, SubReg2.
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struct RegSubRegPairAndIdx : RegSubRegPair {
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unsigned SubIdx;
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RegSubRegPairAndIdx(unsigned Reg = 0, unsigned SubReg = 0,
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unsigned SubIdx = 0)
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: RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {}
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@ -469,7 +481,6 @@ public:
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RegSubRegPair &BaseReg,
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RegSubRegPairAndIdx &InsertedReg) const;
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/// Return true if two machine instructions would produce identical values.
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/// By default, this is only true when the two instructions
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/// are deemed identical except for defs. If this function is called when the
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@ -551,23 +562,19 @@ public:
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PRED_INVALID // Sentinel value
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};
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ComparePredicate Predicate;
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MachineOperand LHS;
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MachineOperand RHS;
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MachineBasicBlock *TrueDest;
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MachineBasicBlock *FalseDest;
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MachineInstr *ConditionDef;
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ComparePredicate Predicate = PRED_INVALID;
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MachineOperand LHS = MachineOperand::CreateImm(0);
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MachineOperand RHS = MachineOperand::CreateImm(0);
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MachineBasicBlock *TrueDest = nullptr;
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MachineBasicBlock *FalseDest = nullptr;
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MachineInstr *ConditionDef = nullptr;
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/// SingleUseCondition is true if ConditionDef is dead except for the
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/// branch(es) at the end of the basic block.
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///
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bool SingleUseCondition;
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bool SingleUseCondition = false;
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explicit MachineBranchPredicate()
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: Predicate(PRED_INVALID), LHS(MachineOperand::CreateImm(0)),
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RHS(MachineOperand::CreateImm(0)), TrueDest(nullptr),
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FalseDest(nullptr), ConditionDef(nullptr), SingleUseCondition(false) {
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}
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explicit MachineBranchPredicate() = default;
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};
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/// Analyze the branching code at the end of MBB and parse it into the
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@ -1117,7 +1124,6 @@ public:
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virtual void insertNoop(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const;
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/// Return the noop instruction to use for a noop.
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virtual void getNoop(MCInst &NopInst) const;
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@ -1621,16 +1627,18 @@ private:
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/// \brief Provide DenseMapInfo for TargetInstrInfo::RegSubRegPair.
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template<>
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struct DenseMapInfo<TargetInstrInfo::RegSubRegPair> {
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typedef DenseMapInfo<unsigned> RegInfo;
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using RegInfo = DenseMapInfo<unsigned>;
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static inline TargetInstrInfo::RegSubRegPair getEmptyKey() {
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return TargetInstrInfo::RegSubRegPair(RegInfo::getEmptyKey(),
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RegInfo::getEmptyKey());
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}
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static inline TargetInstrInfo::RegSubRegPair getTombstoneKey() {
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return TargetInstrInfo::RegSubRegPair(RegInfo::getTombstoneKey(),
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RegInfo::getTombstoneKey());
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}
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/// \brief Reuse getHashValue implementation from
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/// std::pair<unsigned, unsigned>.
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static unsigned getHashValue(const TargetInstrInfo::RegSubRegPair &Val) {
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@ -1638,6 +1646,7 @@ struct DenseMapInfo<TargetInstrInfo::RegSubRegPair> {
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std::make_pair(Val.Reg, Val.SubReg);
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return DenseMapInfo<std::pair<unsigned, unsigned>>::getHashValue(PairVal);
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}
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static bool isEqual(const TargetInstrInfo::RegSubRegPair &LHS,
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const TargetInstrInfo::RegSubRegPair &RHS) {
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return RegInfo::isEqual(LHS.Reg, RHS.Reg) &&
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@ -1,4 +1,4 @@
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//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
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//===- llvm/Target/TargetLowering.h - Target Lowering Info ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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@ -23,6 +23,7 @@
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#ifndef LLVM_TARGET_TARGETLOWERING_H
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#define LLVM_TARGET_TARGETLOWERING_H
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#include "llvm/ADT/APInt.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/STLExtras.h"
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@ -40,6 +41,7 @@
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#include "llvm/IR/CallingConv.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/IRBuilder.h"
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#include "llvm/IR/InlineAsm.h"
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#include "llvm/IR/Instruction.h"
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@ -66,10 +68,13 @@ namespace llvm {
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class BranchProbability;
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class CCState;
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class CCValAssign;
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class Constant;
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class FastISel;
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class FunctionLoweringInfo;
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class GlobalValue;
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class IntrinsicInst;
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struct KnownBits;
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class LLVMContext;
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class MachineBasicBlock;
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class MachineFunction;
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class MachineInstr;
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@ -78,6 +83,7 @@ class MachineLoop;
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class MachineRegisterInfo;
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class MCContext;
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class MCExpr;
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class Module;
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class TargetRegisterClass;
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class TargetLibraryInfo;
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class TargetRegisterInfo;
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@ -127,7 +133,7 @@ public:
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/// LegalizeKind holds the legalization kind that needs to happen to EVT
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/// in order to type-legalize it.
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typedef std::pair<LegalizeTypeAction, EVT> LegalizeKind;
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using LegalizeKind = std::pair<LegalizeTypeAction, EVT>;
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/// Enum that describes how the target represents true/false values.
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enum BooleanContent {
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@ -189,7 +195,7 @@ public:
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void setAttributes(ImmutableCallSite *CS, unsigned ArgIdx);
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};
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typedef std::vector<ArgListEntry> ArgListTy;
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using ArgListTy = std::vector<ArgListEntry>;
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virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC,
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ArgListTy &Args) const {};
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@ -211,8 +217,8 @@ public:
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/// NOTE: The TargetMachine owns TLOF.
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explicit TargetLoweringBase(const TargetMachine &TM);
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TargetLoweringBase(const TargetLoweringBase&) = delete;
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void operator=(const TargetLoweringBase&) = delete;
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TargetLoweringBase(const TargetLoweringBase &) = delete;
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TargetLoweringBase &operator=(const TargetLoweringBase &) = delete;
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virtual ~TargetLoweringBase() = default;
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protected:
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@ -2455,8 +2461,8 @@ class TargetLowering : public TargetLoweringBase {
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public:
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struct DAGCombinerInfo;
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TargetLowering(const TargetLowering&) = delete;
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void operator=(const TargetLowering&) = delete;
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TargetLowering(const TargetLowering &) = delete;
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TargetLowering &operator=(const TargetLowering &) = delete;
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/// NOTE: The TargetMachine owns TLOF.
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explicit TargetLowering(const TargetMachine &TM);
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@ -2772,7 +2778,6 @@ public:
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/// described by the Ins array, into the specified DAG. The implementation
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/// should fill in the InVals array with legal-type argument values, and
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/// return the resulting token chain value.
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///
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virtual SDValue LowerFormalArguments(
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SDValue /*Chain*/, CallingConv::ID /*CallConv*/, bool /*isVarArg*/,
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const SmallVectorImpl<ISD::InputArg> & /*Ins*/, const SDLoc & /*dl*/,
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@ -2786,7 +2791,7 @@ public:
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/// implementation.
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struct CallLoweringInfo {
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SDValue Chain;
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Type *RetTy;
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Type *RetTy = nullptr;
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bool RetSExt : 1;
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bool RetZExt : 1;
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bool IsVarArg : 1;
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@ -2794,30 +2799,28 @@ public:
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bool DoesNotReturn : 1;
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bool IsReturnValueUsed : 1;
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bool IsConvergent : 1;
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bool IsPatchPoint : 1;
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// IsTailCall should be modified by implementations of
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// TargetLowering::LowerCall that perform tail call conversions.
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bool IsTailCall;
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bool IsTailCall = false;
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unsigned NumFixedArgs;
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CallingConv::ID CallConv;
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unsigned NumFixedArgs = -1;
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CallingConv::ID CallConv = CallingConv::C;
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SDValue Callee;
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ArgListTy Args;
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SelectionDAG &DAG;
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SDLoc DL;
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ImmutableCallSite *CS;
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bool IsPatchPoint;
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ImmutableCallSite *CS = nullptr;
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SmallVector<ISD::OutputArg, 32> Outs;
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SmallVector<SDValue, 32> OutVals;
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SmallVector<ISD::InputArg, 32> Ins;
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SmallVector<SDValue, 4> InVals;
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CallLoweringInfo(SelectionDAG &DAG)
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: RetTy(nullptr), RetSExt(false), RetZExt(false), IsVarArg(false),
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IsInReg(false), DoesNotReturn(false), IsReturnValueUsed(true),
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IsConvergent(false), IsTailCall(false), NumFixedArgs(-1),
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CallConv(CallingConv::C), DAG(DAG), CS(nullptr), IsPatchPoint(false) {
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}
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: RetSExt(false), RetZExt(false), IsVarArg(false), IsInReg(false),
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DoesNotReturn(false), IsReturnValueUsed(true), IsConvergent(false),
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IsPatchPoint(false), DAG(DAG) {}
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CallLoweringInfo &setDebugLoc(const SDLoc &dl) {
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DL = dl;
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@ -3091,7 +3094,6 @@ public:
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return nullptr;
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}
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bool verifyReturnAddressArgumentIsConstant(SDValue Op,
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SelectionDAG &DAG) const;
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@ -3140,15 +3142,19 @@ public:
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/// Information about the constraint code, e.g. Register, RegisterClass,
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/// Memory, Other, Unknown.
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TargetLowering::ConstraintType ConstraintType;
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TargetLowering::ConstraintType ConstraintType = TargetLowering::C_Unknown;
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/// If this is the result output operand or a clobber, this is null,
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/// otherwise it is the incoming operand to the CallInst. This gets
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/// modified as the asm is processed.
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Value *CallOperandVal;
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Value *CallOperandVal = nullptr;
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/// The ValueType for the operand value.
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MVT ConstraintVT;
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MVT ConstraintVT = MVT::Other;
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/// Copy constructor for copying from a ConstraintInfo.
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AsmOperandInfo(InlineAsm::ConstraintInfo Info)
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: InlineAsm::ConstraintInfo(std::move(Info)) {}
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/// Return true of this is an input operand that is a matching constraint
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/// like "4".
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@ -3157,15 +3163,9 @@ public:
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/// If this is an input matching constraint, this method returns the output
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/// operand it matches.
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unsigned getMatchedOperand() const;
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/// Copy constructor for copying from a ConstraintInfo.
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AsmOperandInfo(InlineAsm::ConstraintInfo Info)
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: InlineAsm::ConstraintInfo(std::move(Info)),
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ConstraintType(TargetLowering::C_Unknown), CallOperandVal(nullptr),
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ConstraintVT(MVT::Other) {}
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};
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typedef std::vector<AsmOperandInfo> AsmOperandInfoVector;
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using AsmOperandInfoVector = std::vector<AsmOperandInfo>;
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/// Split up the constraint string from the inline assembly value into the
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/// specific constraints and their prefixes, and also tie in the associated
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@ -1,4 +1,4 @@
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//=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===//
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//==- Target/TargetRegisterInfo.h - Target Register Information --*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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@ -17,30 +17,35 @@
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#define LLVM_TARGET_TARGETREGISTERINFO_H
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/ADT/iterator_range.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineValueType.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/MC/LaneBitmask.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/Printable.h"
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#include <cassert>
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#include <cstdint>
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#include <functional>
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namespace llvm {
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class BitVector;
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class MachineFunction;
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class RegScavenger;
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template<class T> class SmallVectorImpl;
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class VirtRegMap;
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class raw_ostream;
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class LiveRegMatrix;
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class MachineFunction;
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class MachineInstr;
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class RegScavenger;
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class VirtRegMap;
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class TargetRegisterClass {
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public:
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typedef const MCPhysReg* iterator;
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typedef const MCPhysReg* const_iterator;
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typedef const TargetRegisterClass* const * sc_iterator;
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using iterator = const MCPhysReg *;
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using const_iterator = const MCPhysReg *;
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using sc_iterator = const TargetRegisterClass* const *;
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// Instance variables filled by tablegen, do not use!
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const MCRegisterClass *MC;
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@ -151,7 +156,6 @@ public:
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/// There exists SuperRC where:
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/// For all Reg in SuperRC:
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/// this->contains(Reg:Idx)
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///
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const uint16_t *getSuperRegIndices() const {
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return SuperRegIndices;
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}
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@ -182,7 +186,6 @@ public:
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/// other criteria.
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///
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/// By default, this method returns all registers in the class.
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///
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ArrayRef<MCPhysReg> getRawAllocationOrder(const MachineFunction &MF) const {
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return OrderFunc ? OrderFunc(MF) : makeArrayRef(begin(), getNumRegs());
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}
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@ -217,8 +220,9 @@ struct RegClassWeight {
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///
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class TargetRegisterInfo : public MCRegisterInfo {
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public:
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typedef const TargetRegisterClass * const * regclass_iterator;
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typedef const MVT::SimpleValueType* vt_iterator;
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using regclass_iterator = const TargetRegisterClass * const *;
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using vt_iterator = const MVT::SimpleValueType *;
|
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|
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private:
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const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen
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const char *const *SubRegIndexNames; // Names of subreg indexes.
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@ -236,8 +240,8 @@ protected:
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const LaneBitmask *SRILaneMasks,
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LaneBitmask CoveringLanes);
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virtual ~TargetRegisterInfo();
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public:
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public:
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// Register numbers can represent physical registers, virtual registers, and
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// sometimes stack slots. The unsigned values are divided into these ranges:
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//
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@ -510,7 +514,7 @@ public:
|
||||
/// Prior to adding the live-out mask to a stackmap or patchpoint
|
||||
/// instruction, provide the target the opportunity to adjust it (mainly to
|
||||
/// remove pseudo-registers that should be ignored).
|
||||
virtual void adjustStackMapLiveOutMask(uint32_t *Mask) const { }
|
||||
virtual void adjustStackMapLiveOutMask(uint32_t *Mask) const {}
|
||||
|
||||
/// Return a super-register of the specified register
|
||||
/// Reg so its sub-register of index SubIdx is Reg.
|
||||
@ -568,7 +572,6 @@ public:
|
||||
/// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has
|
||||
/// ssub_0:S0 - ssub_3:S3 subregs.
|
||||
/// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
|
||||
///
|
||||
unsigned composeSubRegIndices(unsigned a, unsigned b) const {
|
||||
if (!a) return b;
|
||||
if (!b) return a;
|
||||
@ -643,7 +646,6 @@ public:
|
||||
/// corresponding argument register class.
|
||||
///
|
||||
/// The function returns NULL if no register class can be found.
|
||||
///
|
||||
const TargetRegisterClass*
|
||||
getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
|
||||
const TargetRegisterClass *RCB, unsigned SubB,
|
||||
@ -654,7 +656,6 @@ public:
|
||||
//
|
||||
|
||||
/// Register class iterators
|
||||
///
|
||||
regclass_iterator regclass_begin() const { return RegClassBegin; }
|
||||
regclass_iterator regclass_end() const { return RegClassEnd; }
|
||||
iterator_range<regclass_iterator> regclasses() const {
|
||||
@ -909,7 +910,6 @@ public:
|
||||
/// Return true if the register was spilled, false otherwise.
|
||||
/// If this function does not spill the register, the scavenger
|
||||
/// will instead spill it to the emergency spill slot.
|
||||
///
|
||||
virtual bool saveScavengerRegister(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator I,
|
||||
MachineBasicBlock::iterator &UseMI,
|
||||
@ -968,7 +968,6 @@ public:
|
||||
ArrayRef<MCPhysReg> Exceptions = ArrayRef<MCPhysReg>()) const;
|
||||
};
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// SuperRegClassIterator
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -987,7 +986,7 @@ public:
|
||||
//
|
||||
class SuperRegClassIterator {
|
||||
const unsigned RCMaskWords;
|
||||
unsigned SubReg;
|
||||
unsigned SubReg = 0;
|
||||
const uint16_t *Idx;
|
||||
const uint32_t *Mask;
|
||||
|
||||
@ -998,9 +997,7 @@ public:
|
||||
const TargetRegisterInfo *TRI,
|
||||
bool IncludeSelf = false)
|
||||
: RCMaskWords((TRI->getNumRegClasses() + 31) / 32),
|
||||
SubReg(0),
|
||||
Idx(RC->getSuperRegIndices()),
|
||||
Mask(RC->getSubClassMask()) {
|
||||
Idx(RC->getSuperRegIndices()), Mask(RC->getSubClassMask()) {
|
||||
if (!IncludeSelf)
|
||||
++*this;
|
||||
}
|
||||
@ -1039,12 +1036,12 @@ class BitMaskClassIterator {
|
||||
/// Base index of CurrentChunk.
|
||||
/// In other words, the number of bit we read to get at the
|
||||
/// beginning of that chunck.
|
||||
unsigned Base;
|
||||
unsigned Base = 0;
|
||||
/// Adjust base index of CurrentChunk.
|
||||
/// Base index + how many bit we read within CurrentChunk.
|
||||
unsigned Idx;
|
||||
unsigned Idx = 0;
|
||||
/// Current register class ID.
|
||||
unsigned ID;
|
||||
unsigned ID = 0;
|
||||
/// Mask we are iterating over.
|
||||
const uint32_t *Mask;
|
||||
/// Current chunk of the Mask we are traversing.
|
||||
@ -1098,8 +1095,7 @@ public:
|
||||
///
|
||||
/// \pre \p Mask != nullptr
|
||||
BitMaskClassIterator(const uint32_t *Mask, const TargetRegisterInfo &TRI)
|
||||
: NumRegClasses(TRI.getNumRegClasses()), Base(0), Idx(0), ID(0),
|
||||
Mask(Mask), CurrentChunk(*Mask) {
|
||||
: NumRegClasses(TRI.getNumRegClasses()), Mask(Mask), CurrentChunk(*Mask) {
|
||||
// Move to the first ID.
|
||||
moveToNextID();
|
||||
}
|
||||
@ -1151,6 +1147,6 @@ Printable PrintRegUnit(unsigned Unit, const TargetRegisterInfo *TRI);
|
||||
/// registers on a \ref raw_ostream.
|
||||
Printable PrintVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI);
|
||||
|
||||
} // End llvm namespace
|
||||
} // end namespace llvm
|
||||
|
||||
#endif
|
||||
#endif // LLVM_TARGET_TARGETREGISTERINFO_H
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
//==-- llvm/Target/TargetSubtargetInfo.h - Target Information ----*- C++ -*-==//
|
||||
//===- llvm/Target/TargetSubtargetInfo.h - Target Information ---*- C++ -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
@ -20,21 +20,29 @@
|
||||
#include "llvm/CodeGen/PBQPRAConstraint.h"
|
||||
#include "llvm/CodeGen/ScheduleDAGMutation.h"
|
||||
#include "llvm/CodeGen/SchedulerRegistry.h"
|
||||
#include "llvm/MC/MCInst.h"
|
||||
#include "llvm/MC/MCSubtargetInfo.h"
|
||||
#include "llvm/Support/CodeGen.h"
|
||||
#include <memory>
|
||||
#include <vector>
|
||||
|
||||
|
||||
namespace llvm {
|
||||
|
||||
class CallLowering;
|
||||
class InstrItineraryData;
|
||||
struct InstrStage;
|
||||
class InstructionSelector;
|
||||
class LegalizerInfo;
|
||||
class MachineInstr;
|
||||
struct MachineSchedPolicy;
|
||||
struct MCReadAdvanceEntry;
|
||||
struct MCWriteLatencyEntry;
|
||||
struct MCWriteProcResEntry;
|
||||
class RegisterBankInfo;
|
||||
class SDep;
|
||||
class SelectionDAGTargetInfo;
|
||||
struct SubtargetFeatureKV;
|
||||
struct SubtargetInfoKV;
|
||||
class SUnit;
|
||||
class TargetFrameLowering;
|
||||
class TargetInstrInfo;
|
||||
@ -42,7 +50,7 @@ class TargetLowering;
|
||||
class TargetRegisterClass;
|
||||
class TargetRegisterInfo;
|
||||
class TargetSchedModel;
|
||||
struct MachineSchedPolicy;
|
||||
class Triple;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
///
|
||||
@ -64,13 +72,13 @@ protected: // Can only create subclasses...
|
||||
public:
|
||||
// AntiDepBreakMode - Type of anti-dependence breaking that should
|
||||
// be performed before post-RA scheduling.
|
||||
typedef enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL } AntiDepBreakMode;
|
||||
typedef SmallVectorImpl<const TargetRegisterClass *> RegClassVector;
|
||||
using AntiDepBreakMode = enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL };
|
||||
using RegClassVector = SmallVectorImpl<const TargetRegisterClass *>;
|
||||
|
||||
TargetSubtargetInfo() = delete;
|
||||
TargetSubtargetInfo(const TargetSubtargetInfo &) = delete;
|
||||
void operator=(const TargetSubtargetInfo &) = delete;
|
||||
virtual ~TargetSubtargetInfo();
|
||||
TargetSubtargetInfo &operator=(const TargetSubtargetInfo &) = delete;
|
||||
~TargetSubtargetInfo() override;
|
||||
|
||||
virtual bool isXRaySupported() const { return false; }
|
||||
|
||||
@ -112,7 +120,6 @@ public:
|
||||
|
||||
/// getRegisterInfo - If register information is available, return it. If
|
||||
/// not, return null.
|
||||
///
|
||||
virtual const TargetRegisterInfo *getRegisterInfo() const { return nullptr; }
|
||||
|
||||
/// If the information for the register banks is available, return it.
|
||||
@ -121,7 +128,6 @@ public:
|
||||
|
||||
/// getInstrItineraryData - Returns instruction itinerary data for the target
|
||||
/// or specific subtarget.
|
||||
///
|
||||
virtual const InstrItineraryData *getInstrItineraryData() const {
|
||||
return nullptr;
|
||||
}
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
//===- TargetRegisterInfo.cpp - Target Register Information Implementation ===//
|
||||
//==- TargetRegisterInfo.cpp - Target Register Information Implementation --==//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
@ -11,17 +11,27 @@
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "llvm/Target/TargetRegisterInfo.h"
|
||||
#include "llvm/ADT/ArrayRef.h"
|
||||
#include "llvm/ADT/BitVector.h"
|
||||
#include "llvm/ADT/STLExtras.h"
|
||||
#include "llvm/CodeGen/MachineFrameInfo.h"
|
||||
#include "llvm/CodeGen/MachineFunction.h"
|
||||
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
||||
#include "llvm/CodeGen/MachineValueType.h"
|
||||
#include "llvm/CodeGen/VirtRegMap.h"
|
||||
#include "llvm/IR/Attributes.h"
|
||||
#include "llvm/IR/Function.h"
|
||||
#include "llvm/MC/MCRegisterInfo.h"
|
||||
#include "llvm/Support/Compiler.h"
|
||||
#include "llvm/Support/Debug.h"
|
||||
#include "llvm/Support/Format.h"
|
||||
#include "llvm/Support/MathExtras.h"
|
||||
#include "llvm/Support/Printable.h"
|
||||
#include "llvm/Support/raw_ostream.h"
|
||||
#include "llvm/Target/TargetFrameLowering.h"
|
||||
#include "llvm/Target/TargetRegisterInfo.h"
|
||||
#include "llvm/Target/TargetSubtargetInfo.h"
|
||||
#include <cassert>
|
||||
#include <utility>
|
||||
|
||||
#define DEBUG_TYPE "target-reg-info"
|
||||
|
||||
@ -38,7 +48,7 @@ TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
|
||||
CoveringLanes(SRICoveringLanes) {
|
||||
}
|
||||
|
||||
TargetRegisterInfo::~TargetRegisterInfo() {}
|
||||
TargetRegisterInfo::~TargetRegisterInfo() = default;
|
||||
|
||||
void TargetRegisterInfo::markSuperRegs(BitVector &RegisterSet, unsigned Reg)
|
||||
const {
|
||||
@ -126,7 +136,7 @@ Printable PrintVRegOrUnit(unsigned Unit, const TargetRegisterInfo *TRI) {
|
||||
});
|
||||
}
|
||||
|
||||
} // End of llvm namespace
|
||||
} // end namespace llvm
|
||||
|
||||
/// getAllocatableClass - Return the maximal subclass of the given register
|
||||
/// class that is alloctable, or NULL.
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
//===-- TargetSubtargetInfo.cpp - General Target Information ---------------==//
|
||||
//===- TargetSubtargetInfo.cpp - General Target Information ----------------==//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
@ -11,15 +11,17 @@
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "llvm/Target/TargetSubtargetInfo.h"
|
||||
#include "llvm/ADT/Optional.h"
|
||||
#include "llvm/CodeGen/MachineInstr.h"
|
||||
#include "llvm/CodeGen/TargetSchedule.h"
|
||||
#include "llvm/MC/MCInst.h"
|
||||
#include "llvm/Target/TargetSubtargetInfo.h"
|
||||
#include "llvm/Support/Format.h"
|
||||
#include "llvm/Support/raw_ostream.h"
|
||||
#include <string>
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// TargetSubtargetInfo Class
|
||||
//
|
||||
TargetSubtargetInfo::TargetSubtargetInfo(
|
||||
const Triple &TT, StringRef CPU, StringRef FS,
|
||||
ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD,
|
||||
@ -29,7 +31,7 @@ TargetSubtargetInfo::TargetSubtargetInfo(
|
||||
: MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched, WPR, WL, RA, IS, OC, FP) {
|
||||
}
|
||||
|
||||
TargetSubtargetInfo::~TargetSubtargetInfo() {}
|
||||
TargetSubtargetInfo::~TargetSubtargetInfo() = default;
|
||||
|
||||
bool TargetSubtargetInfo::enableAtomicExpand() const {
|
||||
return true;
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
//===-- HexagonSubtarget.cpp - Hexagon Subtarget Information --------------===//
|
||||
//===- HexagonSubtarget.cpp - Hexagon Subtarget Information ---------------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
@ -11,13 +11,23 @@
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "HexagonSubtarget.h"
|
||||
#include "Hexagon.h"
|
||||
#include "HexagonInstrInfo.h"
|
||||
#include "HexagonRegisterInfo.h"
|
||||
#include "HexagonSubtarget.h"
|
||||
#include "llvm/ADT/STLExtras.h"
|
||||
#include "llvm/ADT/SmallSet.h"
|
||||
#include "llvm/ADT/SmallVector.h"
|
||||
#include "llvm/ADT/StringRef.h"
|
||||
#include "MCTargetDesc/HexagonMCTargetDesc.h"
|
||||
#include "llvm/CodeGen/MachineInstr.h"
|
||||
#include "llvm/CodeGen/MachineOperand.h"
|
||||
#include "llvm/CodeGen/ScheduleDAG.h"
|
||||
#include "llvm/CodeGen/ScheduleDAGInstrs.h"
|
||||
#include "llvm/Support/CommandLine.h"
|
||||
#include "llvm/Support/ErrorHandling.h"
|
||||
#include <algorithm>
|
||||
#include <cassert>
|
||||
#include <map>
|
||||
|
||||
using namespace llvm;
|
||||
@ -119,9 +129,7 @@ HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
|
||||
HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU,
|
||||
StringRef FS, const TargetMachine &TM)
|
||||
: HexagonGenSubtargetInfo(TT, CPU, FS), CPUString(CPU),
|
||||
InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
|
||||
FrameLowering() {
|
||||
|
||||
InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this) {
|
||||
initializeEnvironment();
|
||||
|
||||
// Initialize scheduling itinerary for the specified CPU.
|
||||
@ -196,7 +204,6 @@ void HexagonSubtarget::adjustSchedDependency(SUnit *Src, SUnit *Dst,
|
||||
updateLatency(*SrcInst, *DstInst, Dep);
|
||||
}
|
||||
|
||||
|
||||
void HexagonSubtarget::HexagonDAGMutation::apply(ScheduleDAGInstrs *DAG) {
|
||||
for (auto &SU : DAG->SUnits) {
|
||||
if (!SU.isInstr())
|
||||
@ -240,18 +247,18 @@ void HexagonSubtarget::HexagonDAGMutation::apply(ScheduleDAGInstrs *DAG) {
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void HexagonSubtarget::getPostRAMutations(
|
||||
std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
|
||||
Mutations.push_back(make_unique<HexagonSubtarget::HexagonDAGMutation>());
|
||||
std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
|
||||
Mutations.push_back(
|
||||
llvm::make_unique<HexagonSubtarget::HexagonDAGMutation>());
|
||||
}
|
||||
|
||||
void HexagonSubtarget::getSMSMutations(
|
||||
std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
|
||||
Mutations.push_back(make_unique<HexagonSubtarget::HexagonDAGMutation>());
|
||||
std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
|
||||
Mutations.push_back(
|
||||
llvm::make_unique<HexagonSubtarget::HexagonDAGMutation>());
|
||||
}
|
||||
|
||||
|
||||
// Pin the vtable to this file.
|
||||
void HexagonSubtarget::anchor() {}
|
||||
|
||||
@ -447,4 +454,3 @@ unsigned HexagonSubtarget::getL1PrefetchDistance() const {
|
||||
bool HexagonSubtarget::enableSubRegLiveness() const {
|
||||
return EnableSubregLiveness;
|
||||
}
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
//===-- HexagonSubtarget.h - Define Subtarget for the Hexagon ---*- C++ -*-===//
|
||||
//===- HexagonSubtarget.h - Define Subtarget for the Hexagon ----*- C++ -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
@ -15,12 +15,17 @@
|
||||
#define LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
|
||||
|
||||
#include "HexagonFrameLowering.h"
|
||||
#include "HexagonISelLowering.h"
|
||||
#include "HexagonInstrInfo.h"
|
||||
#include "HexagonISelLowering.h"
|
||||
#include "HexagonSelectionDAGInfo.h"
|
||||
#include "llvm/Target/TargetMachine.h"
|
||||
#include "llvm/ADT/SmallSet.h"
|
||||
#include "llvm/ADT/StringRef.h"
|
||||
#include "llvm/CodeGen/ScheduleDAGMutation.h"
|
||||
#include "llvm/MC/MCInstrItineraries.h"
|
||||
#include "llvm/Target/TargetSubtargetInfo.h"
|
||||
#include <memory>
|
||||
#include <string>
|
||||
#include <vector>
|
||||
|
||||
#define GET_SUBTARGETINFO_HEADER
|
||||
#include "HexagonGenSubtargetInfo.inc"
|
||||
@ -30,6 +35,12 @@
|
||||
|
||||
namespace llvm {
|
||||
|
||||
class MachineInstr;
|
||||
class SDep;
|
||||
class SUnit;
|
||||
class TargetMachine;
|
||||
class Triple;
|
||||
|
||||
class HexagonSubtarget : public HexagonGenSubtargetInfo {
|
||||
virtual void anchor();
|
||||
|
||||
@ -57,6 +68,7 @@ private:
|
||||
HexagonSelectionDAGInfo TSInfo;
|
||||
HexagonFrameLowering FrameLowering;
|
||||
InstrItineraryData InstrItins;
|
||||
|
||||
void initializeEnvironment();
|
||||
|
||||
public:
|
||||
@ -108,6 +120,7 @@ public:
|
||||
|
||||
bool useBSBScheduling() const { return UseBSBScheduling; }
|
||||
bool enableMachineScheduler() const override;
|
||||
|
||||
// Always use the TargetLowering default scheduler.
|
||||
// FIXME: This will use the vliw scheduler which is probably just hurting
|
||||
// compiler time and will be removed eventually anyway.
|
||||
@ -124,6 +137,7 @@ public:
|
||||
unsigned getSmallDataThreshold() const {
|
||||
return Hexagon_SMALL_DATA_THRESHOLD;
|
||||
}
|
||||
|
||||
const HexagonArchEnum &getHexagonArchVersion() const {
|
||||
return HexagonArchVersion;
|
||||
}
|
||||
@ -155,4 +169,4 @@ private:
|
||||
|
||||
} // end namespace llvm
|
||||
|
||||
#endif
|
||||
#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
|
||||
|
||||
Loading…
Reference in New Issue
Block a user