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reinstate my patch: the miscompile was caused by an inverted branch in the
'and' case. llvm-svn: 121695
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@ -1909,13 +1909,15 @@ static bool SimplifyBranchOnICmpChain(BranchInst *BI, const TargetData *TD) {
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// then we evaluate them with an explicit branch first. Split the block
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// right before the condbr to handle it.
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if (ExtraCase) {
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return false;
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BasicBlock *NewBB = BB->splitBasicBlock(BI, "switch.early.test");
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// Remove the uncond branch added to the old block.
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TerminatorInst *OldTI = BB->getTerminator();
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BranchInst::Create(EdgeBB, NewBB, ExtraCase, OldTI);
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if (TrueWhenEqual)
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BranchInst::Create(EdgeBB, NewBB, ExtraCase, OldTI);
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else
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BranchInst::Create(NewBB, EdgeBB, ExtraCase, OldTI);
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OldTI->eraseFromParent();
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// If there are PHI nodes in EdgeBB, then we need to add a new entry to them
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@ -1955,6 +1957,7 @@ static bool SimplifyBranchOnICmpChain(BranchInst *BI, const TargetData *TD) {
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// Erase the old branch instruction.
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EraseTerminatorInstAndDCECond(BI);
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return true;
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}
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@ -168,13 +168,13 @@ if.end: ; preds = %entry
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ret void
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; CHECK: @test7
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; HECK: %cmp = icmp ult i32 %x, 32
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; HECK: br i1 %cmp, label %if.then, label %switch.early.test
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; HECK: switch.early.test:
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; HECK: switch i8 %c, label %if.end [
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; HECK: i8 99, label %if.then
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; HECK: i8 97, label %if.then
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; HECK: ]
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; CHECK: %cmp = icmp ult i32 %x, 32
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; CHECK: br i1 %cmp, label %if.then, label %switch.early.test
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; CHECK: switch.early.test:
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; CHECK: switch i8 %c, label %if.end [
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; CHECK: i8 99, label %if.then
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; CHECK: i8 97, label %if.then
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; CHECK: ]
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}
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define i32 @test8(i8 zeroext %c, i32 %x, i1 %C) nounwind ssp noredzone {
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@ -197,12 +197,12 @@ if.end: ; preds = %entry
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ret i32 0
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; CHECK: @test8
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; HECK: switch.early.test:
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; HECK: switch i8 %c, label %if.end [
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; HECK: i8 99, label %if.then
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; HECK: i8 97, label %if.then
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; HECK: ]
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; HECK: %A = phi i32 [ 0, %entry ], [ 42, %switch.early.test ], [ 42, %N ], [ 42, %switch.early.test ]
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; CHECK: switch.early.test:
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; CHECK: switch i8 %c, label %if.end [
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; CHECK: i8 99, label %if.then
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; CHECK: i8 97, label %if.then
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; CHECK: ]
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; CHECK: %A = phi i32 [ 0, %entry ], [ 42, %switch.early.test ], [ 42, %N ], [ 42, %switch.early.test ]
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}
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;; This is "Example 7" from http://blog.regehr.org/archives/320
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@ -254,20 +254,41 @@ lor.end: ; preds = %lor.rhs, %lor.lhs.f
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; CHECK: @test9
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; CHECK: %cmp = icmp ult i8 %c, 33
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; HECK: br i1 %cmp, label %lor.end, label %switch.early.test
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; CHECK: br i1 %cmp, label %lor.end, label %switch.early.test
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; HECK: switch.early.test:
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; HECK: switch i8 %c, label %lor.rhs [
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; HECK: i8 46, label %lor.end
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; HECK: i8 44, label %lor.end
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; HECK: i8 58, label %lor.end
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; HECK: i8 59, label %lor.end
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; HECK: i8 60, label %lor.end
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; HECK: i8 62, label %lor.end
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; HECK: i8 34, label %lor.end
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; HECK: i8 92, label %lor.end
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; HECK: i8 39, label %lor.end
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; HECK: ]
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; CHECK: switch.early.test:
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; CHECK: switch i8 %c, label %lor.rhs [
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; CHECK: i8 46, label %lor.end
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; CHECK: i8 44, label %lor.end
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; CHECK: i8 58, label %lor.end
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; CHECK: i8 59, label %lor.end
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; CHECK: i8 60, label %lor.end
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; CHECK: i8 62, label %lor.end
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; CHECK: i8 34, label %lor.end
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; CHECK: i8 92, label %lor.end
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; CHECK: i8 39, label %lor.end
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; CHECK: ]
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}
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define i32 @test10(i32 %mode, i1 %Cond) {
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%A = icmp ne i32 %mode, 0
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%B = icmp ne i32 %mode, 51
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%C = and i1 %A, %B
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%D = and i1 %C, %Cond
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br i1 %D, label %T, label %F
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T:
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ret i32 123
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F:
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ret i32 324
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; CHECK: @test10
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; CHECK: br i1 %Cond, label %switch.early.test, label %F
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; CHECK:switch.early.test:
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; CHECK: switch i32 %mode, label %T [
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; CHECK: i32 51, label %F
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; CHECK: i32 0, label %F
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; CHECK: ]
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}
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