RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-12-28 22:43:29 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

- Teach TBB / TBH offset limits are 510 and 131070 respectively since the offset

Browse Source 
is scaled by two.
- Teach GetInstSizeInBytes about TBB and TBH.

llvm-svn: 77701
This commit is contained in:
Evan Cheng 2009-07-31 18:28:05 +00:00
parent 4d1b33e52e
commit 038a564156
2 changed files with 14 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -446,9 +446,14 @@ unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
case ARM::BR_JTr:
case ARM::BR_JTm:
case ARM::BR_JTadd:
case ARM::t2BR_JT: {
case ARM::t2BR_JT:
case ARM::t2TBB:
case ARM::t2TBH: {
// These are jumptable branches, i.e. a branch followed by an inlined
// jumptable. The size is 4 + 4 * number of entries.
// jumptable. The size is 4 + 4 * number of entries. For TBB, each
// entry is one byte; TBH two byte each.
unsigned EntrySize = (MI->getOpcode() == ARM::t2TBB)
? 1 : ((MI->getOpcode() == ARM::t2TBH) ? 2 : 4);
unsigned NumOps = TID.getNumOperands();
MachineOperand JTOP =
MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
@ -463,7 +468,7 @@ unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
// FIXME: If we know the size of the function is less than (1 << 16) *2
// bytes, we can use 16-bit entries instead. Then there won't be an
// alignment issue.
return getNumJTEntries(JT, JTI) * 4 + (IsThumb1JT ? 2 : 4);
return getNumJTEntries(JT, JTI) * EntrySize + (IsThumb1JT ? 2 : 4);
}
default:
// Otherwise, pseudo-instruction sizes are zero.

12
lib/Target/ARM/ARMConstantIslandPass.cpp
View File

@ -237,10 +237,10 @@ bool ARMConstantIslands::runOnMachineFunction(MachineFunction &MF) {
// the numbers agree with the position of the block in the function.
MF.RenumberBlocks();
// Thumb1 functions containing constant pools get 2-byte alignment.
// Thumb1 functions containing constant pools get 4-byte alignment.
// This is so we can keep exact track of where the alignment padding goes.
// Set default. Thumb1 function is 1-byte aligned, ARM and Thumb2 are 2-byte
// Set default. Thumb1 function is 2-byte aligned, ARM and Thumb2 are 4-byte
// aligned.
AFI->setAlign(isThumb1 ? 1U : 2U);
@ -1360,10 +1360,9 @@ bool ARMConstantIslands::OptimizeThumb2JumpTables(MachineFunction &MF) {
unsigned DstOffset = BBOffsets[MBB->getNumber()];
// Negative offset is not ok. FIXME: We should change BB layout to make
// sure all the branches are forward.
if (ByteOk && !OffsetIsInRange(JTOffset, DstOffset, (1<<8)-1, false))
if (ByteOk && (DstOffset - JTOffset) > ((1<<8)-1)*2)
ByteOk = false;
if (HalfWordOk &&
!OffsetIsInRange(JTOffset, DstOffset, (1<<16)-1, false))
if (HalfWordOk && (DstOffset - JTOffset) > ((1<<16)-1)*2)
HalfWordOk = false;
if (!ByteOk && !HalfWordOk)
break;
@ -1415,7 +1414,8 @@ bool ARMConstantIslands::OptimizeThumb2JumpTables(MachineFunction &MF) {
.addReg(IdxReg, getKillRegState(IdxRegKill))
.addJumpTableIndex(JTI, JTOP.getTargetFlags())
.addImm(MI->getOperand(JTOpIdx+1).getImm()));
// FIXME: Insert an "ALIGN" instruction to ensure the next instruction
// is 2-byte aligned. For now, asm printer will fix it up.
AddrMI->eraseFromParent();
if (LeaMI)
LeaMI->eraseFromParent();